AD7720BRU Fast Delivery |IC PHOENIX CO.,LIMITED

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AD7720BRU
CMOS Sigma-Delta Modulator
REV.0
CMOS Sigma-Delta Modulator
FUNCTIONAL BLOCK DIAGRAMFEATURES
12.5 MHz Master Clock Frequency
0 V to +2.5 V or 61.25 V Input Range
Single Bit Output Stream
90 dB Dynamic Range
Power Supplies: AVDD, DVDD: +5 V6 5%
On-Chip 2.5 V Voltage Reference
28-Lead TSSOP
GENERAL DESCRIPTION
This device is a 7th order sigma-delta modulator that converts
the analog input signal into a high speed 1-bit data stream. The
part operates from a +5 V supply and accepts a differential input
range of 0 V to +2.5 V or ±1.25 V centered about a common-
mode bias. The analog input is continuously sampled by the
analog modulator, eliminating the need for external sample and
hold circuitry. The input information is contained in the output
stream as a density of ones. The original information can be
reconstructed with an appropriate digital filter.
The part provides an accurate on-chip 2.5 V reference. A refer-
ence input/output function is provided to allow either the inter-
nal reference or an external system reference to be used as the
reference source for the part.
The device is offered in a 28-lead TSSOP package and designed
to operate from –40°C to +85°C.
AVDDAGNDDVDDDGNDREF1
REF2
DATA
SCLK
XTAL1/MCLK
XTAL2
DVAL
RESETO
RESET
VIN(+)
VIN(–)
MZERO
BIP
STBY
AD7720–SPECIFICATIONS1(AVDD = +5 V 6 5%; DVDD = +5 V 6 5%; AGND = DGND = 0 V, fMCLK = 12.5 MHz,
REF2=+2.5 V; TA = TMIN to TMIN, unless otherwise noted)
AD7720
LOGIC OUTPUTS
POWER SUPPLIES
NOTESOperating temperature range is as follows:B Version: –40°C to +85°C.Gain Error excludes reference error. The modulator gain is calibrated w.r.t. the voltage on the REF2 pin.Applies after calibration at temperature of interest.Measurement Bandwidth = 0.5 × fMCLK; Input Level = –0.05 dB.TA = +25°C to +85°C/TA = TMIN to TMAX.
Specifications subject to change without notice.
BIT STREAM
BANDWIDTH = 90.625 kHz
TRANSITION = 292.969kHz
ATTENUATION = 120dB
COEFFICIENTS = 384
16-BIT
OUTPUT
BANDWIDTH = 90.625 kHz
TRANSITION = 104.687kHz
ATTENUATION = 90dB
COEFFICIENTS = 151
Figure 1.Digital Filter (Consists of 2 FIR Filters). This filter is implemented on the AD7722.
AD7720
TIMING CHARACTERISTICS(AVDD = +5 V 6 5%; DVDD = +5 V 6 5%; AGND = DGND = 0 V, REF2=+2.5 V unless otherwise noted)
NOTE
Guaranteed by design.
IOH
200A
+1.6V
OUTPUT
PIN
Figure 2.Load Circuit for Access Time and Bus Relinquish Time
Figure 3.Data Timing
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7720 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Input Voltage to DGND . . –0.3 V to DVDD + 0.3 V
Analog Input Voltage to AGND . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . ±10 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
TSSOP Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 120°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latchup.
PIN CONFIGURATION
ORDERING GUIDE
NC = NO CONNECT
SCLK
DATA
MZERO
BIP
REF2
AGND
STBY
DGND
DVAL
XTAL1/MCLK
XTAL2
VIN(–)
AVDD
REF1
AVDD
RESET
VIN(+)
AGND
RESETO
DGND
AGND
DVDD
AGND
AGND
AGND
AD7720
PIN FUNCTION DESCRIPTIONS
TERMINOLOGY (IDEAL FIR FILTER USED WITH AD7720
[FIGURE 1])
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale (not to be con-
fused with bipolar zero), a point 0.5 LSB below the first code
transition (100...00 to 100...01 in bipolar mode and
000...00 to 000...01 in unipolar mode) and full scale, a
point 0.5 LSB above the last code transition (011...10 to
011...11 in bipolar mode and 111...10 to 111...11 in
unipolar mode). The error is expressed in LSBs.
Differential Nonlinearity
This is the difference between the measured and the ideal 1LSB
change between two adjacent codes in the ADC.
Common-Mode Rejection Ratio
The ability of a device to reject the effect of a voltage applied to
both input terminals simultaneously—often through variation of
a ground level—is specified as a common-mode rejection ratio.
CMRR is the ratio of gain for the differential signal to the gain
for the common-mode signal.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal VIN(+) voltage which is (VIN(–) + 0.5 LSB)
when operating in the unipolar mode.
Bipolar Offset Error
This is the deviation of the midscale transition (111...11
to 000...00) from the ideal VIN(+) voltage which is (VIN(–)
–0.5 LSB) when operating in the bipolar mode.
Gain Error
The first code transition should occur at an analog value 1/2
LSB above minus full scale. The last code transition should
occur for an analog value 3/2 LSB below the nominal full scale.
Gain error is the deviation of the actual difference between first
and last code transitions and the ideal difference between first
and last code transitions.
Signal-to-(Noise + Distortion)
Signal-to-(Noise + Distortion) is measured signal-to-noise at the
output of the ADC. The signal is the rms magnitude of the
fundamental. Noise plus distortion is the rms sum of all of the
nonfundamental signals and harmonics to half the output word
rate (fMCLK/128), excluding dc. Signal-to-(Noise + Distortion) is
dependent on the number of quantization levels used in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical Signal-to-(Noise + Distortion) ratio
for a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
where N is the number of bits.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
AD7720, THD is defined as
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic.
Spurious Free Dynamic Range
Spurious free dynamic range is the difference, in dB, between
the peak spurious or harmonic component in the ADC output
spectrum (up to fMCLK/128 and excluding dc) and the rms value
of the fundamental. Normally, the value of this specification will
be determined by the largest harmonic in the output spectrum
of the FFT. For input signals whose second harmonics occur in
the stop band region of the digital filter, a spur in the noise floor
limits the spurious free dynamic range.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m or n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
(AVDD = DVDD = 5.0 V, TA = +258C; CLKIN = 12.5 MHz, AIN = 20 kHz, Bipolar Mode; VIN(+) = 0 V to 2.5 V, VIN(–) = 1.25 V unless otherwise
noted)
AD7720–Typical Characteristics
INPUT LEVEL – dB
100–40–300–20–10
Figure 5.S/(N+D) and SFDR vs.
Analog Input Level
INPUT FREQUENCY – kHz
–110
Figure 8.SNR, THD, and SFDR vs.
Input Frequency
TEMPERATURE – °C
–98
Figure 11.THD vs. Temperature
OUTPUT DATA RATE – kSPS50300100150200250
Figure 6.S/(N+D) vs. Output Sample
Rate
OUTPUT DATA RATE – kSPS50300100150200250
Figure 9.S/(N+D) vs. Output Sample
Rate
CODES
FREQUENCY OF OCCURENCE
n–3n–2n+3n–1nn+1n+2
3000
Figure 12.Histogram of Output Codes
with DC Input
INPUT FREQUENCY – kHz
–110
Figure 7.SNR, THD, and SFDR vs.
Input Frequency
TEMPERATURE – °C
90.5
Figure 10.SNR vs. Temperature
CODE
DNL ERROR – LSB
0.4
Figure 13.Differential Nonlinearity

Partno	Mfg	Dc	Qty	Available	Descript
AD7720BRU	ANALOG	N/a	144	avai	CMOS Sigma-Delta Modulator