AD7719BRU ,Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual ADCapplications. It contains two high resolution sigma-TMISOURCE Selectdelta ADCs, switchable matched ..
AD7720 ,CMOS Sigma-Delta Modulator with 90 dB Dynamic RangeGENERAL DESCRIPTIONThis device is a 7th order sigma-delta modulator that convertsthe analog input s ..
AD7720BRU ,CMOS Sigma-Delta ModulatorSPECIFICATIONS AMIN MINParameter B Version Units Test Conditions/CommentsSTATIC PERFORMANCE When Te ..
AD7721AN ,CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADCGENERAL DESCRIPTIONThe AD7721 is a complete low power, 12-/16-bit, sigma-deltaADC. The part operat ..
AD7721AR ,CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADCSPECIFICATIONSSignal to (Noise + Distortion) 74 74 dB min Input Bandwidth 0 kHz to 210 kHzTotal Har ..
AD7722AS ,16-Bit, 195 kSPS CMOS, Sigma-Delta ADCSPECIFICATIONSBipolar Mode, UNI = V V = 2.5 V, V (+) = V (–) =1.25 V pk-pkINH CM IN INor, V (–) =1. ..
ADM1041ARQ-REEL , Secondary-Side Controller with Current Share and Housekeeping
ADM1051AJR ,Precision Dual Voltage Regulator ControllersFEATURESThe ADM1051/ADM1051A are dual, precision, voltage regula-Two Independent Controllers on One ..
ADM1051AJR-REEL7 ,Precision Dual Voltage Regulator ControllersSPECIFICATIONS channels, unless otherwise noted. See Test Circuit.)Parameter Min Typ Max Unit Test ..
ADM1051AJRZ ,Precision Dual Voltage Regulator ControllersFEATURESThe ADM1051/ADM1051A are dual, precision, voltage regula-Two Independent Controllers on One ..
ADM1051JR ,Precision Dual Voltage Regulator ControllersSpecifications subject to change without notice.–2– REV. 0ADM1051/ADM1051AABSOLUTE MAXIMUM RATINGS* ..
ADM1051JR-REEL ,Precision Dual Voltage Regulator ControllerSpecifications subject to change without notice.–2– REV. 0ADM1051/ADM1051AABSOLUTE MAXIMUM RATINGS* ..
AD7719BRU
Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual ADC
REV.0
Low Voltage, Low Power,
Factory-Calibrated 16-/24-Bit Dual �-� ADC
FEATURES
HIGH RESOLUTION �-� ADCs
Two Independent ADCs (16- and 24-Bit Resolution)
Factory-Calibrated (Field Calibration Not Required)
Output Settles in One Conversion Cycle (Single
Conversion Mode)
Programmable Gain Front End
Simultaneous Sampling and Conversion of Two
Signal Sources
Separate Reference Inputs for Each Channel
Simultaneous 50 Hz and 60 Hz Rejection at 20 Hz
Update Rate
ISOURCE SelectTM
24-Bit No Missing Codes—Main ADC
13-Bit p-p Resolution @ 20 Hz, 20 mV Range
18-Bit p-p Resolution @ 20 Hz, 2.56 V Range
INTERFACE
3-Wire Serial
SPITM, QSPITM, MICROWIRETM and DSP-Compatible
Schmitt Trigger on SCLK
POWER
Specified for Single 3 V and 5 V Operation
Normal: 1.5 mA Typ @ 3 V
Power-Down: 10 �A (32 kHz Crystal Running)
ON-CHIP FUNCTIONS
Rail-Rail Input Buffer and PGA
4-Bit Digital I/O Port
On-Chip Temperature Sensor
Dual Switchable Excitation Current Sources
GENERAL DESCRIPTIONThe AD7719 is a complete analog front end for low frequency
measurement applications. It contains two high resolution sigma-
delta ADCs, switchable matched excitation current sources,
low-side power switches, digital I/O port, and temperature
sensor. The 24-bit main channel with PGA accepts fully differen-
tial, unipolar, and bipolar input signal ranges from 1.024 ×
REFIN1/128 to 1.024 × REFIN1. Signals can be converted
directly from a transducer without the need for signal condi-
tioning. The 16-bit auxiliary channel has an input signal range
of REFIN2 or REFIN2/2.
The device operates from a 32 kHz crystal with an on-chip
PLL generating the required internal operating frequency. The
output data rate from the part is software programmable. The
peak-to-peak resolution from the part varies with the programmed
gain and output data rate.
The part operates from a single 3 V or 5 V supply. When oper-
ating from 3 V supplies, the power dissipation for the part is
4.5 mW with both ADCs enabled and 2.85 mW with only the
main ADC enabled in unbuffered mode. The AD7719 is housed
in 28-lead SOIC and TSSOP packages.
Low-Side Power Switches
Reference Detect Circuit
APPLICATIONS
Sensor Measurement
Temperature Measurement
Pressure Measurements
Weigh Scales
Portable Instrumentation
4–20 mA TransmittersISOURCE Select is a trademark of Analog Devices.
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
FUNCTIONAL BLOCK DIAGRAM
DVDDDGND
IOUT1
IOUT2
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AVDDAGNDREFIN2PWRGNDP1/SW1P2/SW2P3P4
DOUT
DIN
SCLK
RDY
RESET
XTAL1XTAL2REFIN1(+)REFIN1(–)
AD7719FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 7
DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 9
TYPICAL PERFORMANCE CHARACTERISTICS . . . . 11
DUAL-CHANNEL ADC CIRCUIT INFORMATION . . . 12
Main Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Auxiliary Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Both Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MAIN AND AUXILIARY ADC NOISE
PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Communications Register
(A3, A2, A1, A0 = 0, 0, 0, 0) . . . . . . . . . . . . . . . . . . . . 19
Status Register (A3, A2, A1, A0 = 0, 0, 0, 0;
Power–On Reset = 00 Hex) . . . . . . . . . . . . . . . . . . . . . 20
Mode Register (A3, A2, A1, A0 = 0, 0, 0, 1;
Power-On-Reset = 00 Hex) . . . . . . . . . . . . . . . . . . . . . 21
Operating Characteristics when Addressing the Mode
and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Main ADC Control Register (AD0CON):
(A3, A2, A1, A0 = 0, 0, 1, 0;
Power-On Reset = 07 Hex) . . . . . . . . . . . . . . . . . . . . . 22
Aux ADC Control Registers (AD1CON):
(A3, A2, A1, A0 = 0, 0, 1, 1;
Power-On Reset = 01 Hex) . . . . . . . . . . . . . . . . . . . . . 23
Filter Register (A3, A2, A1, A0 = 0, 1, 0, 0;
Power-On Reset = 45 Hex) . . . . . . . . . . . . . . . . . . . . . 24
I/O and Current Source Control Register (IOCON):
(A3, A2, A1, A0 = 0, 1, 1, 1;
Power-On Reset = 0000 Hex) . . . . . . . . . . . . . . . . . . . 24
Main ADC Data Result Registers (DATA0):
(A3, A2, A1, A0 = 0, 1, 0, 1;
Power-On Reset = 000000 Hex) . . . . . . . . . . . . . . . . . 26
Aux ADC Data Result Registers (DATA1):
(A3, A2, A1, A0 = 0, 1, 1, 0;
Power-On Reset = 0000 Hex) . . . . . . . . . . . . . . . . . . . 26
Main ADC Offset Calibration Coefficient Registers (OF0):
(A3, A2, A1, A0 = 1, 0, 0, 0;
Power-On Reset = 800000 Hex) . . . . . . . . . . . . . . . . . 26
Aux ADC Offset Calibration Coefficient Registers (OF1):
(A3, A2, A1, A0 = 1, 0, 0, 1;
Power-On Reset = 8000 Hex) . . . . . . . . . . . . . . . . . . . 26
Main ADC Gain Calibration Coefficient Registers (GNO):
(A3, A2, A1, A0 = 1, 0, 1, 0;
Power-On Reset = 5XXXX5 Hex) . . . . . . . . . . . . . . . . 25
Aux ADC Gain Calibration Coefficient Registers (GN1):
(A3, A2, A1, A0 = 1, 0, 1, 1;
Power-On Reset = 59XX Hex) . . . . . . . . . . . . . . . . . . . 26
ID Register (ID): (A3, A2, A1, A0 = 1, 1, 1, 1;
Power-On Reset = 0X Hex) . . . . . . . . . . . . . . . . . . . . . 26
User Nonprogrammable Test Registers . . . . . . . . . . . . . . 26
CONFIGURING THE AD7719 . . . . . . . . . . . . . . . . . . . . . 27
MICROCOMPUTER/MICROPROCESSOR
INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AD7719-to-68HC11 Interface . . . . . . . . . . . . . . . . . . . . . 28
AD7719-to-8051 Interface . . . . . . . . . . . . . . . . . . . . . . . . 28
AD7719-to-ADSP-2103/ADSP-2105 Interface . . . . . . . . 30
CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 30
Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 32
Bipolar/Unipolar Configuration . . . . . . . . . . . . . . . . . . . . 33
Data Output Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Burnout Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Excitation Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Reference Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ADC Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pressure Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . 37
3-Wire RTD Configurations . . . . . . . . . . . . . . . . . . . . . . 38
Smart Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 40
TABLE OF CONTENTS
AD7719–SPECIFICATIONS1
(AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V,
REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications TMIN to TMAX unless otherwise noted.)
AD7719REFERENCE INPUT (REFIN2)
LOW-SIDE POWER SWITCHES
TEMPERATURE SENSOR
AD7719–SPECIFICATIONS1START-UP TIME
AD7719NOTESTemperature Range –40°C to +85°C.Guaranteed by design and/or characterization data on production release.System zero calibration will remove this error.A calibration at any temperature will remove this drift error.The Main ADC is factory-calibrated with AVDD = DVDD = 4 V, TA = 25°C, REFIN1(+) – REFIN1(–) = 2.5 V. If the user power supplies or temperature conditions
are significantly different from these, internal full-scale calibration will restore this error to the published specification. System calibration can be used to reduce this
error to the order of the noise. Full scale error applies to both positive and negative full scale.Simultaneous 50 Hz and 60 Hz rejection is achieved using 19.8 Hz (SF = 69) update rate. Normal mode rejection in this case is 60 dB min.Input and Output levels on the I/O Port are with respect to AVDD and AGND.A system full-scale calibration will remove this error.A typical gain error of ± 10µV results following a user self calibration.After a calibration if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale then the device will
output all 0s.FS = Full-Scale Input. FS = 1.024 × REFIN1/Gain on the Main ADC, where REFIN1 = REFIN1(+) – REFIN1(–). FS = REFIN2 on the aux ADC when ARN = 1
in the aux ADC control register (AD1CON) and REFIN2/2 on the aux ADC when ARN = 0.Normal Mode refers to the case where both main and aux ADCs are running.ADC disable is entered by setting both the AD0EN and AD1EN bits in the Main and Aux ADC control registers to a 0 and setting the mode bits (MD2, MD1,
MD0) in the Mode register to non-0.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1(TA = 25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND2. . . . . . . . . . . . . . . . . . . –20 mV to +20 mV
PWRGND to AGND . . . . . . . . . . . . . . . . –20 mV to +20 mV
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +5 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD +0.3 V
Reference Input Voltage to AGND . . –0.3 V to AVDD +0.3 V
Total AIN/REFIN Current (Indefinite) . . . . . . . . . . . . 30 mA
Digital Input Voltage to DGND . . . . –0.3 V to DVDD +0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD +0.3 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
SOIC Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 71.4°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 23°C/W
TSSOP Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 97.9°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 14°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2AGND and DGND and connected internally within the AD7719.
ORDERING GUIDE
TIMING CHARACTERISTICS1, 2Read Operation
NOTESSample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.See Figures 2 and 3.
3SCLK active edge is falling edge of SCLK.These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.
6These numbers are derived from the measured time taken by the data output to change 0.5V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the
part and as such are independent of external bus loading capacitances.RDY returns high after a read of both ADCs. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur
close to the next output update.
(AVDD = 2.7 V to 3.6 V or AVDD = 4.75 V to 5.25 V; DVDD = 2.7 V to 3.6 V or DVDD = 4.75 V to
5.25 V; AGND = DGND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.)Figure 1.Load Circuit for Timing Characterization
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7719 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
AD7719Figure 2.Write Cycle Timing Diagram
to ensure that a data read is not attempted while the register is
being updated. CS is used to select the device. It can be used to
decode the AD7719 in systems where a number of parts are
connected to the serial bus.
Figures 2 and 3 show timing diagrams for interfacing to the
AD7719 with CS used to decode the part. Figure 3 is for a read
operation from the AD7719’s output shift register while Figure 2
shows a write operation to the input shift register. It is possible
to read the same data twice from the output register even though
the RDY line returns high after the first read operation. Care must
be taken, however, to ensure that the read operations have been
completed before the next output update is about to take place.
The AD7719 serial interface can operate in 3-wire mode by
tying the CS input low. In this case, the SCLK, DIN, and
DOUT lines are used to communicate with the AD7719 and
the status of RDY bits (RDY0 and RDY1) can be obtained by
interrogating the STATUS Register. This scheme is suitable
for interfacing to microcontrollers. If CS is required as a decod-
ing signal, it can be generated from a port bit. For microcontroller
interfaces, it is recommended that the SCLK idles high between
data transfers.
The AD7719 can also be operated with CS used as a frame
synchronization signal. This scheme is suitable for DSP inter-
faces. In this case, the first bit (MSB) is effectively clocked out
by CS since CS would normally occur after the falling edge of
SCLK in DSPs. The SCLK can continue to run between data
transfers provided the timing numbers are obeyed.
DIGITAL INTERFACEAs previously outlined, the AD7719’s programmable functions
are controlled using a set of on-chip registers. Data is written to
these registers via the part’s serial interface and read access to
the on-chip registers is also provided by this interface. All com-
munications to the part must start with a write operation to the
Communications Register. After power-on or RESET, the device
expects a write to its Communications Register. The data writ-
ten to this register determines whether the next operation to the
part is a read or a write operation and also determines to which
register this read or write operation occurs. Therefore, write
access to any of the other registers on the part starts with a write
operation to the Communications Register followed by a write
to the selected register. A read operation from any other register
on the part (including the output data register) starts with a
write operation to the Communications Register followed by a
read operation from the selected register.
The AD7719’s serial interface consists of five signals, CS, SCLK,
DIN, DOUT, and RDY. The DIN line is used for transferring
data into the on-chip registers while the DOUT line is used for
accessing data from the on-chip registers. SCLK is the serial
clock input for the device and all data transfers (either on DIN
or DOUT) take place with respect to this SCLK signal. The
RDY line is used as a status signal to indicate when data is ready
to be read from the AD7719’s data register. RDY goes low when a
new data word is available in the output register of either the
main or Aux ADCs. It is reset high when a read operation from
the data register is complete. It also goes high prior to the updating
of the output register to indicate when not to read from the device
PIN CONFIGURATIONThe serial interface can be reset by exercising the RESET input
on the part. It can also be reset by writing a series of 1s on the
DIN input. If a Logic 1 is written to the AD7719 DIN line for
at least 32 serial clock cycles the serial interface is reset. This
ensures that in 3-wire systems, if the interface gets lost either via
a software error or by some glitch in the system, it can be reset
back to a known state. This state returns the interface to where
the AD7719 is expecting a write operation to its Communica-
tions Register. This operation resets the contents of all registers to
their power-on reset values.
Some microprocessor or microcontroller serial interfaces have a
single serial data line. In this case, it is possible to connect the
AD7719’s DATA OUT and DATA IN lines together and connect
them to the single data line of the processor. A 10 kΩ pull-up
resistor should be used on this single data line. In this case, if
the interface gets lost, because the read and write operations
share the same line the procedure to reset it back to a known
state is somewhat different than previously described. It requires
a read operation of 24 serial clocks followed by a write operation
where a Logic 1 is written for at least 32 serial clock cycles to
ensure that the serial interface is back into a known state.
PIN FUNCTION DESCRIPTIONS
AD7719
PIN FUNCTION DESCRIPTIONS (continued)
TPC 1.Typical Noise Plot on ±20 mV Input Range with
19.79 Hz Update Rate
TPC 2.Noise Distribution Histogram
TPC 4.No-Missing-Codes Performance
TPC 5.Temperature Sensor Accuracy
AD7719TPC 7.Typical Oscillator Power-Up
DUAL-CHANNEL ADC CIRCUIT INFORMATION
OverviewThe AD7719 incorporates two independent Σ-∆ ADC channels
(main and auxiliary) with on-chip digital filtering intended for
the measurement of wide dynamic range, low frequency signals
such as those in weigh-scale, strain-gauge, pressure transducer,
or temperature measurement applications.
Main ChannelThis channel is intended to convert the primary sensor input.
This channel can be operated in buffered or unbuffered mode
and can be programmed to have one of eight input voltage ranges
from ±20 mV to ±2.56 V. This channel can be configured as
either two fully differential inputs (AIN1/AIN2 and AIN3/AIN4)
or three pseudo-differential input channels (AIN1/AIN4, AIN2/
AIN4, and AIN3/AIN4). Buffering the input channel means that
the part can accommodate significant source impedances on the
analog input and that R, C filtering (for noise rejection or RFI
reduction) can be placed on the analog inputs if required. Oper-
ating in unbuffered mode leads to lower power consumption in
low power applications, but care must be exercised in unbuffered
mode as source impedances can introduce gain errors. The main
ADC also features sensor burnout currents that can be switched
on and off. These currents can be used to check that a transducer
is still operational before attempting to take measurements.
The ADC employs a sigma-delta conversion technique to realize
up to 24 bits of no-missing-codes performance. The sigma-delta
modulator converts the sampled input signal into a digital pulse
train whose duty cycle contains the digital information. A Sinc3
programmable low-pass filter is then employed to decimate the
modulator output data stream to give a valid data conversion
result at programmable output rates from 5.35 Hz (186.77 ms)
to 105.0 3 Hz (9.52 ms). A chopping scheme is also employed
to minimize ADC channel offset errors. A block diagram of the
Main ADC input channel is shown in Figure 4. The sampling
frequency of the modulator loop is many times higher than the
bandwidth of the input signal. The integrator in the modulator
shapes the quantization noise (which results from the analog-to-
digital conversion) so that the noise is pushed toward one-half of
the modulator frequency. The output of the sigma-delta modu-
lator feeds directly into the digital filter. The digital filter then
band-limits the response to a frequency significantly lower than
one-half of the modulator frequency. In this manner, the 1-bit
output of the comparator is translated into a bandlimited, low
noise output from the AD7719 ADC. The AD7719 filter is a
low-pass, Sinc3 or (SIN(x)/x)3 filter whose primary function is to
remove the quantization noise introduced at the modulator. The
cutoff frequency and decimated output data rate of the filter are
programmable via the SF word loaded to the filter register.
A chopping scheme is employed where the complete signal chain is
chopped, resulting in excellent dc offset and offset drift specifi-
cations, and is extremely beneficial in applications where drift, noise
rejection, and optimum EMI rejection are important factors.
With chopping the ADC repeatedly reverses its inputs. The
decimated digital output words from the Sinc3 filters therefore
have a positive offset and negative offset term included. As a result,
a final summing stage is included so that each output word from
the filter is summed and averaged with the previous filter output
to produce a new valid output result to be written to the ADC
data register.
Auxiliary ChannelThe Auxiliary (Aux) channel is intended to convert supplemen-
tary inputs such as from a cold junction diode or thermistor.
This channel is unbuffered and has an input range of ±REFIN2
or ±REFIN2/2 determined by the ARN bit in the auxiliary ADC
control register (AD1CON). AIN3 and AIN4 can be multiplexed
into the auxiliary channel as single ended inputs with respect to
AGND while AIN5 and AIN6 can operate as a differential input
pair or with AIN6 tied to AGND, AIN5 can be operated as an
additional single-ended input. A block diagram of the Auxiliary
ADC channel is shown in Figure 5.
SINC3 FILTERANALOG
INPUT
DIGITAL
OUTPUT
AIN + VOS
AIN – VOS
fCHOPfINfMODfCHOPfADCFigure 4.Main ADC Channel Block Diagram
Both ChannelsThe operation of the AUX channel is identical to the Main
channel with the exception that there is no PGA on the AUX
channel. The input chopping is incorporated into the input
multiplexer while the output chopping is accomplished by an
XOR gate at the output of the modulator. The chopped modu-
lator bit stream is applied to a Sinc3 filter. The programming of
the Sinc3 decimation factor is restricted to an 8-bit register SF,
the actual decimation factor is the register value times 8. The
decimated output rate from the Sinc3 filter (and the ADC con-
version rate) will therefore be:
where
fADC is the ADC update rate.
SF is the decimal equivalent of the word loaded to the
filter register.
fMOD is the modulator sampling rate of 32.768 kHz.
Programming the filter register determines the update rate for
both the main and aux ADC. Both ADCs operate with the same
update rate.
The chop rate of the channel is half the output data rate.
where
fMOD = 32,768 Hz
SF = value programmed into SF SFR.
fOUT = fMOD/(SF × 8 × 3)
The following shows plots of the filter frequency response for
the SF words shown in Table I. The overall frequency response
is the product of a Sinc3 and a sinc response. There are Sinc3
notches at integer multiples of 3 × fADC and there are sinc notches
SINC3 FILTERANALOG
INPUT
DIGITAL
OUTPUT
AIN + VOS
AIN – VOS
fCHOPfMODfCHOPfADCFigure 5.Auxiliary ADC Channel Block Diagram
at odd integer multiples of fADC/2. The 3 dB frequency for all
values of SF obeys the following equation:
f (3 dB) = 0.24 × fADC
The signal chain is chopped as shown in Figures 4 and 5. The
chop frequency is:
As shown in the block diagram, the Sinc3 filter outputs alternately
contain +VOS and –VOS, where VOS is the respective channel
offset. This offset is removed by performing a running average
of 2. This average by 2 means that the settling time to any change
in programming of the ADC will be twice the normal conversion
time, while an asynchronous step change on the analog input will
not be fully reflected until the third subsequent output.
The allowable range for SF is 13 to 255, with a default of 69
(45H). The corresponding conversion rates, conversion times
and settling times are tabulated in Table I. Note that the con-
version time increases by 0.732 ms for each increment in SF.
Table I.ADC Conversion and Settling Times for Various
SF WordsNormal-mode rejection is the major function of the digital filter
on the AD7719. The normal mode 50 ± 1 Hz rejection with an SF
word of 82 is typically –100 dB. The 60 ± 1 Hz rejection with
SF = 68 is typically –100 dB. Simultaneous 50 Hz and 60 Hz
rejection of better than 60 dB is achieved with an SF of 69.
Choosing an SF word of 69 places notches at both 50 Hz and
60 Hz. Figures 6 to 9 show the filter rejection for a selection
of SF words.
AD7719Figure 8.Filter Profile with Default SF = 69 Giving Filter
Notches at Both 50 Hz and 60 Hz
Figure 9.Filter Profile with SF = 255
Figure 6.Filter Profile with SF = 13
Figure 7.Filter Profile with SF = 82
MAIN AND AUXILIARY ADC NOISE PERFORMANCETables II to VII show the output rms noise and output peak-to-
peak resolution in bits (rounded to the nearest 0.5 LSB) for a
selection of output update rates on both the main and auxiliary
ADCs. The numbers are typical and generated at a differential
input voltage of 0 V. The output update rate is selected via the
SF7-SF0 bits in the Filter Register. It is important to note that
the peak-to-peak resolution figures represent the resolution for
which there will be no code flicker within a six-sigma limit. The
output noise comes from two sources. The first is the electrical
noise in the semiconductor devices (device noise) used in the
implementation of the modulator. Secondly, when the analog
input is converted into the digital domain, quantization noise is
added. The device noise is at a low level and is independent of
frequency. The quantization noise starts at an even lower level
but rises rapidly with increasing frequency to become the domi-
nant noise source. The numbers in the tables are given for the
bipolar input ranges. For the unipolar ranges the rms noise
numbers will be the same as the bipolar range, but the peak-to-
peak resolution is now based on half the signal range, which
effectively means losing 1 bit of resolution.
Table II.Typical Output RMS Noise vs. Input Range and Update Rate for Main ADC (Buffered Mode) Output RMS
Noise in �V
Table III.Peak-to-Peak Resolution vs. Input Range and Update Rate for Main ADC (Buffered Mode) Peak-to-Peak
Resolution in Bits
Table IV.Typical Output RMS Noise vs. Input Range and Update Rate for Main ADC (Unbuffered Mode) Output
RMS Noise in �V
Table V.Peak-to-Peak Resolution vs. Input Range and Update Rate for Main ADC (Unbuffered Mode) Peak-to-Peak
Resolution in Bits
Table VI. Typical Output RMS Noise vs.
Update Rate for Auxiliary ADC Unbuffered)
Table VII. Peak-to-Peak Resolution vs. Update
Rate for Auxiliary ADC (Unbuffered Mode)
AD7719
ON-CHIP REGISTERSBoth the main and auxiliary ADC channels are controlled and
configured via a number of on-chip registers as shown in Figure
10 and described in more detail in the following pages. In the fol-
lowing descriptions, SET implies a Logic 1 state and CLEARED
implies a Logic 0 state, unless otherwise stated.
Figure 10.On-Chip Registers
Table VIII.Registers—Quick Reference Guide
Power-On/Reset
Register NameTypeSizeDefault ValueFunctionCommunicationsWrite Only8 BitsNot ApplicableAll operations to other registers are initiated through
the Communications Register. This controls whether
subsequent operations are read or write operations
and also selects the register for that subsequent
operation.Provides status information on conversions, cali-
brations, error conditions, and the validity of the
reference voltage.Controls functions such as mode of operation, chan-
nel configuration, oscillator operation in power-down.
Main ADC (AD0CON)
Control RegisterRead/Write8 Bits07 HexThis register is used to enable the Main ADC and
configure the Main ADC for range, channel selection,
16-/24-bit operation, and unipolar or bipolar operation.
Aux ADC (AD1CON)
Control RegisterRead/Write8 Bits01 HexThis register is used to enable the aux ADC and
configure the Aux ADC for range, channel selection,
unipolar or bipolar operation, and input range.
I/O (IOCON)This register is used to control and configure the
various excitation and burnout current source options
available on-chip along with controlling the I/O port.
AD7719
Power-On/Reset
Register NameTypeSizeDefault ValueFunctionMain ADC (DATA0)
Data RegisterRead Only16 Bits or 24 Bits000000 HexProvides the most up-to-date conversion result from
the Main ADC. Main ADC data register length
can be programmed to be 16-bit or 24-bit.
Aux ADC (DATA1)
Data RegisterRead Only16 Bits0000 HexProvides the most up-to-date conversion result from
the auxiliary ADC. Aux ADC data register length is
16 bits.
Main ADC
Offset RegisterRead/Write24 Bits800000 HexContains a 24-bit word that is the offset calibration
coefficient for the part. The contents of this register
are used to provide offset correction on the output
from the digital filter. There are three Offset Regis-
ters on the part and these are associated with input
channel pairs as outlined in the AD0CON register.
Main ADC
Gain RegisterRead/Write24 Bits5XXXX5 HexContains a 24-bit word that is the gain calibration
coefficient for the part. The contents of this register
are used to provide gain correction on the output
from the digital filter. There are three Gain Registers
on the part and these are associated with input chan-
nel pairs as outlined in the AD0CON register.
Aux ADC
Offset RegisterRead/Write16 Bits8000 HexContains a 16-bit word that is the offset calibration
coefficient for the part. The contents of this register
are used to provide offset correction on the output
from the digital filter.
Aux ADC
Gain RegisterRead/Write24 Bits59XX HexContains a 16-bit word that is the gain calibration
coefficient for the part. The contents of this register
are used to provide gain correction on the output
from the digital filter.
ID RegisterRead8 Bits0X HexContains an 8-bit byte that is the identifier for the
part.
Test RegistersRead/Write16 Bits0000 HexControls the test modes of the part which are used
when testing the part. The user is advised not to
change the contents of these registers.
Communications Register (A3, A2, A1, A0 = 0, 0, 0, 0)The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the
Communications Register. The data written to the Communications Register determines whether the next operation is a read
or write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write
operation to the selected register is complete, the interface returns to where it expects a write operation to the Communications
Register. This is the default state of the interface, and on power-up or after a RESET, the AD7719 is in this default state waiting for
a write operation to the Communications Register. In situations where the interface sequence is lost, a write operation of at least 32
serial clock cycles with DIN high, returns the AD7719 to this default state by resetting the part. Table IX outlines the bit designa-
tions for the Communications Register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the Communications
Register. CR7 denotes the first bit of the data stream.
Table IX.Communications Register Bit Designations
Table X.Register Selection Table
AD7719
Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; Power-On Reset = 00 Hex)The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communica-
tions Register selecting the next operation to be a read and load bits A3–A0 with 0, 0, 0, 0. Table XI outlines the bit designations for
the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first
bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
Table XI. Status Register Bit DesignationsSR3
SR2
SR1
SR0
