AD7716BP-AD7716BS Fast Delivery |IC PHOENIX CO.,LIMITED

AD7716BP ,LC2MOS 22-Bit Data Acquisition SystemFEATURES22-Bit Sigma-Delta ADCAV DV AVRESET A0 A1 A2 CLKIN CLKOUTDD DD SSDynamic Range of 105 dB (1 ..
AD7716BS ,LC2MOS 22-Bit Data Acquisition SystemSpecifications subject to change without notice.–2– REV. AAD7716Table I. Typical Usable Dynamic Ran ..
AD7718BR ,8-/10-Channel, Low Voltage, Low Power, ADCsOverview (CHOP Disabled CHOP = 1) . . . 19 Bipolar/Unipolar Configuration . . . . . . . . . . . . . ..
AD7719BRU ,Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual ADCapplications. It contains two high resolution sigma-TMISOURCE Selectdelta ADCs, switchable matched ..
AD7720 ,CMOS Sigma-Delta Modulator with 90 dB Dynamic RangeGENERAL DESCRIPTIONThis device is a 7th order sigma-delta modulator that convertsthe analog input s ..
AD7720BRU ,CMOS Sigma-Delta ModulatorSPECIFICATIONS AMIN MINParameter B Version Units Test Conditions/CommentsSTATIC PERFORMANCE When Te ..
ADM1034ARQ-REEL ,Thermal Monitor and Fan Speed ControllerCharacteristics 8 Conversion Rate Register .... 23 Functional Description ... 10 I/O Timer and Li ..
ADM1034ARQZ ,Thermal Monitor and Fan Speed ControllerSpecifications subject to change without notice. No license is granted by implication www.analog.c ..
ADM1034ARQZ ,Thermal Monitor and Fan Speed ControllerCharacteristics ........ 6 Interrupt Masking Register. 22 ESD Caution. 6 FAN_FAULT Output .. 23 Pin ..
ADM1034ARQZ-REEL ,Thermal Monitor and Fan Speed ControllerSpecifications.... 4 ALERT Interrupt Behavior . 21 Absolute Maximum Ratings...... 6 Handling SMBUSA ..
ADM1041A ,Secondary-Side Controller with Current Share and HousekeepingGENERAL DESCRIPTIONThe ADM1041A is a secondary-side and management IC spec- Another key feature of ..
ADM1041AARQZ , Secondary-Side Controller with Current Share and Housekeeping

AD7716BP-AD7716BS
LC2MOS 22-Bit Data Acquisition System

AD7716–SPECIFICATIONS1, 2(fCLKIN = 8 MHz; MODE Pin Is High (Slave Mode Operation); AVDD = DVDD = +5 V
6 5%; AVSS = –5 V 6 5%; AGND = DGND = 0 V; VREF = 2.5 V; Filter Cutoff = 146 Hz; Noise Measurement Bandwidth = 146 Hz; AIN Source
Resistance = 750 V2 with 1 nF to AGND at each AIN. TA = TMIN to TMAX, unless otherwise noted.)
POWER SUPPLIES
NOTESOperating temperature ranges as follows : B Version; –40°C to +85°C.The AIN pins present a very high impedance dynamic load which varies with clock frequency.Guaranteed by design and characterization. Digital filter has linear phase.Usable dynamic range is guaranteed by measuring noise and relating this to the full-scale input range.100 mV p-p, 120 Hz sine wave applied to each supply.
Specifications subject to change without notice.
Table I.Typical Usable Dynamic Range, RMS Noise and Filter Settling Time vs. Filter Cutoff Frequency
NOTE
Usable Dynamic Range is defined as the ratio of the rms full-scale reading (sine wave input) to the rms noise of the converter.
CONTROL REGISTER TIMING CHARACTERISTICS1, 2(AVDD = DVDD = +5V6 5%; AVSS= –5V6 5%; AGND =
DGND = 0 V; fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted)
NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.See Figure 2.CLKIN Duty Cycle range is 40% to 60%.
Figure 1.Load Circuit for Access Time and Bus Relinquish Time
Figure 2.Control Register Timing Diagram
AD7716
t11
t12
t13
t15
t16
t17
t20
NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.See Figures 1 and 3.CLKIN duty cycle range is 40% to 60%.The AD7716 is production tested with fCLKIN at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz and 8 MHz in master mode.Specified using 10% and 90% points on waveform of interest.t16 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.t17 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
MASTER MODE TIMING CHARACTERISTICS1, 2(AVDD = DVDD = +5V6 5%; AVSS= –5V6 5%; AGND = DGND = 0 V;
fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted)
Figure 3.Master Mode Timing Diagram
SLAVE MODE TIMING CHARACTERISTICS1, 2(AVDD = DVDD = +5V6 5%; AVSS= –5V6 5%; AGND = DGND = 0 V;
fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted)
t24
t28
t30
NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.See Figures 1 and 4.CLKIN duty cycle range is 40% to 60%.The AD7716 is production tested with fCLKIN at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz.Specified using 10% and 90% points on waveform of interest.t28 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.t30 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Figure 4.Slave Mode Timing Diagram
AD7716
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
Analog Inputs to AGND . . . . . .AVSS – 0.3 V to AVDD + 0.3 V
VREF to AGND . . . . . . . . . . . .AVSS – 0.3 V to AVDD + 0.3 V
Digital Inputs to DGND2 . . . . . . . . . .–0.3 V to DVDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . .–0.3 V to DVDD + 0.3 V
Operating Temperature Range
Commercial Plastic (B Versions) . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
PQFP Package, Power Dissipation . . . . . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
PLCC Package, Power Dissipation . . . . . . . . . . . . . . .500 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .55°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.PLCC PINOUT
ORDERING GUIDE
*P = PLCC (Plastic Leaded Chip Carrier); S = PQFP (Plastic Quad Flatpack).
PIN DESCRIPTION
DVDD
AVSS
RESET
A0–A2
CLKIN
CLKOUT
MODE
CASCIN
CASCOUT
DOUT1, DOUT2
VREF
AGND
DGND
AD7716
OUTPUT UPDATE RATE
This is the rate at which the digital filter updates the output shift
register. It is a function of the master clock frequency and the
programmed filter cutoff frequency.
FILTER CUTOFF FREQUENCY
The digital filter of the AD7716 can be programmed, in binary
steps, to 5 discrete cutoff frequencies, ranging from 584 Hz to
36.5 Hz (for a CLKIN frequency of 8 MHz).
SETTLING TIME
This is the settling time of the on-chip digital filter, to 0.0007%
of FSR, in response to a full-scale step at the input of the ADC.
It is proportional to the master clock frequency and the filter
cutoff frequency.
USABLE DYNAMIC RANGE
The usable dynamic range is the ratio of the rms full-scale
reading (sine wave input) to the rms noise of the converter,
expressed in dBs. It determines the level to which it is possible
to resolve the input signal. For example, at a bandwidth of
146 Hz, the rms noise of the converter is 11 μV. The full-scale
rms is 1.77 volts. So, the usable dynamic range is 104 dB. Any
signal below this level will be indistinguishable from noise unless
extra post-filtering techniques are employed.
TOTAL HARMONIC DISTORTION
Total harmonic distortion (THD) is the ratio of the rms sum
of the harmonics to the fundamental. For the AD7716, it is
defined as:
THD(dB)=20log
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through
sixth harmonics.
ABSOLUTE GROUP DELAY
Absolute group delay is the rate of change of phase versus fre-
quency, dφ/df and is expressed in seconds. For the AD7716,
it is dependent on master clock frequency and filter cutoff
frequency.
DIFFERENTIAL GROUP DELAY
Differential group delay is the total variation in absolute group
delay in the specified bandwidth. Since the digital filter in the
AD7716 has perfectly linear phase, the differential group delay
is almost zero. This is important in many signal processing ap-
plications where excessive differential group delay can cause
phase distortion.
TERMINOLOGY
LINEARITY ERROR
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale (not to be con-
fused with Bipolar Zero), a point 0.5 LSB below the first code
transition (000...000 to 000...001) and full scale, a point
0.5 LSB above the last code transition (111...110 to
111...111). The error is expressed as a percentage of full
scale.
DIFFERENTIAL LINEARITY ERROR/NO MISSED CODES
This is the difference between any code’s actual width and the
ideal (1 LSB) width. Differential Linearity Error is expressed in
LSBs. A differential linearity specification of ±1 LSB or less
guarantees no missed codes to the full resolution of the device.
The AD7716 has no missed codes guaranteed to 21 bits with a
cutoff frequency of 146 Hz.
GAIN ERROR
Gain Error is the deviation of the last code transition
(111...110 to 111...1) from the ideal (VREF –3/2 LSBs). It
is expressed as a percentage of full scale.
GAIN TC
This is the variation of gain error with temperature and is ex-
pressed in μV/°C.
OFFSET ERROR
Offset Error is the deviation of the first code transition from the
ideal (–VREF + 0.5 LSB). It is expressed as a percentage of full
scale.
OFFSET TC
This is the variation of offset error with temperature and is ex-
pressed in μV/°C.
NOISE
This is the converter rms noise expressed in μV. Because of the
digital filtering in the sigma delta converter, the noise perfor-
mance is a function of the programmed filter cutoff.
SAMPLING RATE
This is the modulator sampling rate. For the AD7716, it is
fCLKIN/14.

Partno	Mfg	Dc	Qty	Available	Descript
AD7716BP		N/a	9	avai	LC2MOS 22-Bit Data Acquisition System
AD7716BS	AD	N/a	2	avai	LC2MOS 22-Bit Data Acquisition System