AD7715AN-5 ,3 V/5 V, 450 uA 16-Bit, Sigma-Delta ADCGENERAL DESCRIPTION CMOS construction ensures very low power dissipation, and theThe AD7715 is a co ..
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AD7715AN-3-AD7715AN-5-AD7715AR-3-AD7715AR-5-AD7715ARU-5
3 V/5 V, 450 uA 16-Bit, Sigma-Delta ADC
FUNCTIONAL BLOCK DIAGRAMREV.C
3 V/5 V, 450 mA
16-Bit, Sigma-Delta ADC
FEATURES
Charge-Balancing ADC
16 Bits No Missing Codes
0.0015% Nonlinearity
Programmable Gain Front End
Gains of 1, 2, 32 and 128
Differential Input Capability
Three-Wire Serial Interface
SPI™, QSPI™, MICROWIRE™ and DSP Compatible
Ability to Buffer the Analog Input
3 V (AD7715-3) or 5 V (AD7715-5) Operation
Low Supply Current: 450␣mA max @ 3␣
V Supplies
Low-Pass Filter with Programmable Output Update
16-Lead SOIC/DIP/TSSOPCMOS construction ensures very low power dissipation, and the
power-down mode reduces the standby power consumption to
50␣mW typ. The part is available in a 16-lead, 0.3 inch-wide,
plastic dual-in-line package (DIP) as well as a 16-lead 0.3 inch-
wide small outline (SOIC) package and a 16-lead TSSOP package.
PRODUCT HIGHLIGHTSThe AD7715 consumes less than 450␣mA in total supply
current at 3 V supplies and 1␣MHz master clock, making it
ideal for use in low-power systems. Standby current is less
than 10␣mA.The programmable gain input allows the AD7715 to accept
input signals directly from a strain gage or transducer remov-
ing a considerable amount of signal conditioning.The AD7715 is ideal for microcontroller or DSP processor
applications with a three-wire serial interface reducing the
number of interconnect lines and reducing the number of
opto-couplers required in isolated systems. The part con-
tains on-chip registers which allow software control over
output update rate, input gain, signal polarity and calibration
modes.The part features excellent static performance specifications
with 16-bits no missing codes, –0.0015% accuracy and low
rms noise (<550␣nV). Endpoint errors and the effects of
temperature drift are eliminated by on-chip calibration op-
tions, which remove zero-scale and full-scale errors.
GENERAL DESCRIPTIONThe AD7715 is a complete analog front end for low frequency
measurement applications. The part can accept low level input
signals directly from a transducer and outputs a serial digital
word. It employs a sigma-delta conversion technique to realize
up to 16 bits of no missing codes performance. The input signal
is applied to a proprietary programmable gain front end based
around an analog modulator. The modulator output is pro-
cessed by an on-chip digital filter. The first notch of this digital
filter can be programmed via the on-chip control register allow-
ing adjustment of the filter cutoff and output update rate.
The AD7715 features a differential analog input as well as a dif-
ferential reference input. It operates from a single supply (+3␣V
or +5␣V). It can handle unipolar input signal ranges of 0 mV to
+20␣mV, 0 mV to +80␣mV, 0 V to +1.25␣V and 0 V to +2.5␣V.
It can also handle bipolar input signal ranges of –20␣mV, –80␣mV,1.25␣V and –2.5␣V. These bipolar ranges are referenced to
the negative input of the differential analog input. The AD7715
thus performs all signal conditioning and conversion for a single-
channel system.
The AD7715 is ideal for use in smart, microcontroller or DSP
based systems. It features a serial interface that can be config-
ured for three-wire operation. Gain settings, signal polarity and
update rate selection can be configured in software using the
input serial port. The part contains self-calibration and system
calibration options to eliminate gain and offset errors on the
part itself or in the system.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
*. Patent No: 5,134,401.See page 30 for data sheet index.
ANALOG INPUTS/REFERENCE INPUTS
LOGIC INPUTS
LOGIC OUTPUTS (Including MCLK OUT)
AD7715-5–SPECIFICATIONS (AVDD = +5␣V, DVDD = +3␣V or +5␣V, REF IN(+) = +2.5␣V; REF␣IN(–) = AGND;
fCLK IN = 2.4576␣MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
STATIC PERFORMANCE
ANALOG INPUTS/REFERENCE INPUTS
LOGIC INPUTS
AD7715AD7715-3–SPECIFICATIONS (AVDD = +3␣V, DVDD = +3 V, REF IN (+) = +1.25␣V;
REF␣IN(–) = AGND; fCLK IN = 2.4576␣MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
NOTESTemperature Range as follows: A Version, –40°C to +85°C.A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables V to XII. This applies after calibration at the
temperature of interest.Recalibration at any temperature will remove these drift errors.Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error–Unipolar Offset Error for unipolar ranges and Full-Scale Error–Bipolar Zero Error
for bipolar ranges.Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero scale calibrations only were performed.These numbers are guaranteed by design and/or characterization.This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN(–) does not go more positive than AVDD + 30 mV or go more nega-
tive than AGND – 30␣mV.The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(–). The absolute voltage on the analog inputs should not go more posi-
tive than AVDD + 30␣mV or go more negative than AGND␣– 30␣mV.VREF = REF IN(+) – REF IN(–).These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.Sample tested at +25°C to ensure compliance.After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AVDD + 30␣mV or go more negative than AGND –
30␣mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.Assumes CLK Bit of Setup Register is set to correct status corresponding to the master clock frequency.When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation will vary depending on
the crystal or resonator type (see Clocking and Oscillator Circuit section).Measured at dc and applies in the selected passband. PSRR at 50␣Hz will exceed 120␣dB with filter notches of 25 Hz or 50␣Hz. PSRR at 60␣Hz will exceed 120␣dB
with filter notches of 20 Hz or 60␣Hz.
AD7715–SPECIFICATIONS A (AVDD = +3␣V to +5␣V, DVDD = +3␣V to +5␣V, REF IN(+) = +1.25␣V (AD7715-3) or +2.5␣V
(AD7715-5); REF␣IN(–) = AGND; MCLK␣IN = 1␣MHz to 2.4576␣MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
TIMING CHARACTERISTICS1, 2NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.See Figures 6 and 7.CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7715 is not in Standby mode. If no clock is present in this case, the
device can draw higher current than specified and possibly become uncalibrated.The AD7715 is production tested with fCLKIN at 2.4576␣MHz (1␣MHz for some IDD tests). It is guaranteed by characterization to operate at 400␣kHz.These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.These numbers are derived from the measured time taken by the data output to change 0.5␣V when loaded with the circuit of Figure 1. The measured number is
then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and as such are independent of external bus loading capacitances.DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high although care
should be taken that subsequent reads do not occur close to the next output update.
Specifications subject to change without notice.
OUTPUT
PIN
+1.6V
ISINK (800mA AT DVDD = 5V
100mA AT DVDD = 3.3V)
ISOURCE (200mA AT DVDD = 5V
100mA AT DVDD = 3.3V)Figure 1.Load Circuit for Access Time and Bus Relinquish Time
(DVDD = +3␣V to +5.25␣V; AVDD = +3␣V to +5.25␣V; AGND = DGND = 0 V; fCLKIN = 2.4576␣MHz;
Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted)
AD7715
ORDERING GUIDE*N = Plastic DIP; R = SOIC RU = TSSOP.
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3␣V to +7␣V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3␣V to +7␣V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . .–0.3␣V to +7␣V
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3␣V to +7␣V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3␣V to +7␣V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . .–0.3␣V to +7␣V
Analog Input Voltage to AGND . . . . .–0.3 V to AVDD + 0.3␣V
Reference Input Voltage to AGND . . .–0.3 V to AVDD + 0.3␣V
Digital Input Voltage to DGND . . . . .–0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . .–0.3 V to DVDD + 0.3 V
Operating Temperature Range
Commercial (A Version) . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . .450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .105°C/W
Lead Temperature, (Soldering, 10 sec) . . . . . . . . . .+260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . .450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . .450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .128°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
Power Dissipation (Any Package) to +75°C . . . . . . . .450 mW
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4000V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
DIP, SOIC and TSSOP
PIN FUNCTION DESCRIPTION6AVDD
AD7715
TERMINOLOGY
Integral NonlinearityThis is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end-
points of the transfer function are Zero-Scale (not to be confused
with Bipolar Zero), a point 0.5 LSB below the first code transition
(000...000 to 000...001) and Full-Scale, a point 0.5␣LSB
above the last code transition (111...110 to 111...111). The
error is expressed as a percentage of full scale.
Positive Full-Scale ErrorPositive Full-Scale Error is the deviation of the last code transi-
tion (111...110 to 111...111) from the ideal AIN(+) voltage
(AIN(–) + VREF/GAIN –3/2 LSBs). It applies to both unipolar
and bipolar analog input ranges.
Unipolar Offset ErrorUnipolar Offset Error is the deviation of the first code transition
from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-
ating in the unipolar mode.
Bipolar Zero ErrorThis is the deviation of the midscale transition (0111...111
to 1000...000) from the ideal AIN(+) voltage (AIN(–)
– 0.5␣LSB) when operating in the bipolar mode.
Gain ErrorThis is a measure of the span error of the ADC. It includes full-
scale errors but not zero-scale errors. For unipolar input ranges
it is defined as (full scale error–unipolar offset error) while for
bipolar input ranges it is defined as (full-scale error–bipolar zero
error).
Bipolar Negative Full-Scale ErrorThis is the deviation of the first code transition from the ideal
AIN(+) voltage (AIN(–) – VREF/GAIN + 0.5␣LSB), when oper-
ating in the bipolar mode.
Positive Full-Scale OverrangePositive full-scale overrange is the amount of overhead available
to handle input voltages on AIN(+) input greater than AIN(–) +
VREF/GAIN (for example, noise peaks or excess voltages due to
system gain errors in system calibration routines) without intro-
ducing errors due to overloading the analog modulator or over-
flowing the digital filter.
Negative Full-Scale OverrangeThis is the amount of overhead available to handle voltages on
AIN(+) below AIN(–) –VREF/GAIN without overloading the
analog modulator or overflowing the digital filter. Note that the
analog input will accept negative voltage peaks even in the uni-
polar mode provided that AIN(+) is greater than AIN(–) and
greater than AGND –␣30␣mV.
Offset Calibration RangeIn the system calibration modes, the AD7715 calibrates its
offset with respect to the analog input. The offset calibration
range specification defines the range of voltages that the
AD7715 can accept and still calibrate offset accurately.
Full-Scale Calibration RangeThis is the range of voltages that the AD7715 can accept in the
system calibration mode and still calibrate full scale correctly.
Input SpanIn system calibration schemes, two voltages applied in sequence
to the AD7715’s analog input define the analog input range.
The input span specification defines the minimum and maxi-
mum input voltages from zero to full scale that the AD7715 can
accept and still calibrate gain accurately.
ON-CHIP REGISTERSThe part contains four on-chip registers which can be accessed by via the serial port on the part. The first of these is a Communica-
tions Register that decides whether the next operation is a read or write operation and also decides which register the read or write
operation accesses. All communications to the part must start with a write operation to the Communications Register. After power-
on or RESET, the device expects a write to its Communications Register. The data written to this register determines whether the
next operation to the part is a write or a read operation and also determines to which register this read or write operation occurs.
Therefore, write access to any of the other registers on the part starts with a write operation to the Communications Register fol-
lowed by a write to the selected register. A read operation from any register on the part (including the Communications Register itself
and the output data register) starts with a write operation to the Communications Register followed by a read operation from the
selected register. The Communication Register also controls the standby mode and the operating gain of the part. The DRDY status
is also available by reading from the Communications Register. The second register is a Setup Register that determines calibration
modes, filter selection and bipolar/unipolar operation. The third register is the Data Register from which the output data from the
part is accessed. The final register is a Test Register that is accessed when testing the device. It is advised that the user does not
attempt to access or change the contents of the test register as it may lead to unspecified operation of the device. The registers are
discussed in more detail in the following sections.
Communications Register (RS1, RS0 = 0, 0)The Communications Register is an eight-bit register from which data can either be read or to which data can be written. All com-
munications to the part must start with a write operation to the Communications Register. The data written to the Communications
Register determines whether the next operation is a read or write operation and to which register this operation takes place. Once the
subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to
the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7715 is in this
default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, if a
write operation to the device of sufficient duration (containing at least 32 serial clock cycles) takes place with DIN high, the AD7715
returns to this default state. Table I outlines the bit designations for the Communications Register.
Table I. Communications Register0/DRDYFor a write operation, a 0 must be written to this bit so that the write operation to the Communications Reg-
ister actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the regis-
ter. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to this bit, the next 7 bits
will be loaded to the Communications Register. For a read operation, this bit provides the status of theDRDY flag from the part. The status of this bit is the same as the DRDY output pin.
ZEROFor a write operation, a 0 must be written to this bit for correct operation of the part. Failure to do this will
result in unspecified operation of the device. For a read operation, a 0 will be read back from this bit location.
RS1– RS0Register Selection Bits. These bits select to which one of four on-chip registers the next read or write opera-
tion takes place as shown in Table II along with the register size. When the read or write to the selected regis-
ter is complete, the part returns to where it is waiting for a write operation to the Communications Register.
It does not remain in a state where it will continue to access the selected register.
R/WRead/Write Select. This bit selects whether the next operation is a read or write operation to the selected
register. A 0 indicates a write cycle as the next operation to the appropriate register, while a 1 indicates a read
operation from the appropriate register.
Table II.Register SelectionSTBYStandby. Writing a 1 to this bit puts the part in its standby or power-down mode. In this mode, the part
consumes only 10␣mA of power supply current. The part retains its calibration and control word information
when in STANDBY. Writing a 0 to this bit places the part in its normal operating mode. The default value
for this bit after power-on or RESET is 0.G1Gain Setting12321128
AD7715
Setup Register (RS1, RS0 = 0, 1); Power On/Reset Status: 28␣HexThe Setup Register is an eight-bit register from which data can either be read or to which data can be written. This register controls
the setup which the device is to operate in such as the calibration mode, output rate, unipolar/bipolar operation etc. Table III out-
lines the bit designations for the Setup Register.
Table III. Setup RegisterMD1MD0Operating Mode0Normal Mode; this is the normal mode of operation of the device whereby the device is performing normal
conversions. This is the default condition of these bits after Power-On or RESET.1Self-Calibration; this activates self-calibration on the part. This is a one step calibration sequence and when
complete the part returns to Normal Mode with MD1 and MD0 returning to 0, 0. The DRDY output or bit
goes high when calibration is initiated and returns low when this self-calibration is complete and a new valid
word is available in the data register. The zero-scale calibration is performed at the selected gain on internally
shorted (zeroed) inputs and the full-scale calibration is performed at the selected gain on an internally
generated VREF/Selected Gain.0Zero-Scale System Calibration; this activates zero-scale system calibration on the part. Calibration is per-
formed at the selected gain on the input voltage provided at the analog input during this calibration sequence.
This input voltage should remain stable for the duration of the calibration. The DRDY output or bit goes
high when calibration is initiated and returns low when this zero-scale calibration is complete and a new valid
word is available in the data register. At the end of the calibration, the part returns to Normal Mode with
MD1 and MD0 returning to 0, 0.1Full-Scale System Calibration; this activates full-scale system calibration on the part. Calibration is per-
formed at the selected gain on the input voltage provided at the analog input during this calibration sequence.
This input voltage should remain stable for the duration of the calibration. Once again, the DRDY output or
bit goes high when calibration is initiated and returns low when this full-scale calibration is complete and a
new valid word is available in the data register. At the end of the calibration, the part returns to Normal
Mode with MD1 and MD0 returning to 0, 0.
CLKClock Bit. This bit should be set in accordance with the operating frequency of the AD7715. If the device has
a master clock frequency of 2.4576␣MHz, then this bit should be set to a 1. If the device has a master clock
frequency of 1␣MHz, then this bit should be set to a 0. This bit sets up the correct scaling currents for a given
master clock and also chooses (along with FS1 and FS0) the output update rate for the device. If this bit is
not set correctly for the master clock frequency of the device, then the device may not operate to specifica-
tion. The default value for this bit after power-on or RESET is 1.
FS1, FS0Filter Selection Bits. Along with the CLK bit, FS1 and FS0 determine the output update rate, filter first
notch and –3 dB frequency as outlined in Table IV. The on-chip digital filter provides a Sinc3 (or (Sinx/x)3 )
filter response. In association with the gain selection, it also determines the output noise (and hence the
resolution) of the device. Changing the filter notch frequency, as well as the selected gain, impacts resolution.
Tables V through XII show the effect of the filter notch frequency and gain on the output noise and effective
resolution of the part. The output data rate (or effective conversion time) for the device is equal to the fre-
quency selected for the first notch of the filter. For example, if the first notch of the filter is selected at 50␣Hz
then a new word is available at a 50 Hz rate or every 20␣ms. If the first notch is at 500␣Hz, a new word is
available every 2␣ms. The default value for these bits is 1, 0.
The settling-time of the filter to a full-scale step input change is worst case 4 · 1/(output data rate). For
example, with the first filter notch at 50␣Hz, the settling time of the filter to a full-scale step input change is
80␣ms max. If the first notch is at 500␣Hz, the settling time of the filter to a full-scale input step is 8␣ms max.
This settling-time can be reduced to 3 · 1/(output data rate) by synchronizing the step input change to a
reset of the digital filter. In other words, if the step input takes place with the FSYNC bit high, the settling-
time time will be 3 · 1/(output data rate) from when FSYNC returns low.
The –3 dB frequency is determined by the programmed first notch frequency according to the relationship:
filter –3 dB frequency = 0.262 · filter first notch frequency.
Table IV.Output Update Rates*Assumes correct clock frequency at MCLK IN pin
B/UBipolar/Unipolar Operation. A 0 in this bit selects Bipolar Operation. This is the default (Power-On orRESET) status of this bit. A 1 in this bit selects unipolar operation.
BUFBuffer Control. With this bit low, the on-chip buffer on the analog input is shorted out. With the buffer
shorted out, the current flowing in the AVDD line is reduced to 250␣mA (all gains at fCLK IN = 1 MHz and gain
of 1 or 2 at fCLK IN = 2.4576 MHz) or 500␣mA (gains of 32 and 128 @ fCLK IN = 2.4576 MHz) and the output
noise from the part is at its lowest. When this bit is high, the on-chip buffer is in series with the analog input
allowing the input to handle higher source impedances.
FSYNCFilter Synchronization. When this bit is high, the nodes of the digital filter, the filter control logic and the
calibration control logic are held in a reset state and the analog modulator is also held in its reset state. When
this bit goes low, the modulator and filter start to process data and a valid word is available in 3 · 1/(output
update rate), i.e., the settling-time of the filter. This FSYNC bit does not affect the digital interface and does
not reset the DRDY output if it is low.
Test Register (RS1, RS0 = 1, 0)The part contains a Test Register which is used in testing the device. The user is advised not to change the status of any of the
bits in this register from the default (Power-On or RESET) status of all 0s as the part will be placed in one of its test modes and
will not operate correctly. If the part enters one of its test modes, exercising RESET will exit the part from the mode. An alterna-
tive scheme for getting the part out of one of its test modes, is to reset the interface by writing 32 successive 1s to the part and
then load all 0s to the Test Register.
Data Register (RS1, RS0 = 1, 1)The Data Register on the part is a read-only 16-bit register which contains the most up-to-date conversion result from the
AD7715. If the Communications Register data sets up the part for a write operation to this register, a write operation must actu-
ally take place to return the part to where it is expecting a write operation to the Communications Register (the default state of
the interface). However, the 16 bits of data written to the part will be ignored by the AD7715.
AD7715
OUTPUT NOISE
AD7715-5Table V shows the AD7715-5 output rms noise for the selectable notch and –3␣dB frequencies for the part, as selected by FS1 and
FS0 of the Setup Register. The numbers given are for the bipolar input ranges with a VREF of +2.5␣V. These numbers are typical
and are generated at a differential analog input voltage of 0␣V with the part used in unbuffered mode (BUF bit of the Setup Register
= 0). Table VI meanwhile shows the output peak-to-peak noise for the selectable notch and –3␣dB frequencies for the part. It is im-
portant to note that these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but
on peak-to-peak noise. The numbers given are for the bipolar input ranges with a VREF of +2.5␣V and for the BUF bit of the Setup
Register = 0. These numbers are typical, are generated at an analog input voltage of 0␣V and are rounded to the nearest LSB.
Meanwhile, Table VII and Table VIII show rms noise and peak-to-peak resolution respectively with the AD7715-5 operating under
the same conditions as above except that now the part is operating in buffered mode (BUF Bit of the Setup Register = 1).
Table V.Output RMS Noise vs. Gain and Output Update Rate for AD7715-5 (Unbuffered Mode)
Filter First Notch & O/P Data Rate
Table VI.Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-5 (Unbuffered Mode)
Table VII.Output RMS Noise vs. Gain and Output Update Rate for AD7715-5 (Buffered Mode)
Filter First Notch & O/P Data Rate
Table VIII.Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-5 (Buffered Mode)
AD7715-3Table IX shows the AD7715-3 output rms noise for the selectable notch and –3␣dB frequencies for the part, as selected by FS1 and
FS0 of the Setup Register. The numbers given are for the bipolar input ranges with a VREF of +1.25␣V. These numbers are typical
and are generated at an analog input voltage of 0␣V with the part used in unbuffered mode (BUF bit of the Setup Register = 0).
Table X meanwhile shows the output peak-to-peak noise for the selectable notch and –3␣dB frequencies for the part. It is important to
note that these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-
to-peak noise. The numbers given are for the bipolar input ranges with a VREF of +1.25␣V and for the BUF bit of the Setup Register =
0. These numbers are typical, are generated at an analog input voltage of 0␣V and are rounded to the nearest LSB.
Meanwhile, Table XI and Table XII show rms noise and peak-to-peak resolution respectively with the AD7715-3 operating under
the same conditions as above except that now the part is operating in buffered mode (BUF Bit of the Setup Register = 1).
Table IX.Output RMS Noise vs. Gain and Output Update Rate for AD7715-3 (Unbuffered Mode)
Filter First Notch & O/P Data Rate
Table X.Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-3 (Unbuffered Mode)
Table XI.Output RMS Noise vs. Gain and Output Update Rate for AD7715-3 (Buffered Mode)
Table XII.Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-3 (Buffered Mode)
Filter First Notch & O/P Data Rate
AD7715
CALIBRATION SEQUENCESThe AD7715 contains a number of calibration options as outlined previously. Table XIII summarizes the calibration types, the op-
erations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to
monitor when DRDY returns low at the end of the sequence. DRDY not only indicates when the sequence is complete but also that
the part has a valid new sample in its data register. This valid new sample is the result of a normal conversion which follows the cali-
bration sequence. The second method of determining when calibration is complete is to monitor the MD1 and MD0 bits of the
Setup Register. When these bits return to 0, 0 following a calibration command, it indicates that the calibration sequence is com-
plete. This method does not give any indication of there being a valid new result in the data register. However, it gives an earlier
indication than DRDY that calibration is complete. The duration to when the Mode Bits (MD1 and MD0) return to 0, 0 represents
the duration of the calibration carried out. The sequence to when DRDY goes low also includes a normal conversion and a pipeline
delay, tP, to correctly scale the results of this first conversion. tP will never exceed 2000 · tCLK IN. The time for both methods is given
in the table.
Table XIII.Calibration Sequences
CIRCUIT DESCRIPTIONThe AD7715 is a sigma-delta A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low frequency signals such as those in industrial control or pro-
cess control applications. It contains a sigma-delta (or charge-
balancing) ADC, a calibration microcontroller with on-chip
static RAM, a clock oscillator, a digital filter and a bidirectional
serial communications port. The part consumes only 450␣mA of
power supply current, making it ideal for battery-powered or
loop-powered instruments. The part comes in two versions, the
AD7715-5 which is specified for operation from a nominal
+5␣V analog supply (AVDD) and the AD7715-3 which is speci-
fied for operation from a nominal +3.3␣V analog supply. Both
versions can be operated with a digital supply (DVDD) voltage of
+3.3␣V or +5␣V.
The part contains a programmable-gain fully differential analog
input channel. The selectable gains on this input are 1, 2, 32
and 128 allowing the part to accept unipolar signals of between
0 mV to +20␣mV and 0 V to +2.5␣V or bipolar signals in the
range from –20␣mV to –2.5␣V when the reference input voltage
equals +2.5␣V. With a reference voltage of +1.25␣V, the input
ranges are from 0 mV to +10␣mV to 0 V to +1.25␣V in unipolar
mode and from –10␣mV to –1.25 V in bipolar mode. Note that
the bipolar ranges are with respect to AIN(–) and not with re-
spect to AGND.
The input signal to the analog input is continuously sampled at
a rate determined by the frequency of the master clock,
MCLK␣IN, and the selected gain. A charge-balancing A/D
converter (sigma-delta modulator) converts the sampled signal
into a digital pulse train whose duty cycle contains the digital
information. The programmable gain function on the analog
input is also incorporated in this sigma-delta modulator with the
input sampling frequency being modified to give the higher
gains. A sinc3 digital low-pass filter processes the output of the
sigma-delta modulator and updates the output register at a rate
determined by the first notch frequency of this filter. The out-
put data can be read from the serial port randomly or periodi-
cally at any rate up to the output register update rate. The first
notch of this digital filter (and hence its –3␣dB frequency) can be
programmed via the Setup Register bits FS0 and FS1. With a
master clock frequency of 2.4576␣MHz, the programmable
range for this first notch frequency is from 50␣Hz to 500␣Hz
giving a programmable range for the –3␣dB frequency of
13.1␣Hz to 131␣Hz. With a master clock frequency of 1␣MHz,
the programmable range for this first notch frequency is from
20␣Hz to 200␣Hz giving a programmable range for the –3␣dB
frequency of 5.24␣Hz to 52.4␣Hz.
The basic connection diagram for the AD7715-5 is shown in
Figure 2. This shows both the AVDD and DVDD pins of the
AD7715 being driven from the analog +5␣V supply. Some
applications will have AVDD and DVDD driven from separate
supplies. An AD780, precision +2.5 V reference, provides the
reference source for the part. On the digital side, the part is
configured for three-wire operation with CS tied to DGND. A
quartz crystal or ceramic resonator provides the master clock
source for the part. In most cases, it will be necessary to connect
capacitors on the crystal or resonator to ensure that it does
not oscillate at overtones of its fundamental operating fre-
quency. The values of capacitors will vary depending on the
manufacturer’s specifications.
CSAMP must be charged through RSW and through any external
source impedances every input sample cycle. Therefore, in
unbuffered mode, source impedances mean a longer charge time
for CSAMP, and this may result in gain errors on the part. Table
XIV shows the allowable external resistance/capacitance values,
for unbuffered mode, such that no gain error to the 16-bit level
is introduced on the part. Note that these capacitances are total
capacitances on the analog input, external capacitance plus
10 pF capacitance from the pins and lead frame of the device.
Table XIV.External R, C Combination for No 16-Bit Gain
Error (Unbuffered Mode Only)In buffered mode, the analog inputs look into the high imped-
ance inputs stage of the on-chip buffer amplifier. CSAMP is
charged via this buffer amplifier such that source impedances do
not affect the charging of CSAMP. This buffer amplifier has an
offset leakage current of 1 nA. In this buffered mode, large
source impedances result in a small dc offset voltage developed
across the source impedance but not in a gain error.
Input Sample RateThe modulator sample frequency for the AD7715 remains at
fCLK␣IN/128 (19.2␣kHz @ fCLK IN = 2.4576␣MHz) regardless of
the selected gain. However, gains greater than 1 are achieved by
a combination of multiple input samples per modulator cycle
and a scaling of the ratio of reference capacitor to input capaci-
tor. As a result of the multiple sampling, the input sample rate
of the device varies with the selected gain (see Table XV). In
buffered mode, the input is buffered before the input sampling
Table XV.Input Sampling Frequency vs. Gaincapacitor. In unbuffered mode, where the analog input looks
directly into the sampling capacitor, the effective input imped-
ance is 1/CSAMP · fS where CSAMP is the input sampling capaci-
tance and fS is the input sample rate.
Bipolar/Unipolar InputsThe analog input on the AD7715 can accept either unipolar or
bipolar input voltage ranges. Bipolar input ranges do not imply
that the part can handle negative voltages on its analog input
since the analog input cannot go more negative than –30␣mV to
ensure correct operation of the part. The input channel is fully
differential. As a result, the voltage to which the unipolar and
bipolar signals on the AIN(+) input are referenced is the voltage
0.1mF
ANALOG
GROUND
DIFFERENTIAL
ANALOG INPUT
DIGITAL
GROUND
ANALOG
+5V SUPPLY
DATA READY
RECEIVE (READ)
SERIAL DATA
SERIAL CLOCK
CRYSTAL OR
CERAMIC
RESONATOR
+5V
ANALOG
+5V SUPPLYFigure 2.AD7715-5 Basic Connection Diagram
ANALOG INPUT
Analog Input RangesThe AD7715 contains a differential analog input pair AIN(+)
and AIN(–). This input pair provides a programmable-gain,
differential input channel which can handle either unipolar or
bipolar input signals. It should be noted that the bipolar input
signals are referenced to the respective AIN(–) input of the
input pair.
In unbuffered mode, the common-mode range of the input is
from AGND to AVDD provided that the absolute value of the
analog input voltage lies between AGND␣–␣30␣mV and
AVDD␣+␣30␣mV. This means that in unbuffered mode the part
can handle both unipolar and bipolar input ranges for all gains.
In buffered mode, the analog inputs can handle much larger
source impedances but the absolute input voltage range is re-
stricted to between AGND␣+ 50␣mV to AVDD – 1.5␣V which
also places restrictions on the common-mode range. This means
that in buffered mode there are some restrictions on the allow-
able gains for bipolar input ranges. Care must be taken in set-
ting up the common-mode voltage and input voltage range so
that the above limits are not exceeded, otherwise there will be a
degradation in linearity performance.
In unbuffered mode, the analog inputs look directly into the
input sampling capacitor, CSAMP. The dc input leakage current
in this unbuffered mode is 1␣nA maximum. As a result, the
analog inputs see a dynamic load that is switched at the input
sample rate (see Figure 3). This sample rate depends on master
clock frequency and selected gain. CSAMP is charged to AIN(+)
and discharged to AIN(–) every input sample cycle. The effec-
tive on-resistance of the switch, RSW, is typically 7␣kW.
AIN(+)
AIN(–)
AD7715
DIGITAL FILTERINGThe AD7715 contains an on-chip low-pass digital filter that
processes the output of the part’s sigma-delta modulator. There-
fore, the part not only provides the analog-to-digital conversion
function but it also provides a level of filtering. There are a
number of system differences when the filtering function is
provided in the digital domain rather than the analog domain
and the user should be aware of these.
First, since digital filtering occurs after the A-to-D conversion
process, it can remove noise injected during the conversion
process. Analog filtering cannot do this. Also, the digital filter
can be made programmable far more readily than an analog
filter. Depending on the digital filter design, this gives the user
the capability of programming cutoff frequency and output
update rate.
On the other hand, analog filtering can remove noise superim-
posed on the analog signal before it reaches the ADC. Digital
filtering cannot do this and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
and digital filter, even though the average value of the signal is
within limits. To alleviate this problem, the AD7715 has over-
range headroom built into the sigma-delta modulator and digital
filter which allows overrange excursions of 5% above the analog
input range. If noise signals are larger than this, consideration
should be given to analog input filtering, or to reducing the
input channel voltage so that its full scale is half that of the
analog input channel full scale. This will provide an overrange
capability greater than 100% at the expense of reducing the
dynamic range by 1 bit (50%).
In addition, the digital filter does not provide any rejection at
integer multiples of the digital filter’s sample frequency. How-
ever, the input sampling on the part provides attenuation at
multiples of the digital filter’s sampling frequency so that the
unattenu-ated bands actually occur around multiples of the
sampling frequency fS (as defined in Table XV). Thus the unat-
tenuated bands occur at n · fS (where n = 1, 2, 3...). At these
frequencies, there are frequency bands, –f3 dB wide (f3 dB is the
cutoff frequency of the digital filter) at either side where noise
passes unattenuated to the output.
Filter CharacteristicsThe AD7715’s digital filter is a low-pass filter with a (sinx/x)3
response (also called sinc3). The transfer function for this filter
is described in the z-domain by:
and in the frequency domain by:
where N is the ratio of the modulator rate to the output rate and
fMOD is the modulator rate.
with a gain of 2 and a VREF of +2.5␣V, the input voltage range
on the AIN(+) input is +2.5␣V to +3.75␣V. If AIN(–) is +2.5␣V
and the AD7715 is configured for bipolar mode with a gain of 2
and a VREF of +2.5␣V, the analog input range on the AIN(+)
input is +1.25␣V to +3.75 V (i.e., 2.5␣V – 1.25␣V). If AIN(–) is
at AGND, the part cannot be configured for bipolar ranges in
excess of –30␣mV.
Bipolar or unipolar options are chosen by programming the B/U
bit of the Setup Register. This programs the channel for either
unipolar or bipolar operation. Programming the channel for
either unipolar or bipolar operation does not change any of the
input signal conditioning; it simply changes the data output
coding and the points on the transfer function where calibra-
tions occur.
REFERENCE INPUTThe AD7715’s reference inputs, REF␣IN(+) and REF␣IN(–),
provide a differential reference input capability. The common-
mode range for these differential inputs is from AGND to
AVDD. The nominal reference voltage, VREF (REF␣IN(+)␣–
REF␣IN(–)), for specified operation is +2.5␣V for the AD7715-5
and +1.25␣V for the AD7715-3. The part is functional with
VREF voltages down to 1 V but with degraded performance as
the output noise will, in terms of LSB size, be larger. REF␣IN(+)
must always be greater than REF␣IN(–) for correct operation of
the AD7715.
Both reference inputs provide a high impedance, dynamic load
similar to the analog inputs in unbuffered mode. The maximum
dc input leakage current is –1 nA over temperature and source
resistance may result in gain errors on the part. In this case, the
sampling switch resistance is 5␣kW typ and the reference capaci-
tor (CREF) varies with gain. The sample rate on the reference
inputs is fCLK IN/64 and does not vary with gain. For gains of 1
and 2, CREF is 8␣pF; for a gain of 32, it is 4.25␣pF, and for a gain
of 128, it is 3.3125␣pF.
The output noise performance outlined in Tables V through XII
is for an analog input of 0␣V which effectively removes the effect
of noise on the reference. To obtain the same noise performance
as shown in the noise tables over the full input range requires a
low noise reference source for the AD7715. If the reference
noise in the bandwidth of interest is excessive, it will degrade
the performance of the AD7715. In applications where the
excitation voltage for the bridge transducer on the analog input
also derives the reference voltage for the part, the effect of the
noise in the excitation voltage will be removed as the application
is ratiometric. Recommended reference voltage sources for the
AD7715-5 include the AD780, REF43 and REF192, while the
recommended reference sources for the AD7715-3 include the
AD589 and AD1580. It is generally recommended to decouple
the output of these references in order to further reduce the
noise level.
