AD7714AN-5 ,3 V/5 V, CMOS, 500 uA Signal Conditioning ADCFEATURESFUNCTIONAL BLOCK DIAGRAMCharge Balancing ADCDVAV REF IN(–) REF IN(+)DD DD24 Bits No Missing ..
AD7714ANZ-5 , 3 V/5 V, CMOS, 500 mu A Signal Conditioning ADC
AD7714AR-3 ,3 V/5 V, CMOS, 500 uA Signal Conditioning ADCapplications with a three-wire serial interface reducing the num-conversion for a system consisting ..
AD7714AR-5 ,3 V/5 V, CMOS, 500 uA Signal Conditioning ADCspecifications T to T unless otherwise noted.)CLK IN MIN MAXParameter A Versions Units Conditions/C ..
AD7714ARS-3 ,3 V/5 V, CMOS, 500 uA Signal Conditioning ADCspecifications T to T unless otherwise noted.)CLK IN MIN MAX1Parameter A Versions Units Conditions/ ..
AD7714ARS-5 ,3 V/5 V, CMOS, 500 uA Signal Conditioning ADCspecifications T to T unless otherwise noted.)CLK IN MIN MAX1Parameter A Versions Units Conditions/ ..
ADM1032ARMZ-1 , 1C Remote and Local System Temperature Monitor
ADM1032ARMZ-1RL , 1C Remote and Local System Temperature Monitor Supports SMBus Alert
ADM1032ARMZ-2RL7 , ±1℃ Remote and Local System Temperature Monitor
ADM1032ARMZ-R7 , ±1℃ Remote and Local System Temperature Monitor
ADM1032ARMZ-R7 , ±1℃ Remote and Local System Temperature Monitor
ADM1032AR-REEL ,High Accuracy, Remote Thermal Diode Monitor in Micro SOIC PackageFEATURES PRODUCT DESCRIPTIONOn-Chip and Remote Temperature Sensing The ADM1032 is a dual-channel di ..
AD7714AN-3-AD7714AN-5-AD7714AR-3-AD7714AR-5-AD7714ARS-3-AD7714ARS-5-AD7714YN-AD7714YR-AD7714YRU
3 V/5 V, CMOS, 500 uA Signal Conditioning ADC
FUNCTIONAL BLOCK DIAGRAMFEATURES
Charge Balancing ADC
24 Bits No Missing Codes
0.0015% Nonlinearity
Five-Channel Programmable Gain Front End
Gains from 1 to 128
Can Be Configured as Three Fully Differential
Inputs or Five Pseudo-Differential Inputs
Three-Wire Serial Interface
SPI™, QSPI™, MICROWIRE™ and DSP Compatible
3 V (AD7714-3) or 5 V (AD7714-5) Operation
Low Noise (<150nV rms)
Low Current (350␣mA typ) with Power-Down (5 mA typ)
AD7714Y Grade:
+2.7 V to 3.3 V or +4.75 V to +5.25 V Operation
0.0010% Linearity Error
–408C to +1058C Temperature Range
Schmitt Trigger on SCLK and DIN
Low Current (226␣mA typ) with Power-Down (4 mA typ)
Lower Power Dissipation than Standard AD7714
Available in 24-Lead TSSOP Package
Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
APPLICATIONS
Portable Industrial Instruments
Portable Weigh Scales
Loop-Powered Systems
Pressure Transducers
3 V/5 V, CMOS, 500
Signal Conditioning ADC
GENERAL DESCRIPTION†The AD7714 is a complete analog front end for low-frequency
measurement applications. The device accepts low level signals
directly from a transducer and outputs a serial digital word. It
employs a sigma-delta conversion technique to realize up to 24
bits of no missing codes performance. The input signal is applied
to a proprietary programmable gain front end based around an
analog modulator. The modulator output is processed by an on-
chip digital filter. The first notch of this digital filter can be
programmed via the on-chip control register allowing adjust-
ment of the filter cutoff and settling time.
The part features three differential analog inputs (which can also
be configured as five pseudo-differential analog inputs) as well as a
differential reference input. It operates from a single supply (+3␣V
or +5␣V). The AD7714 thus performs all signal conditioning and
conversion for a system consisting of up to five channels.
The AD7714 is ideal for use in smart, microcontroller- or DSP-
based systems. It features a serial interface that can be configured
REV. C
for three-wire operation. Gain settings, signal polarity and channel
selection can be configured in software using the serial port. The
AD7714 provides self-calibration, system calibration and back-
ground calibration options and also allows the user to read and
write the on-chip calibration registers.
CMOS construction ensures very low power dissipation, and the
power-down mode reduces the standby power consumption to
15␣mW typ. The part is available in a 24-pin, 0.3 inch-wide, plastic
dual-in-line package (DIP); a 24-lead small outline (SOIC)
package, a 28-lead shrink small outline package (SSOP) and a
24-lead thin shrink small outline package (TSSOP).
PRODUCT HIGHLIGHTSThe AD7714Y offers the following features in addition to the
standard AD7714: wider temperature range, Schmitt trigger
on SCLK and DIN, operation down to 2.7 V, lower power
consumption, better linearity, and availability in 24-lead
TSSOP package.The AD7714 consumes less than 500 mA (fCLK IN = 1␣MHz)
or 1 mA (fCLK IN = 2.5␣MHz) in total supply current, making
it ideal for use in loop-powered systems.The programmable gain channels allow the AD7714 to ac-
cept input signals directly from a strain gage or transducer
removing a considerable amount of signal conditioning.The AD7714 is ideal for microcontroller or DSP processor
applications with a three-wire serial interface reducing the num-
ber of interconnect lines and reducing the number of opto-
couplers required in isolated systems. The part contains
on-chip registers that allow control over filter cutoff, input gain,
channel selection, signal polarity and calibration modes.The part features excellent static performance specifications
with 24-bit no missing codes, –0.0015% accuracy and low
rms noise (140 nV). Endpoint errors and the effects of tem-
perature drift are eliminated by on-chip self-calibration,
*. Patent No. 5,134,401.†See page 39 for data sheet index.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
NOTESTemperature range is as follows: A Versions: –40°C to +85°C.A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I to IV. This applies after calibration at the temperature of interest.Recalibration at any temperature will remove these drift errors.
AD7714-5–SPECIFICATIONS(AVDD = +5␣V, DVDD = +3.3␣V or +5␣V, REF IN(+) = +2.5␣V; REF␣IN(–) = AGND;
fCLK IN = 2.4576␣MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
ANALOG INPUTS/REFERENCE INPUTS
LOGIC INPUTS
LOGIC OUTPUTS (Including MCLK OUT)
NOTESGain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero-scale calibrations only were performed as is the case with
background calibration.These numbers are guaranteed by design and/or characterization.The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.
AD7714-3–SPECIFICATIONS(AVDD = +3.3␣V, DVDD = +3.3␣V, REF IN(+) = +1.25␣V; REF␣IN(–) = AGND;
fCLK IN = 2.4576␣MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
AD7714
AD7714–SPECIFICATIONSSYSTEM CALIBRATION
NOTESAfter calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AVDD + 30␣mV or go more negative than AGND␣–␣30␣mV. The
offset calibration limit applies to both the unipolar zero point and the bipolar zero point.For higher gains (‡8) at fCLK␣IN = 2.4576␣MHz, the BST bit of the Filter High Register must be set to 1. For other conditions, it can be set to 0.When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation will vary depending on the crystal
or resonator type (see Clocking and Oscillator Circuit section).Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120dB
with filter notches of 6 Hz, 10 Hz, 30 Hz or 60 Hz.PSRR depends on gain. For Gain of 1 : 70 dB typ: For Gain of 2 : 75 dB typ; For Gain of 4 : 80 dB typ; For Gains of 8 to 128 : 85 dB typ.If the external master clock continues to run in standby mode, the standby current increases to 150 mA typical with 5 V supplies and 75 mA typical with 3.3 V supplies. When
using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation
depends on the crystal or resonator type (see Standby Mode section).
Specifications subject to change without notice.
(AVDD = + 3.3␣V to +5␣V, DVDD = +3.3␣V to +5␣V, REF IN(+) = +1.25␣V (AD7714-3) or +2.5␣V
(AD7714-5); REF␣IN(–) = AGND; MCLK␣IN = 1␣MHz to 2.4576␣MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
STATIC PERFORMANCE
ANALOG INPUTS/REFERENCE INPUTS
LOGIC INPUTS
AD7714Y–SPECIFICATIONS (AVDD = DVDD = +2.7␣V to +3.3␣V or 4.75 V to 5.25 V, REF IN(+) = +1.25␣V; with AVDD = 3 V
and +2.5 V with AVDD = 5 V; REF␣IN(–) = AGND; MCLK IN = 2.4576␣MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
AD7714
TRANSDUCER BURNOUT
NOTESTemperature range is as follows: Y Version: –40°C to +105°C.A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I to IV. This applies after calibration at the temperature of interest.Recalibration at any temperature will remove these drift errors.Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error—Unipolar Offset Error for unipolar ranges and Full-Scale Error—Bipolar Zero Error for
bipolar ranges.Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero-scale calibrations only were performed as is the case with background calibration.These numbers are guaranteed by design and/or characterization.The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.The input voltage range on the analog inputs is given here with respect to the voltage on the respective negative input of its differential or pseudo-differential pair. See Table VII for which
inputs form differential pairs.VREF = REF IN(+) – REF IN(–).These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.Sample tested at +25°C to ensure compliance.See Burnout Current section.After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AVDD + 30␣mV or go more negative than AGND␣–␣30␣mV. The offset calibration
limit applies to both the unipolar zero point and the bipolar zero point.For higher gains (‡8) at fCLK␣IN = 2.4576␣MHz, the BST bit of the Filter High Register must be set to 1. For other conditions, it can be set to 0.When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation will vary depending on the crystal or resonator
type (see Clocking and Oscillator Circuit section).Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120dB with filter
notches of 6 Hz, 10 Hz, 30 Hz or 60 Hz.PSRR depends on gain.
AD7714Y
ORDERING GUIDE
TIMING CHARACTERISTICS1, 2(AVDD = DVDD = +2.7 V to +5.25 V; AGND = DGND = 0 V; fCLKIN = 2.5␣MHz; Input Logic 0 = 0 V,
Logic 1 = DVDD unless otherwise noted.)tCLK IN LO
Read Operation
t10
t13
t14
t15
NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.2See Figures 6 and 7. Timing applies for all grades.CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7714 is not in standby mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.The AD7714 is production tested with fCLKIN at 2.4576␣MHz (1␣MHz for some IDD tests). It is guaranteed by characterization to operate at 400␣kHz.SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0.These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.7These numbers are derived from the measured time taken by the data output to change 0.5␣V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high although care
should be taken that subsequent reads do not occur close to the next output update.
Specifications subject to change without notice.
TO OUTPUT
PIN
+1.6V
AD7714
DIP and SOIC/TSSOP
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3␣V to +7␣V
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3␣V to +7␣V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3␣V to +7␣V
Analog Input Voltage to AGND . . . . .–0.3 V to AVDD + 0.3␣V
Reference Input Voltage to AGND . . .–0.3 V to AVDD + 0.3␣V
Digital Input Voltage to DGND . . . . .–0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . .–0.3 V to DVDD + 0.3 V
Operating Temperature Range
Commercial (A Version) . . . . . . . . . . . . . . .–40°C to +85°C
Extended (Y Version) . . . . . . . . . . . . . . . . .–40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . .450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .105°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . .450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . .450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .109°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . .450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .128°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may still
occur on these devices if they are subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
SSOP
SCLK
MCLK IN
SYNC
AIN1
MCLK OUT
POL
AIN2
AIN3
AIN4
STANDBY
AVDDRESET
SCLK
MCLK IN
SYNC
RESET
MCLK OUT
POLNC
AIN1
AIN2
AIN3
AIN4
STANDBY
AVDD
PIN FUNCTION DESCRIPTION
DIP/SOIC PIN NUMBERSAD7714
PIN FUNCTION DESCRIPTION (Continued)
BIPOLAR NEGATIVE FULL-SCALE ERRORThis is the deviation of the first code transition from the ideal
AIN(+) voltage (AIN(–) – VREF/GAIN + 0.5␣LSB) when operat-
ing in the bipolar mode.
POSITIVE FULL-SCALE OVERRANGEPositive Full-Scale Overrange is the amount of overhead avail-
able to handle input voltages on AIN(+) input greater than
AIN(–) + VREF/GAIN (for example, noise peaks or excess volt-
ages due to system gain errors in system calibration routines)
without introducing errors due to overloading the analog modu-
lator or overflowing the digital filter.
NEGATIVE FULL-SCALE OVERRANGEThis is the amount of overhead available to handle voltages on
AIN(+) below AIN(–) – VREF/GAIN without overloading the
analog modulator or overflowing the digital filter. Note that the
analog input will accept negative voltage peaks even in the uni-
polar mode provided that AIN(+) is greater than AIN(–) and
greater than AGND – 30␣mV.
OFFSET CALIBRATION RANGEIn the system calibration modes, the AD7714 calibrates its
offset with respect to the analog input. The Offset Calibration
Range specification defines the range of voltages that the
AD7714 can accept and still calibrate offset accurately.
FULL-SCALE CALIBRATION RANGEThis is the range of voltages that the AD7714 can accept in the
system calibration mode and still calibrate full scale correctly.
INPUT SPANIn system calibration schemes, two voltages applied in sequence
to the AD7714’s analog input define the analog input range.
The input span specification defines the minimum and maxi-
TERMINOLOGY*
INTEGRAL NONLINEARITYThis is the maximum deviation of any code from a straight line
passingthroughtheendpointsofthetransferfunction. The end-
points of the transfer function are zero scale (not to be confused
withbipolarzero),apoint0.5LSBbelowthefirstcode transi-
tion (000...000 to 000...001) and full scale, a point
0.5LSB abovethelastcodetransition(111...110to
111...111). The error is expressed as a percentage of full
scale.
POSITIVE FULL-SCALE ERRORPositive Full-Scale Error is the deviation of the last code transi-
tion (111...110 to 111...111) from the ideal AIN(+) voltage
(AIN(–) + VREF/GAIN – 3/2 LSBs). It applies to both unipolar
and bipolar analog input ranges.
UNIPOLAR OFFSET ERRORUnipolar Offset Error is the deviation of the first code transition
from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-
ating in the unipolar mode.
BIPOLAR ZERO ERRORThis is the deviation of the midscale transition (0111...111
to 1000...000) fromtheidealAIN(+)voltage(AIN(–)–
0.5LSB) when operating in the bipolar mode.
GAIN ERRORThis is a measure of the span error of the ADC. It includes full-
scale errors but not zero-scale errors. For unipolar input ranges
it is defined as (full-scale error – unipolar offset error) while for
bipolar input ranges it is defined as (full-scale error – bipolar
zero error).
AD7714-5 OUTPUT NOISETable Ia shows the output rms noise and effective resolution for some typical notch and –3␣dB frequencies for the AD7714-5 with
fCLK␣IN = 2.4576␣MHz while Table Ib gives the information for fCLK IN = 1␣MHz. The numbers given are for the bipolar input ranges
with a VREF of +2.5␣V and with BUFFER = 0. These numbers are typical and are generated at an analog input voltage of 0␣V. The
numbers in brackets in each table are for the effective resolution of the part (rounded to the nearest 0.5␣LSB). The effective resolu-
tion of the device is defined as the ratio of the output rms noise to the input full scale (i.e., 2 · VREF/GAIN). It should be noted that
it is not calculated using peak-to-peak output noise numbers. Peak-to-peak noise numbers can be up to 6.6 times the rms numbers
while effective resolution numbers based on peak-to-peak noise can be 2.5 bits below the effective resolution based on rms noise as
quoted in the tables.
The output noise from the part comes from two sources. The first is the electrical noise in the semiconductor devices used in the
implementation of the modulator (device noise). Secondly, when the analog input signal is converted into the digital domain, quan-
tization noise is added. The device noise is at a low level and is largely independent of frequency. The quantization noise starts at
an even lower level but rises rapidly with increasing frequency to become the dominant noise source. Consequently, lower filter
notch settings (below 100␣Hz approximately for fCLK IN = 2.4576␣MHz and below 40␣Hz approximately for fCLK IN = 1␣MHz) tend to
be device noise dominated while higher notch settings are dominated by quantization noise. Changing the filter notch and cutoff
frequency in the quantization-noise dominated region results in a more dramatic improvement in noise performance than it does in
the device-noise dominated region as shown in Table I. Furthermore, quantization noise is added after the PGA, so effective resolu-
tion is largely independent of gain for the higher filter notch frequencies. Meanwhile, device noise is added in the PGA and, there-
fore, effective resolution reduces at high gains for lower notch frequencies. Additionally, in the device-noise dominated region, the
output noise (in mV) is largely independent of reference voltage while in the quantization-noise dominated region, the noise is pro-
portional to the value of the reference. It is possible to do post-filtering on the device to improve the output data rate for a given
–3␣dB frequency and also to further reduce the output noise.
At the lower filter notch settings (below 60␣Hz for fCLK IN = 2.4576␣MHz and below 25␣Hz for fCLK IN = 1␣MHz), the no missing
codes performance of the device is at the 24-bit level. At the higher settings, more codes will be missed until at 1␣kHz notch setting
for fCLK␣IN = 2.4576␣MHz (400␣Hz for fCLK IN = 1␣MHz), no missing codes performance is only guaranteed to the 12-bit level.
Table Ia.AD7714-5 Output Noise/Resolution vs. Gain and First Notch for fCLK IN = 2.4576␣MHz, BUFFER = 0
Table Ib.AD7714-5 Output Noise/Resolution vs. Gain and First Notch for fCLK IN = 1␣MHz, BUFFER = 0
AD7714
AD7714-3 OUTPUT NOISETable IIa shows the output rms noise and effective resolution for some typical notch and –3␣dB frequencies for the AD7714-3 with
fCLK␣IN = 2.4576␣MHz while Table IIb gives the information for fCLK IN = 1␣MHz. The numbers given are for the bipolar input
ranges with a VREF of +1.25␣V and BUFFER = 0. These numbers are typical and are generated at an analog input voltage of 0␣V.
The numbers in brackets in each table are for the effective resolution of the part (rounded to the nearest 0.5␣LSB). The effective
resolution of the device is defined as the ratio of the output rms noise to the input full scale (i.e., 2 · VREF/GAIN). It should be
noted that it is not calculated using peak-to-peak output noise numbers. Peak-to-peak noise numbers can be up to 6.6 times the rms
numbers while effective resolution numbers based on peak-to-peak noise can be 2.5 bits below the effective resolution based on rms
noise as quoted in the tables.
The output noise from the part comes from two sources. The first is the electrical noise in the semiconductor devices used in the
implementation of the modulator (device noise). Secondly, when the analog input signal is converted into the digital domain, quan-
tization noise is added. The device noise is at a low level and is largely independent of frequency. The quantization noise starts at
an even lower level but rises rapidly with increasing frequency to become the dominant noise source. Consequently, lower filter
notch settings (below 100␣Hz approximately for fCLK IN = 2.4576␣MHz and below 40␣Hz approximately for fCLK IN = 1␣MHz) tend to
be device noise dominated while higher notch settings are dominated by quantization noise. Changing the filter notch and cutoff
frequency in the quantization noise dominated region results in a more dramatic improvement in noise performance than it does in
the device-noise dominated region as shown in Table II. Furthermore, quantization noise is added after the PGA, so effective reso-
lution is largely independent of gain for the higher filter notch frequencies. Meanwhile, device noise is added in the PGA and, there-
fore, effective resolution suffers a little at high gains for lower notch frequencies. Additionally, in the device-noise dominated region,
the output noise (in mV) is largely independent of reference voltage while in the quantization-noise dominated region, the noise is
proportional to the value of the reference. It is possible to do post-filtering on the device to improve the output data ratefor a given
–3␣dB frequency and also to further reduce the output noise.
At the lower filter notch settings (below 60␣Hz for fCLK IN = 2.4576␣MHz and below 25␣Hz for fCLK IN = 1␣MHz), the no missing
codes performance of the device is at the 24-bit level. At the higher settings, more codes will be missed until at 1␣kHz notch setting
for fCLK␣IN = 2.4576␣MHz (400␣Hz for fCLK IN = 1␣MHz), no missing codes performance is only guaranteed to the 12-bit level.
Table IIa.AD7714-3 Output Noise/Resolution vs. Gain and First Notch for fCLK IN = 2.4576␣MHz, BUFFER = 0
Table IIb.AD7714-3 Output Noise/Resolution vs. Gain and First Notch for fCLK IN = 1␣MHz, BUFFER = 0
BUFFERED MODE NOISETable III shows the typical output rms noise and effective resolution for some typical notch and –3␣dB frequencies for the AD7714-
5 with fCLK␣IN = 2.4576␣MHz and BUFFER = +5 V. Table IV gives the information for the AD7714-3 again with fCLK IN = 2.4576
MHz and BUFFER = +5␣V. The numbers given are for the bipolar input ranges and are generated with a differential analog input
voltage of 0␣V. For the AD7714-5, the VREF voltage is +2.5␣V while for the AD7714 the VREF voltage is +1.25␣V. The numbers in
brackets in each table are for the effective resolution of the part (rounded to the nearest 0.5 LSB). The effective resolution of the
device is defined as the ratio of the output rms noise to the input full scale (i.e., 2 · VREF/GAIN). It should be noted that it is not
calculated using peak-to-peak output noise numbers. Peak-to-peak noise numbers can be up to 6.6 times the rms numbers while
effective resolution numbers based on peak-to-peak noise can be 2.5 bits below the effective resolution based on rms noise as quoted
in the tables.
Table III.AD7714-5 Buffered Mode Output Noise/Resolution for fCLK IN = 2.4576␣MHz
Table IV.AD7714-3 Buffered Mode Output Noise/Resolution for fCLK IN = 2.4576␣MHz
AD7714
ON-CHIP REGISTERSThe AD7714 contains eight on-chip registers which can be accessed via the serial port of the part. The first of these is a Communica-
tions Register which controls the channel selection, decides whether the next operation is a read or write operation and also decides
which register the next read or write operation accesses. All communications to the part must start with a write operation to the
Communications Register. After power-on or RESET, the device expects a write to its Communications Register. The data written
to this register determines whether the next operation to the part is a read or a write operation and also determines to which register
this read or write operation occurs. Therefore, write access to any of the other registers on the part starts with a write operation to the
Communications Register followed by a write to the selected register. A read operation from any other register on the part (including
the output data register) starts with a write operation to the Communications Register followed by a read operation from the selected
register. The communications register also controls channel selection and the DRDY status is also available by reading from the
Communications Register. The second register is a Mode Register which determines calibration mode and gain setting. The third
register is labelled the Filter High Register and this determines the word length, bipolar/unipolar operation and contains the upper 4
bits of the filter selection word. The fourth register is labelled the Filter Low Register and contains the lower 8 bits of the filter selec-
tion word. The fifth register is a Test Register which is accessed when testing the device. The sixth register is the Data Register from
which the output data from the part is accessed. The final registers allow access to the part’s calibration registers. The Zero Scale
Calibration Register allows access to the zero scale calibration coefficients for the selected input channel while the Full Scale Calibra-
tion Register allows access to the full scale calibration coefficients for the selected input channel. The registers are discussed in more
detail in the following sections.
Communications Register (RS2-RS0 = 0, 0, 0)The Communications Register is an 8-bit register from which data can either be read or to which data can be written. All communi-
cations to the part must start with a write operation to the Communications Register. The data written to the Communications Reg-
ister determines whether the next operation is a read or write operation and to which register this operation takes place. Once the
subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to
the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7714 is in this
default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, if a
write operation of sufficient duration (containing at least 32 serial clock cycles) takes place with DIN high, the AD7714 returns to
this default state. Table V outlines the bit designations for the Communications Register.
Table V.Communications Register
Table VI.Register Selection0/DRDYFor a write operation, a 0 must be written to this bit so that the write operation to the Communications Register
actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the register. It will stay
at this bit location until a 0 is written to this bit. Once a 0 is written to this bit, the next 7 bits will be loaded to the
Communications Register. For a read operation, this bit provides the status of the DRDY flag from the part. The
status of this bit is the same as the DRDY output pin.
RS2–RS0Register Selection Bits. RS2 is the MSB of the three selection bits. The three bits select to which one of eight on-chip
registers the next read or write operation takes place as shown in Table VI along with the register size.
Mode Register (RS2-RS0 = 0, 0, 1); Power On/Reset Status: 00␣HexThe Mode Register is an eight bit register from which data can either be read or to which data can be written. Table VIII outlines the
bit designations for the Mode Register.
Table VIII.Mode Register
Table VII.Channel SelectionCH2–CH0Channel Select. These three bits select a channel either for conversion or for access to calibration coefficients as
outlined in Table VII. There are three pairs of calibration registers on the part. In fully differential mode, the part
has three input channels so each channel has its own pair of calibration registers. In pseudo-differential mode, the
AD7714 has five input channels with some of the input channel combinations sharing calibration registers. With
CH2, CH1 and CH0 at a logic 1, the part looks at the AIN6 input internally shorted to itself. This can be used as
a test method to evaluate the noise performance of the part with no external noise sources. In this mode, the AIN6
input should be connected to an external voltage within the allowable common-mode range for the part. The
Power-On or RESET status of these bits is 1,0,0 selecting the differential pair AIN1 and AIN2.
AD7714FSYNC
Filter Registers. Power On/Reset Status: Filter High Register: 01␣Hex. Filter Low Register: 40␣Hex.There are two 8-bit Filter Registers on the AD7714 from which data can either be read or to which data can be written. Tables IX
and X outline the bit designations for the Filter Registers.
Table IX.Filter High Register (RS2–RS0 = 0, 1, 0)A VersionsY Versions
Table X.Filter Low Register (RS2–RS0 = 0, 1, 1)All Versions
AD7714
Test Register (RS2–RS0 = 1, 0, 0)The part contains a Test Register which is used in testing the device. The user is advised not to change the status of any of the bits in this
register from the default (Power-On or RESET) status of all 0s as the part will be placed in one of its test modes and will not operate cor-
rectly. If the part enters one of its test modes, exercising RESET will exit the part from the mode. An alternative scheme for getting the
part out of one of its test modes, is to reset the interface by writing 32 successive 1s to the part and then write all 0s to the Test Register.
Data Register (RS2–RS0 = 1, 0, 1)The Data Register on the part is a read-only register which contains the most up-to-date conversion result from the AD7714. The
register can be programmed to be either 16-bits or 24-bits wide, determined by the status of the WL bit of the Mode Register. If the
Communications Register data sets up the part for a write operation to this register, a write operation must actually take place in
order to return the part to where it is expecting a write operation to the Communications Register (the default state of the interface).
However, the 16 or 24 bits of data written to the part will be ignored by the AD7714.
Zero-Scale Calibration Register (RS2–RS0 = 1, 1, 0); Power On/Reset Status: 1F4000␣HexThe AD7714 contains three zero-scale calibration registers, labelled Zero-Scale Calibration Register 0 to Zero Scale Calibration
Register␣2. The three registers are totally independent of each other such that in fully differential mode there is a zero-scale register
for each of the input channels. Each of these registers is a 24-bit read/write register and, when writing to the registers, 24 bits must be
written; otherwise no data will be transferred to the register. The register is used in conjunction with the associated full-scale calibra-
tion register to form a register pair. These register pairs are associated with input channel pairs as outlined in Table VII.
While the part is set up to allow access to these registers over the digital interface, the part itself no longer has access to the register
coefficients to correctly scale the output data. As a result, there is a possibility that after accessing the calibration registers (either read
or write operation) the first output data read from the part may contain incorrect data. In addition, a read or write operation to the
calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by taking either theSYNC input low or the FSYNC bit of the Mode Register high before the calibration register operation and taking them either high or
low respectively after the operation is complete.
Full-Scale Calibration Register (RS2–RS0 = 1, 1, 1); Power On/Reset Status: 5761AB␣HexThe AD7714 contains three full-scale calibration registers, labelled Full-Scale Calibration Register 0 to Full-Scale Calibration Regis-
ter 2. The three registers are totally independent of each other such that in fully differential mode there is a full-scale register for each
of the input channels. Each of these registers is a 24-bit read/write register and, when writing to the registers, 24 bits must be written,
otherwise no data will be transferred to the register. The register is used in conjunction with the associated zero-scale calibration
register to form a register pair. These register pairs are associated with input channel pairs as outlined in Table␣VII.
While the part is set up to allow access to these registers over the digital interface, the part itself no longer has access to the coeffi-
cients to correctly scale the output data. As a result, there is a possibility that after accessing the calibration registers (either read or
write operation) the first output data read from the part may contain incorrect data. In addition, a read or write operation to the
calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by taking either theSYNC input low or the FSYNC bit of the Mode Register high before the calibration register operation and taking them either high or
low respectively after the operation is complete.
CALIBRATION OPERATIONSThe AD7714 contains a number of calibration options as outlined previously. Table XI summarizes the calibration types, the opera-
tions involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to moni-
tor when DRDY returns low at the end of the sequence. DRDY not only indicates when the sequence is complete but also that the
part has a valid new sample in its data register. This valid new sample is the result of a normal conversion which follows the calibra-
tion sequence. The second method of determining when calibration is complete is to monitor the MD2, MD1 and MD0 bits of the
Mode Register. When these bits return to 0, 0, 0 following a calibration command, it indicates that the calibration sequence is com-
plete. This method does not give any indication of there being a valid new result in the data register. However, it gives an earlier
indication that calibration is complete than DRDY. The time to when the Mode Bits (MD2, MD1 and MD0) return to 0, 0, 0
represents the duration of the calibration. The sequence to when DRDY goes low also includes a normal conversion and a pipeline
delay, tP (2000 · tCLK IN), to correctly scale the results of this first conversion. The time for both methods is given in the table.
Table XI.Calibration Operations
CIRCUIT DESCRIPTIONThe AD7714 is a sigma-delta A/D converter with on-chip digi-
tal filtering, intended for the measurement of wide dynamic
range, low frequency signals such as those in weigh-scale, pres-
sure transducer, industrial control or process control applica-
tions. It contains a sigma-delta (or charge-balancing) ADC, a
calibration microcontroller with on-chip static RAM, a clock
oscillator, a digital filter and a bidirectional serial communica-
tions port. The part consumes only 500mA of power supply
current and features a standby mode which requires only 10mA,
making it ideal for battery-powered or loop-powered instru-
ments. The part comes in two versions, the AD7714-5, which is
specified for operation from a nominal +5␣V analog supply
(AVDD), and the AD7714-3, which is specified for operation
from a nominal +3.3␣V analog supply. Both versions can be
operated with a digital supply (DVDD) voltage of either +3.3␣V
or +5␣V. AD7714Y grade parts operate with a nominal AVDD
of 3 V or 5 V and can be operated with a digital supply voltage
of either 3 V or 5 V.
The part contains three programmable-gain fully differential
analog input channels that can be reconfigured as five pseudo-
differential inputs. The gain range on all channels is from 1 to
128, allowing the part to accept unipolar signals of betweenmV to +20␣mV and 0V to +2.5␣V. In bipolar mode, the part
handles genuine bipolar signals of –20mV and quasi-bipolar
signals up to –2.5V when the reference input voltage equals
+2.5␣V. With a reference voltage of +1.25␣V, the input ranges
are from 0mV to +10mV to 0V to +1.25␣V in unipolar mode,
while in bipolar mode, the part handles genuine bipolar signals
of –10mV and quasi-bipolar signals up to –1.25V.
The part employs a sigma-delta conversion technique to realize
up to 24 bits of no missing codes performance. The sigma-delta
modulator converts the sampled input signal into a digital pulse
train whose duty cycle contains the digital information. The
programmable gain function on the analog input is also
incorporated in this sigma-delta modulator with the input sam-
pling frequency of the modulator being modified to give the
higher gains. A sinc3 digital low-pass filter processes the output
of the sigma-delta modulator and updates the output register at
a rate determined by the first notch frequency of this filter. The
output data can be read from the serial port randomly or peri-
odically at any rate up to the output register update rate. The
first notch of this digital filter, its –3␣dB frequency and its out-
put rate can be programmed via the filter high and filter low
registers. With a master clock frequency of 2.4576MHz, the
programmable range for this first notch frequency and output
rate is from 4.8␣Hz to 1.01kHz giving a programmable range
for the –3␣dB frequency of 1.26Hz to 265␣Hz.
The basic connection diagram for the part is shown in Figure 2.
This shows both the AVDD and DVDD pins of the AD7714 being
driven from the analog +3␣V or +5␣V supply. Some applications
will have AVDD and DVDD driven from separate supplies. In the
connection diagram shown, the AD7714’s analog inputs are
configured as three fully differential inputs. The part is set up
for unbuffered mode on the these analog inputs. An AD780,
precision +2.5 V reference, provides the reference source for the
part. On the digital side, the part is configured for three-wire
operation with CS tied to DGND. A quartz crystal or ceramic
resonator provides the master clock source for the part. It may
be necessary to connect capacitors on the crystal or resonator to
0.1mF
ANALOG
GROUND
DIFFERENTIAL
ANALOG INPUT 3
DIFFERENTIAL
ANALOG INPUT 2
DIFFERENTIAL
ANALOG INPUT 1
DIGITAL
ANALOG
+5V SUPPLY
ANALOG
+5V SUPPLY
DATA
READY
RECEIVE
(READ)
SERIAL
DATA
SERIAL
CLOCK
CRYSTAL OR
CERAMIC
RESONATOR
+5VFigure 2.Basic Connection Diagram
AD7714
ANALOG INPUT
Analog Input RangesThe AD7714 contains six analog input pins (labelled AIN1 to
AIN6) which can be configured as either three fully differential
input channels or five pseudo-differential input channels. Bits
CH0, CH1 and CH2 of the Communications Register configure
the analog input arrangement and the channel selection is as
outlined previously in Table VII. The input pairs (either differ-
ential or pseudo-differential) provide programmable-gain, input
channels which can handle either unipolar or bipolar input
signals. It should be noted that the bipolar input signals are
referenced to the respective AIN(–) input of the input pair.
In unbuffered mode, the common-mode range of these inputs is
from AGND to AVDD provided that the absolute value of the analog
input voltage lies between AGND␣–␣30␣mV and AVDD + 30␣mV.
This means that in unbuffered mode the part can handle both
unipolar and bipolar input ranges for all gains. In buffered
mode, the analog inputs can handle much larger source imped-
ances, but the absolute input voltage range is restricted to be-
tween AGND␣+ 50␣mV to AVDD – 1.5␣V which also places
restrictions on the common-mode range. This means that in
buffered mode there are some restrictions on the allowable gains
for bipolar input ranges. Care must be taken in setting up the
common-mode voltage and input voltage range so that the
above limits are not exceeded, otherwise there will be a degrada-
tion in linearity performance.
In unbuffered mode, the analog inputs look directly into thepF input sampling capacitor, CSAMP. The dc input leakage
current in this unbuffered mode is 1␣nA maximum. As a result,
the analog inputs see a dynamic load which is switched at the
input sample rate (see Figure 3). This sample rate depends on
master clock frequency and selected gain. CSAMP is charged to
AIN(+) and discharged to AIN(–) every input sample cycle.
The effective on-resistance of the switch, RSW, is typically 7␣kW.
CSAMP must be charged through RSW and through any external
source impedances every input sample cycle. Therefore, in unbuf-
fered mode, source impedances mean a longer charge time for
CSAMP and this may result in gain errors on the part. Table XII
shows the allowable external resistance/capacitance values, for
unbuffered mode, such that no gain error to the 16-bit level is
introduced on the part. Table XIII shows the allowable external
resistance/capacitance values, once again for unbuffered mode,
such that no gain error to the 20-bit level is introduced.
Table XII.External R, C Combination for No 16-Bit Gain
Error (Unbuffered Mode Only)
Table XIII.External R, C Combination for No 20-Bit Gain
Error (Unbuffered Mode Only)In buffered mode, the analog inputs look into the high impedance
inputs stage of the on-chip buffer amplifier. CSAMP is charged via
this buffer amplifier such that source impedances do not affect
the charging of CSAMP. This buffer amplifier has an offset leak-
age current of 1␣nA. In this buffered mode, large source imped-
ances result in a dc offset voltage developed across the source
impedance but not in a gain error.
Input Sample RateThe modulator sample frequency for the AD7714 remains at
fCLK␣IN/128 (19.2␣kHz @ fCLK IN = 2.4576␣MHz) regardless of
the selected gain. However, gains greater than 1 are achieved
by a combination of multiple input samples per modulator cycle
and a scaling of the ratio of reference capacitor to input capaci-
tor. As a result of the multiple sampling, the input sample rate
of the device varies with the selected gain (see Table XIV). In
buffered mode, the input is buffered before the input sampling
capacitor. In unbuffered mode, where the analog input looks
directly into the sampling capacitor, the effective input imped-
ance is 1/CSAMP · fS where CSAMP is the input sampling capaci-
tance and fS is the input sample rate.
AIN(+)
AIN(–)Figure 3.Unbuffered Analog Input Structure
