AD7713AN ,LC2MOS Loop-Powered Signal Conditioning ADCapplications with an on-chip control register which allowscan be configured in software using the b ..
AD7713AR ,LC2MOS Loop-Powered Signal Conditioning ADCfeatures two differential analog inputs and one single-flexibility of the part, the high level anal ..
AD7714 ,CMOS, 3V/5V, 500 礎, 24-Bit Sigma-Delta, Signal Conditioning ADCSpecifications for AIN and REF IN Unless NotedInput Common-Mode Rejection (CMR) 90 dB min At DC. Ty ..
AD7714AN-3 ,3 V/5 V, CMOS, 500 uA Signal Conditioning ADCspecificationsSPI and QSPI are trademarks of Motorola, Inc.with 24-bit no missing codes, – 0.0015% ..
AD7714AN-5 ,3 V/5 V, CMOS, 500 uA Signal Conditioning ADCFEATURESFUNCTIONAL BLOCK DIAGRAMCharge Balancing ADCDVAV REF IN(–) REF IN(+)DD DD24 Bits No Missing ..
AD7714ANZ-5 , 3 V/5 V, CMOS, 500 mu A Signal Conditioning ADC
ADM1032ARM-REEL ,High Accuracy, Remote Thermal Diode Monitor in Micro SOIC PackageSPECIFICATIONSParameter Min Typ Max Unit Test Conditions/CommentsPOWER SUPPLYSupply Voltage, V 3.0 ..
ADM1032ARM-REEL7 ,High Accuracy, Remote Thermal Diode Monitor in Micro SOIC PackageFEATURES PRODUCT DESCRIPTIONOn-Chip and Remote Temperature Sensing The ADM1032 is a dual-channel di ..
ADM1032ARMZ ,High Accuracy, Remote Thermal Diode Monitor in Micro SOIC PackageSPECIFICATIONSParameter Min Typ Max Unit Test Conditions/CommentsPOWER SUPPLYSupply Voltage, V 3.0 ..
ADM1032ARMZ-1 , 1C Remote and Local System Temperature Monitor
ADM1032ARMZ-1RL , 1C Remote and Local System Temperature Monitor Supports SMBus Alert
ADM1032ARMZ-2RL7 , ±1℃ Remote and Local System Temperature Monitor
AD7713AN-AD7713AR
LC2MOS Loop-Powered Signal Conditioning ADC
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Charge Balancing ADC
24 Bits No Missing Codes60.0015% Nonlinearity
Three-Channel Programmable Gain Front End
Gains from 1 to 128
Two Differential Inputs
One Single Ended High Voltage Input
Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
Bidirectional Microcontroller Serial Interface
Single Supply Operation
Low Power (3.5 mW typ) with Power-Down Mode
(150 mW typ)
APPLICATIONS
Loop Powered (Smart) Transmitters
RTD Transducers
Process Control
Portable Industrial Instruments
Loop-Powered Signal Conditioning ADCREV.C
CMOS construction ensures low power dissipation and a hard-
ware programmable power-down mode reduces the standby
power consumption to only 150 μW typical. The part is avail-
able in a 24-pin, 0.3 inch wide, plastic and hermetic dual-in-line
package (DIP) as well as a 24-lead small outline (SOIC) package.
PRODUCT HIGHLIGHTSThe AD7713 consumes less than 1 mA in total supply cur-
rent, making it ideal for use in loop-powered systems.The two programmable gain channels allow the AD7713 to
accept input signals directly from a transducer removing a
considerable amount of signal conditioning. To maximize the
flexibility of the part, the high level analog input accepts
4 × VREF signals. On-chip current sources provide excitation
for three-wire and four-wire RTD configurations.No Missing Codes ensures true, usable, 24-bit dynamic
range coupled with excellent ±0.0015% accuracy. The effects
of temperature drift are eliminated by on-chip self-calibration,
which removes zero-scale and full-scale errors.The AD7713 is ideal for microcontroller or DSP processor
applications with an on-chip control register which allows
control over filter cutoff, input gain, signal polarity and cali-
bration modes. The AD7713 allows the user to read and
write the on-chip calibration registers.
GENERAL DESCRIPTIONThe AD7713 is a complete analog front end for low frequency
measurement applications. The device accepts low level signals
directly from a transducer or high level signals (4 × VREF) and
outputs a serial digital word. It employs a sigma-delta con-
version technique to realize up to 24 bits of no missing codes
performance. The input signal is applied to a proprietary pro-
grammable gain front end based around an analog modulator.
The modulator output is processed by an on-chip digital filter.
The first notch of this digital filter can be programmed via the
on-chip control register allowing adjustment of the filter cutoff
and settling time.
The part features two differential analog inputs and one single-
ended high level analog input as well as a differential reference
input. It can be operated from a single supply (AVDD and DVDD
at +5 V). The part provides two current sources which can be
used to provide excitation in three-wire and four-wire RTD con-
figurations. The AD7713 thus performs all signal conditioning
and conversion for a single, dual or three-channel system.
The AD7713 is ideal for use in smart, microcontroller-based
systems. Gain settings, signal polarity and RTD current control
can be configured in software using the bidirectional serial port.
The AD7713 contains self-calibration, system calibration and
background calibration options and also allows the user to read
and to write the on-chip calibration registers.
*. Patent No. 5,134,401.
NOTESTemperature range is as follows: A Version, –40°C to +85°C; S Version, –55°C to +125°C.Applies after calibration at the temperature of interest.Positive full-scale error applies to both unipolar and bipolar input ranges.These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 μV typical after self-calibration
or background calibration.Recalibration at any temperature or use of the background calibration mode will remove these drift errors.These numbers are guaranteed by design and/or characterization.The AIN1 and AIN2 analog inputs presents a very high impedance dynamic load which varies with clock frequency and input sample rate. The maximum
recommended source resistance depends on the selected gain.The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2 (–) inputs. The input
voltage range on the AIN3 input is with respect to AGND. The absolute voltage on the AIN1 and AIN2 inputs should not go more positive than AVDD + 30 mV or
more negative than AGND – 30 mV.VREF = REF IN(+) – REF IN(–).This common-mode voltage range is allowed provided that the input voltage on AIN(+) and AIN(–) does not exceed AVDD + 30 mV and AGND – 30 mV.This error can be removed using the system calibration capabilities of the AD7713. This error is not removed by the AD7713’s self-calibration feature. The offset
drift on the AIN3 input is four times the value given in the Static Performance section.
(AVDD = +5V 6 5%; DVDD = +5
V 6 5%; REF IN(+) = +2.5V; REF IN(–) = AGND;
MCLK IN = 2MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)AD7713–SPECIFICATIONS
NOTESGuaranteed by design, not production tested.After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.These calibration and span limits apply provided the absolute voltage on the AIN1 and AIN2 analog inputs does not exceed AVDD + 30 mV or go more negative
than AGND – 30 mV.The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
AD7713
NOTESThe ±5% tolerance on the DVDD input is allowed provided that DVDD does not exceed AVDD by more than 0.3 V.Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz
will exceed 120 dB with filter notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz or 60 Hz.PSRR depends on gain: gain of 1 = 70 dB typ; gain of 2 = 75 dB typ; gain of 4 = 80 dB typ; gains of 8 to 128 = 85 dB typ.
Specifications subject to change without notice.
AD7713–SPECIFICATIONS
TIMING CHARACTERISTICS1, 2
(DVDD = +5V ± 5%; AVDD = +5V or +10 V ± 5%; AGND = DGND = 0 V; fCLKIN =2MHz;
Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.)
NOTESGuaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.See Figures 10 to 13.CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7713 is not in STANDBY mode. If no clock is present in this case, the
device can draw higher current than specified and possibly become uncalibrated.The AD7713 is production tested with fCLK IN at 2 MHz. It is guaranteed by characterization to operate at 400kHz.Specified using 10% and 90% points on waveform of interest.These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are
the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
TO OUTPUT
PIN+2.1V
1.6mA
200µA
100pFFigure 1.Load Circuit for Access Time and Bus Relinquish Time
AD7713Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .105°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . .+260°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . .70°C/W
Lead Temperature, Soldering . . . . . . . . . . . . . . . . . . .+300°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
Power Dissipation (Any Package) to +75°C . . . . . . . . .450 mW
*Stresses above those listed under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C, unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +12 V
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AIN1, AIN2 Input Voltage
to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to AVDD + 0.3 V
AIN3 Input Voltage to AGND . . . . . . . . . . . .–0.3 V to +22 V
Reference Input Voltage to AGND . . – 0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . . – 0.3 V to AVDD + 0.3 V
Digital Output Voltage to DGND . . . – 0.3 V to DVDD + 0.3 V
Operating Temperature Range
Commercial (A Version) . . . . . . . . . . . . . . .–40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V, which readily
accumulate on the human body and on test equipment, can discharge without detection. Although
devices feature proprietary ESD protection circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic discharges. Therefore, proper precautions are
recommended to avoid any performance degradation or loss of functionality.
ORDERING GUIDE *N = Plastic DIP; Q = Cerdip; R = SOIC.
PIN CONFIGURATION
DIP AND SOIC
SCLK
DRDY
SDATA
DVDD
DGND
MCLK IN
MCLK OUT
AGND
TFS
RFSSYNC
MODE
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)REF IN(+)
RTD2
AIN3
STANDBY
AVDD
REF IN(–)
RTD1
PIN FUNCTION DESCRIPTION
AD7713
TERMINOLOGY
INTEGRAL NONLINEARITYThis is the maximum deviation of any code from a straight line
passingthroughtheendpointsofthetransferfunction. The end-
points of the transfer function are zero scale (not to be confused
withbipolarzero),apoint0.5LSBbelowthefirstcode transi-
tion (000...000 to 000...001) and full scale, a point 0.5LSB
abovethelastcodetransition(111...110to 111...111). The
error is expressed as a percentage of full scale.
POSITIVE FULL-SCALE ERRORPositive full-scale error is the deviation of the last code transi-
tion (111...110 to 111...111) from the ideal input full-scale
voltage. For AIN1(+) and AIN2(+), the ideal full-scale input
voltage is (AIN1(–) + VREF/GAIN – 3/2 LSBs) where AIN(–) is
either AIN1(–) or AIN2(–) as appropriate; for AIN3, the ideal
full-scale voltage is +4 × VREF/GAIN – 3/2 LSBs. Positive full-
scale error applies to both unipolar and bipolar analog input
ranges.
UNIPOLAR OFFSET ERRORUnipolar offset error is the deviation of the first code transition
from the ideal voltage. For AIN1(+) and AIN2(+), the ideal
input voltage is (AIN1(–) + 0.5 LSB); for AIN3, the ideal input
is 0.5 LSB when operating in the Unipolar Mode.
BIPOLAR ZERO ERRORThis is the deviation of the midscale transition (0111...111
to 1000...000) fromtheideal input voltage. For AIN1(+) and
AIN2(+), the ideal input voltage is (AIN1(–)– 0.5LSB); AIN3
can only accommodate unipolar input ranges.
BIPOLAR NEGATIVE FULL-SCALE ERRORThis is the deviation of the first code transition from the ideal
input voltage. For AIN1(+) and AIN2(+), the ideal input volt-
age is (AIN1(–) – VREF/GAIN + 0.5 LSB); AIN3 can only ac-
commodate unipolar input ranges.
POSITIVE FULL-SCALE OVERRANGEPositive full-scale overrange is the amount of overhead available
to handle input voltages on AIN1(+) and AIN2(+) inputs
greater than (AIN1(–) + VREF/GAIN) or on AIN3 of greater
than +4 × VREF/GAIN (for example, noise peaks or excess volt-
ages due to system gain errors in system calibration routines)
without introducing errors due to overloading the analog modu-
lator or to overflowing the digital filter.
NEGATIVE FULL-SCALE OVERRANGEThis is the amount of overhead available to handle voltages on
AIN1(+) and AIN2(+) below (AIN1(–) – VREF/GAIN) without
overloading the analog modulator or overflowing the digital filter.
OFFSET CALIBRATION RANGEIn the system calibration modes, the AD7713 calibrates its offset
with respect to the analog input. The offset calibration range
specification defines the range of voltages that the AD7713 can
accept and still calibrate offset accurately.
FULL-SCALE CALIBRATION RANGEThis is the range of voltages that the AD7713 can accept in the
system calibration mode and still calibrate full scale correctly.
INPUT SPANIn system calibration schemes, two voltages applied in sequence
to the AD7713’s analog input define the analog input range.
The input span specification defines the minimum and maxi-
mum input voltages from zero to full scale that the AD7713 can
accept and still calibrate gain accurately.
CONTROL REGISTER (24 BITS)A write to the device with the A0 input low writes data to the control register. A read to the device with the A0 input low accesses the
contents of the control register. The control register is 24 bits wide and when writing to the register 24 bits of data must be written
otherwise the data will not be loaded to the control register. In other words, it is not possible to write just the first 12 bits of data into
the control register. If more than 24 clock pulses are provided before TFS returns high, then all clock pulses after the 24th clock
pulse are ignored. Similarly, a read operation from the control register should access 24 bits of data.
MSB
LSB
Operating Mode
AD7713
PGA GainGlG0Gain001(Default Condition After the Internal Power-On Reset)12041801613206411128
Channel Selection
CH1CH0Channel0AIN1(Default Condition After the Internal Power-On Reset)1AIN20AIN3
Word LengthOutput Word Length16-Bit(Default Condition After Internal Power-On Reset)24-Bit
RTD Excitation CurrentsOff(Default Condition After Internal Power-On Reset)
1On
Burn-Out CurrentOff(Default Condition After Internal Power-On Reset)
1On
Bipolar/Unipolar Selection (Both Inputs)
B/U0 Bipolar(Default Condition After Internal Power-On Reset)
1 Unipolar
Filter Selection (FS11–FS0)The on-chip digital filter provides a Sinc3 (or (Sinx/x)3) filter response. The 12 bits of data programmed into these bits determine
the filter cutoff frequency, the position of the first notch of the filter and the data rate for the part. In association with the gain selec-
tion, it also determines the output noise (and hence the effective resolution) of the device.
The first notch of the filter occurs at a frequency determined by the relationship: filter first notch frequency = (fCLK IN/512)/code
where code is the decimal equivalent of the code in bits FS0 to FS11 and is in the range 19 to 2,000. With the nominal fCLK IN of
2 MHz, this results in a first notch frequency range from 1.952 Hz to 205.59 kHz. To ensure correct operation of the AD7713, the
value of the code loaded to these bits must be within this range. Failure to do this will result in unspecified operation of the device.
Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables I and II and Figure 2 show the effect of
the filter notch frequency and gain on the effective resolution of the AD7713. The output data rate (or effective conversion time) for
the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected at
10 Hz, then a new word is available at a 10 Hz rate or every 100 ms. If the first notch is at 200 Hz, a new word is available every 5 ms.
The settling time of the filter to a full-scale step input change is worst case 4 × 1/(output data rate). This settling time is to 100% of
the final value. For example, with the first filter notch at 100 Hz, the settling time of the filter to a full-scale step input change is
400 ms max. If the first notch is at 200 Hz, the settling time of the filter to a full-scale input step is 20 ms max. This settling time
can be reduced to 3 × l/(output data rate) by synchronizing the step input change to a reset of the digital filter. In other words, if the
step input takes place with SYNC low, the settling time will be 3 × l/(output data rate). If a change of channels takes place, the set-
tling time is 3 × l/(output data rate) regardless of the SYNC input.
The –3 dB frequency is determined by the programmed first notch frequency according to the relationship: filter –3 dB frequency
= 0.262 × first notch frequency.
Tables I and II show the output rms noise for some typical notch and –3 dB frequencies. The numbers given are for the bipolar in-
put ranges with a VREF of +2.5 V. These numbers are typical and are generated with an analog input voltage of 0 V. The output
noise from the part comes from two sources. First, there is the electrical noise in the semiconductor devices used in the implementa-
tion of the modulator (device noise). Secondly, when the analog input signal is converted into the digital domain, quantization noise
is added. The device noise is at a low level and is largely independent of frequency. The quantization noise starts at an even lower
level but rises rapidly with increasing frequency to become the dominant noise source. Consequently, lower filter notch settings
(below 12 Hz approximately) tend to be device noise dominated while higher notch settings are dominated by quantization noise.
Changing the filter notch and cutoff frequency in the quantization noise dominated region results in a more dramatic improvement
in noise performance than it does in the device noise dominated region as shown in Table I. Furthermore, quantization noise is
added after the PGA, so effective resolution is independent of gain for the higher filter notch frequencies. Meanwhile, device noise is
added in the PGA and, therefore, effective resolution suffers a little at high gains for lower notch frequencies.
At the lower filter notch settings (below 12 Hz), the no missing codes performance of the device is at the 24-bit level. At the higher
settings, more codes will be missed until at 200 Hz notch setting, no missing codes performance is only guaranteed to the 12-bit
level. However, since the effective resolution of the part is 10.5 bits for this filter notch setting, this no missing codes performance
should be more than adequate for all applications.
The effective resolution of the device is defined as the ratio of the output rms noise to the input full scale. This does not remain con-
stant with increasing gain or with increasing bandwidth. Table II shows the same table as Table I except that the output is now ex-
pressed in terms of effective resolution (the magnitude of the rms noise with respect to 2 × VREF/GAIN, i.e., the input full scale). It is
possible to do post filtering on the device to improve the output data rate for a given –3 dB frequency and also to further reduce the
output noise (see Digital Filtering section).
Table I.Output Noise vs. Gain and First Notch Frequency
Filter and O/PNOTES
1The default condition (after the internal power-on reset) for the first notch of filter is 60 Hz.
2For these filter notch frequencies, the output rms noise is primarily dominated by device noise and as a result is independent of the value of the reference voltage.
Therefore, increasing the reference voltage will give an increase in the effective resolution of the device (i.e., the ratio of the rms noise to the input full scale is
increased since the output rms noise remains constant as the input full scale increases).
3For these filter notch frequencies, the output rms noise is dominated by quantization noise and as a result is proportional to the value of the reference voltage.
Table II.Effective Resolution vs. Gain and First Notch FrequencyNOTEEffective resolution is defined as the magnitude of the output rms noise with respect to the input full scale (i.e., 2 × VREF/GAIN). The above table applies for
AD7713Figure 2 gives similar information to that outlined in Table I. In this plot, the output rms noise is shown for the full range of avail-
able cutoff frequencies rather than for some typical cutoff frequencies as in Tables I and II. The numbers given in these plots are
typical values at 25°C.
100010000100
NOTCH FREQUENCY — Hz
OUTPUT NOISE — µVFigure 2a.Plot of Output Noise vs. Gain and Notch
Frequency (Gains of 1 to 8)
CIRCUIT DESCRIPTIONThe AD7713 is a sigma-delta A/D converter with on-chip digi-
tal filtering, intended for the measurement of wide dynamic
range, low frequency signals such as those in industrial control
or process control applications. It contains a sigma-delta (or
charge balancing) ADC, a calibration microcontroller with on-
chip static RAM, a clock oscillator, a digital filter and a bidirec-
tional serial communications port.
The part contains three analog input channels, two program-
mable gain differential input and one programmable gain high-
level single-ended input. The gain range on both inputs is from
1 to 128. For the AIN1 and AIN2 inputs, this means that the
input can accept unipolar signals of between 0 mV to +20 mV
and 0 V to +2.5 V or bipolar signals in the range from ±20 mV
to ±2.5 V when the reference input voltage equals +2.5 V. The
input voltage range for the AIN3 input is +4 × VREF/GAIN and
is 0 V to + 10 V with the nominal reference of +2.5 V and a
gain of 1. The input signal to the selected analog input channel
is continuously sampled at a rate determined by the frequency
of the master clock, MCLK IN, and the selected gain (see
Table III). A charge balancing A/D converter (Sigma-Delta
Modulator) converts the sampled signal into a digital pulse train
whose duty cycle contains the digital information. The program-
mable gain function on the analog input is also incorporated in
this sigma-delta modulator with the input sampling frequency
being modified to give the higher gains. A sinc3 digital low-pass
filter processes the output of the sigma-delta modulator and up-
dates the output register at a rate determined by the first notch
frequency of this filter. The output data can be read from the
serial port randomly or periodically at any rate up to the output
register update rate. The first notch of this digital filter (and
hence its –3 dB frequency) can be programmed via an on-chip
control register. The programmable range for this first notch
frequency is from 1.952 Hz to 205.59 Hz, giving a programma-
ble range for the –3 dB frequency of 0.52 Hz to 53.9 Hz.
Figure 2b. Plot of Output Noise vs. Gain and Notch
Frequency (Gain of 16 to 128)
from the analog +5 V supply. Some applications will have sepa-
rate supplies for both AVDD and DVDD and in some of these
cases the analog supply will exceed the +5 V digital supply (see
Power Supplies and Grounding section).
Figure 3.Basic Connection Diagram
The AD7713 provides a number of calibration options which
can be programmed via the on-chip control register. A calibra-
tion cycle may be initiated at any time by writing to this control
register. The part can perform self-calibration using the on-chip
calibration microcontroller and SRAM to store calibration
parameters. Other system components may also be included in
the calibration loop to remove offset and gain errors in the input
channel using the system calibration mode. Another option is a
background calibration mode where the part continuously per-
forms self-calibration and updates the calibration coefficients.
The AD7713 gives the user access to the on-chip calibration
registers allowing the microprocessor to read the device’s cali-
bration coefficients and also to write its own calibration coeffi-
cients to the part from prestored values in E2PROM. This gives
the microprocessor much greater control over the AD7713’s
calibration procedure. It also means that the user can verify that
the device has performed its calibration correctly by comparing the
coefficients after calibration with prestored values in E2PROM.
For battery operation or low power systems, the AD7713 offers
a standby mode (controlled by the STANDBY pin) that reduces
idle power consumption to typically 150 μW.
THEORY OF OPERATIONThe general block diagram of a sigma-delta ADC is shown in
Figure 4. It contains the following elements:A sample-hold amplifier.A differential amplifier or subtracter.An analog low-pass filter.A 1-bit A/D converter (comparator).A 1-bit DAC.A digital low-pass filter.
S/H AMP
COMPARATOR
DIGITAL DATAFigure 4.General Sigma-Delta ADC
In operation, the analog signal sample is fed to the subtracter,
along with the output of the 1-bit DAC. The filtered difference
signal is fed to the comparator, whose output samples the differ-
ence signal at a frequency many times that of the analog signal
sampling frequency (oversampling).
Oversampling is fundamental to the operation of sigma-delta
ADCs. Using the quantization noise formula for an ADC:
SNR = (6.02 × number of bits + 1.76) dB,
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
The AD7713 samples the input signal at a frequency of 7.8 kHz or
greater (see Table III). As a result, the quantization noise is
spread over a much wider frequency than that of the band of
interest. The noise in the band of interest is reduced still further
by analog filtering in the modulator loop, which shapes the
quantization noise spectrum to move most of the noise energy to
frequencies outside the bandwidth of interest. The noise perfor-
mance is thus improved from this 1-bit level to the performance
outlined in Tables I and II and in Figure 2.
The output of the comparator provides the digital input for the
1-bit DAC, so that the system functions as a negative feedback
loop that tries to minimize the difference signal. The digital data
that represents the analog input voltage is contained in the duty
cycle of the pulse train appearing at the output of the compara-
tor. It can be retrieved as a parallel binary data word using a
Sigma-delta ADCs are generally described by the order of the
analog low-pass filter. A simple example of a first order sigma-
delta ADC is shown in Figure 5. This contains only a first order
low-pass filter or integrator. It also illustrates the derivation of
the alternative name for these devices: Charge Balancing ADCs
WIN
DIFFERENTIAL
AMPLIFIERINTEGRATORFigure 5.Basic Charge-Balancing ADC
It consists of a differential amplifier (whose output is the differ-
ence between the analog input and the output of a 1-bit DAC),
an integrator and a comparator. The term charge balancing,
comes from the fact that this system is a negative feedback loop
that tries to keep the net charge on the integrator capacitor at
zero by balancing charge injected by the input voltage with
charge injected by the 1-bit DAC. When the analog input is
zero, the only contribution to the integrator output comes from
the 1-bit DAC. For the net charge on the integrator capacitor to
be zero, the DAC output must spend half its time at +FS and
half its time at –FS. Assuming ideal components, the duty cycle
of the comparator will be 50%.
When a positive analog input is applied, the output of the 1-bit
DAC must spend a larger proportion of the time at +FS, so the
duty cycle of the comparator increases. When a negative input
voltage is applied, the duty cycle decreases.
The AD7713 uses a second-order sigma-delta modulator and a
digital filter that provides a rolling average of the sampled out-
put. After power-up or if there is a step change in the input
voltage, there is a settling time that must elapse before valid
data is obtained.
Input Sample RateThe modulator sample frequency for the device remains at
fCLK IN/512 (3.9 kHz @ fCLK IN = 2 MHz) regardless of the
selected gain. However, gains greater than ×1 are achieved by a
combination of multiple input samples per modulator cycle and
a scaling of the ratio of reference capacitor to input capacitor.
As a result of the multiple sampling, the input sample rate of
the device varies with the selected gain (see Table III). The ef-
fective input impedance is 1/C × fS where C is the input sam-
pling capacitance and fS is the input sample rate.
Table III.Input Sampling Frequency vs. Gain
AD7713
DIGITAL FILTERINGThe AD7713’s digital filter behaves like a similar analog filter,
with a few minor differences.
First, since digital filtering occurs after the A-to-D conversion
process, it can remove noise injected during the conversion pro-
cess. Analog filtering cannot do this.
On the other hand, analog filtering can remove noise superim-
posed on the analog signal before it reaches the ADC. Digital
filtering cannot do this, and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
and digital filter, even though the average value of the signal is
within limits. To alleviate this problem, the AD7713 has over-
range headroom built into the sigma-delta modulator and digi-
tal filter which allows overrange excursions of 5% above the
analog input range. If noise signals are larger than this, consid-
eration should be given to analog input filtering, or to reducing
the input channel voltage so that its full scale is half that of the
analog input channel full scale. This will provide an overrange
capability greater than 100% at the expense of reducing the dy-
namic range by 1 bit (50%).
Filter CharacteristicsThe cutoff frequency of the digital filter is determined by the
value loaded to bits FS0 to FS11 in the control register. At the
maximum clock frequency of 2 MHz, the minimum cutoff fre-
quency of the filter is 0.52 Hz while the maximum program-
mable cutoff frequency is 53.9 Hz.
Figure 6 shows the filter frequency response for a cutoff fre-
quency of 0.52 Hz which corresponds to a first filter notch fre-
quency of 2 Hz. This is a (sinx/x)3 response (also called sinc3)
FREQUENCY – Hz
GAIN – dBs
–10010Figure 6. Frequency Response of AD7713 Filter
that provides >100 dB of 50 Hz and 60 Hz rejection. Program-
ming a different cutoff frequency via FS0–FS11 does not alter
the profile of the filter response; it changes the frequency of the
notches as outlined in the Control Register section.
Since the AD7713 contains this on-chip, low-pass filtering,
there is a settling time associated with step function inputs, and
data on the output will be invalid after a step change until the
settling time has elapsed. The settling time depends upon the
notch frequency chosen for the filter. The output data rate
Post FilteringThe on-chip modulator provides samples at a 3.9kHz output
rate. The on-chip digital filter decimates these samples to pro-
vide data at an output rate which corresponds to the pro-
grammed first notch frequency of the filter. Since the output
data rate exceeds the Nyquist criterion, the output rate for a
given bandwidth will satisfy most application requirements.
However, there may be some applications which require a
higher data rate for a given bandwidth and noise performance.
Applications that need this higher data rate will require some
post filtering following the digital filter of the AD7713.
For example, if the required bandwidth is 1.57 Hz but the re-
quired update rate is 20 Hz, the data can be taken from the
AD7713 at the 20 Hz rate giving a –3 dB bandwidth of
5.24 Hz. Post filtering can be applied to this to reduce the band-
width and output noise, to the 1.57 Hz bandwidth level, while
maintaining an output rate of 20 Hz.
Post filtering can also be used to reduce the output noise from
the device for bandwidths below 0.52 Hz. At a gain of 128, the
output rms noise is 250 nV. This is essentially device noise or
white noise, and since the input is chopped, the noise has a flat
frequency response. By reducing the bandwidth below 0.52 Hz,
the noise in the resultant passband can be reduced. A reduction
in bandwidth by a factor of two results in a √2 reduction in the
output rms noise. This additional filtering will result in a longer
settling time.
Antialias ConsiderationsThe digital filter does not provide any rejection at integer mul-
tiples of the modulator sample frequency (n × 3.9 kHz, where
n = 1, 2, 3 . . . ). This means that there are frequency bands,
±f3 dB wide (f3 dB is cutoff frequency selected by FS0 to FS11)
where noise passes unattenuated to the output. However, due to
the AD7713’s high oversampling ratio, these bands occupy only
a small fraction of the spectrum and most broadband noise is
filtered. In any case, because of the high oversampling ratio a
simple, RC, single pole filter is generally sufficient to attenuate
the signals in these bands on the analog input and thus provide
adequate antialiasing filtering.
If passive components are placed in front of the AIN1 and AIN2
inputs of the AD7713, care must be taken to ensure that the
source impedance is low enough so as not to introduce gain er-
rors in the system. The dc input impedance for the AIN1 and
AIN2 inputs is over 1 GΩ. The input appears as a dynamic load
that varies with the clock frequency and with the selected gain
(see Figure 7). The input sample rate, as shown in Table III,
determines the time allowed for the analog input capacitor, CIN,
to be charged. External impedances result in a longer charge
time for this capacitor, and this may result in gain errors being
