AD7712AR ,LC2MOS Signal Conditioning ADCapplications with an on-chip control register that allowsinput signals on the low level analog inpu ..
AD7712AR ,LC2MOS Signal Conditioning ADCGENERAL DESCRIPTIONport. The AD7712 also contains self-calibration, system calibra-The AD7712 is a ..
AD7713AN ,LC2MOS Loop-Powered Signal Conditioning ADCapplications with an on-chip control register which allowscan be configured in software using the b ..
AD7713AR ,LC2MOS Loop-Powered Signal Conditioning ADCfeatures two differential analog inputs and one single-flexibility of the part, the high level anal ..
AD7714 ,CMOS, 3V/5V, 500 礎, 24-Bit Sigma-Delta, Signal Conditioning ADCSpecifications for AIN and REF IN Unless NotedInput Common-Mode Rejection (CMR) 90 dB min At DC. Ty ..
AD7714AN-3 ,3 V/5 V, CMOS, 500 uA Signal Conditioning ADCspecificationsSPI and QSPI are trademarks of Motorola, Inc.with 24-bit no missing codes, – 0.0015% ..
ADM1032ARM-REEL ,High Accuracy, Remote Thermal Diode Monitor in Micro SOIC PackageSPECIFICATIONSParameter Min Typ Max Unit Test Conditions/CommentsPOWER SUPPLYSupply Voltage, V 3.0 ..
ADM1032ARM-REEL7 ,High Accuracy, Remote Thermal Diode Monitor in Micro SOIC PackageFEATURES PRODUCT DESCRIPTIONOn-Chip and Remote Temperature Sensing The ADM1032 is a dual-channel di ..
ADM1032ARMZ ,High Accuracy, Remote Thermal Diode Monitor in Micro SOIC PackageSPECIFICATIONSParameter Min Typ Max Unit Test Conditions/CommentsPOWER SUPPLYSupply Voltage, V 3.0 ..
ADM1032ARMZ-1 , 1C Remote and Local System Temperature Monitor
ADM1032ARMZ-1RL , 1C Remote and Local System Temperature Monitor Supports SMBus Alert
ADM1032ARMZ-2RL7 , ±1℃ Remote and Local System Temperature Monitor
AD7712AN-AD7712AQ-AD7712AR
LC2MOS Signal Conditioning ADC
FUNCTIONAL BLOCK DIAGRAM
AGNDDGNDMODESDATASCLKA0
MCLK
OUT
MCLK
AIN1(–)
REF
IN (–)
REF
IN (+)
SYNC
DRDYTFSRFS
REF OUTVBIASAIN2
STANDBY
VSS
DVDDAVDD
AIN1(+)
FEATURES
Charge Balancing ADC
24 Bits No Missing Codes60.0015% Nonlinearity
High Level and Low Level Analog Input Channels
Programmable Gain for Both Inputs
Gains from 1 to 128
Differential Input for Low Level Channel
Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
Bidirectional Microcontroller Serial Interface
Internal/External Reference Option
Single or Dual Supply Operation
Low Power (25 mW typ) with Power-Down Mode
(100 mW typ)
APPLICATIONS
Process Control
Smart Transmitters
Portable Industrial Instruments
Signal Conditioning ADCREV.E
GENERAL DESCRIPTIONThe AD7712 is a complete analog front end for low frequency
measurement applications. The device has two analog input
channels and accepts either low level signals directly from a
transducer or high level (–4 · VREF) signals and outputs a serial
digital word. It employs a sigma-delta conversion technique to
realize up to 24 bits of no missing codes performance. The low
level input signal is applied to a proprietary programmable gain
front end based around an analog modulator. The high level
analog input is attenuated before being applied to the same
modulator. The modulator output is processed by an on-chip
digital filter. The first notch of this digital filter can be pro-
grammed via the on-chip control register allowing adjustment of
the filter cutoff and settling time.
Normally, one of the channels will be used as the main channel
with the second channel used as an auxiliary input to periodi-
cally measure a second voltage. The part can be operated from a
single supply (by tying the VSS pin to AGND) provided that the
input signals on the low level analog input are more positive
than –30 mV. By taking the VSS pin negative, the part can con-
vert signals down to –VREF on this low level input. This low level
input, as well as the reference input, features differential input
capability.
The AD7712 is ideal for use in smart, microcontroller-based
systems. Input channel selection, gain settings and signal polar-
ity can be configured in software using the bidirectional serial
port. The AD7712 also contains self-calibration, system calibra-
tion and background calibration options and also allows the user
to read and to write the on-chip calibration registers.
CMOS construction ensures low power dissipation and a hard-
ware programmable power-down mode reduces the standby
power consumption to only 100 mW typical. The part is avail-
able in a 24-lead, 0.3 inch wide, plastic and hermetic dual-in-
line package (DIP) as well as a 24-lead small outline (SOIC)
package.
PRODUCT HIGHLIGHTSThe low level analog input channel allows the AD7712 to
accept input signals directly from a strain gage or transducer,
removing a considerable amount of signal conditioning. To
maximize the flexibility of the part, the high level analog
input accepts signals of –4 · VREF/GAIN.The AD7712 is ideal for microcontroller or DSP processor
applications with an on-chip control register that allows
control over filter cutoff, input gain, channel selection, signal
polarity and calibration modes.The AD7712 allows the user to read and to write the on-chip
calibration registers. This means that the microcontroller has
much greater control over the calibration procedure.No Missing Codes ensures true, usable, 23-bit dynamic
range coupled with excellent –0.0015% accuracy. The effects
of temperature drift are eliminated by on-chip self-calibration,
which removes zero-scale and full-scale errors.
*. Patent No. 5,134,401.
NOTESTemperature range is as follows: A Version, –40°C to +85°C; S Version –55°C to +125°C. See also Note 18.Applies after calibration at the temperature of interest.Positive full-scale error applies to both unipolar and bipolar input ranges.These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 mV typical after self-calibration
or background calibration.Recalibration at any temperature or use of the background calibration mode will remove these drift errors.These numbers are guaranteed by design and/or characterization.This common-mode voltage range is allowed provided that the input voltage on AIN1(+) and AIN1(–) does not exceed AVDD + 30 mV and VSS – 30 mV.The AIN1 analog input presents a very high impedance dynamic load which varies with clock frequency and input sample rate. The maximum recommended
source resistance depends on the selected gain (see Tables IV and V).The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1(–) input. The input voltage range on the AIN2
input is with respect to AGND. The absolute voltage on the AIN1 input should not go more positive than AVDD + 30 mV or more negative than VSS – 30 mV.VREF = REF IN(+) – REF IN(–).This error can be removed using the system calibration capabilities of the AD7712. This error is not removed by the AD7712’s self-calibration features. The offset
(AVDD = +5␣V 6 5%; DVDD = +5␣V 6 5%; VSS = 0␣V or –5V 6 5%; REF IN(+) = +2.5␣V;
REF IN(–) = AGND; MCLK IN = 10␣MHz unless otherwise stated. All specifications TMIN to TMAX unless otherwise noted.)AD7712–SPECIFICATIONS
REFERENCE OUTPUT
VBIAS INPUT
LOGIC OUTPUTS
NOTES
13The AD7712 is tested with the following VBIAS voltages. With AVDD = +5 V and VSS = 0 V, VBIAS = +2.5 V; with AVDD = +10 V and VSS = 0 V, VBIAS = +5 V and
with AVDD = +5 V and VSS = –5 V, VBIAS = 0 V.
14Guaranteed by design, not production tested.
15After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.
16These calibration and span limits apply provided the absolute voltage on the AIN1 analog inputs does not exceed AVDD + 30 mV or does not go more negative
than VSS – 30 mV.
17The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
AD7712
POWER REQUIREMENTS
NOTESThe AD7712 is specified with a 10 MHz clock for AVDD voltages of +5 V – 5%. It is specified with an 8 MHz clock for AVDD voltages greater than 5.25 V and less
than 10.5V.The –5% tolerance on the DVDD input is allowed provided that DVDD does not exceed AVDD by more than 0.3 V.Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will
exceed 120 dB with filter notches of 10 Hz, 30 Hz or 60 Hz.PSRR depends on gain: gain of 1 = 70 dB typ; gain of 2 = 75 dB typ; gain of 4 = 80 dB typ; gains of 8 to 128 = 85 dB typ. These numbers can be improved
(to 95 dB typ) by deriving the VBIAS voltage (via Zener diode or reference) from the AVDD supply.Using the hardware STANDBY pin. Standby power dissipation using the software standby bit (PD) of the Control Register is 8 mW typ.
Specifications subject to change without notice.
AD7712–SPECIFICATIONS
CAUTIONESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
REF OUT to AGND . . . . . . . . . . . . . . . . . . . .–0.3 V to AVDD
Digital Input Voltage to DGND . . . . .–0.3 V to AVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Operating Temperature Range
Commercial (A Version) . . . . . . . . . . . . . . .–40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . . . .450 mW
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C, unless otherwise noted)
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V
AVDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +12 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AIN1 Input Voltage to AGND . . VSS – 0.3 V to AVDD + 0.3 V
Reference Input Voltage to AGND
. . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to AVDD + 0.3 V
ORDERING GUIDE*N = Plastic DIP, Q = Cerdip; R = SOIC.
TIMING CHARACTERISTICS1, 2
(DVDD = +5␣V 6 5%; AVDD = +5␣V or +10 V3 6 5%; VSS = 0 V or –5 V 6 5%; AGND = DGND =
0 V; fCLKIN =10␣MHz; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.)
AD7712NOTESGuaranteed by design, not production tested. Sample tested during initial release and after any redesign or process change that may affect this parameter. All input
signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.See Figures 11 to 14.The AD7712 is specified with a 10 MHz clock for AVDD voltages of +5 V – 5%. It is specified with an 8 MHz clock for AVDD voltages greater than 5.25V and less
than 10.5V.CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7712 is not in STANDBY mode. If no clock is present in this case, the
device can draw higher current than specified and possibly become uncalibrated.The AD7712 is production tested with fCLK IN at 10 MHz (8 MHz for AVDD < +5.25 V). It is guaranteed by characterization to operate at 400kHz.Specified using 10% and 90% points on waveform of interest.These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are
the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
Specifications subject to change without notice.
TO OUTPUT
PIN+2.1V
100pFFigure 1.Load Circuit for Access Time and Bus Relinquish
Time
PIN CONFIGURATION
DIP AND SOIC
PIN FUNCTION DESCRIPTIONAD7712 22
23
TERMINOLOGY
INTEGRAL NONLINEARITYThis is the maximum deviation of any code from a straight line
passingthroughtheendpointsofthetransferfunction. The end-
points of the transfer function are zero-scale (not to be confused
withbipolarzero),apoint0.5LSBbelowthefirstcode transi-
tion (000...000 to 000...001) and full scale, a point 0.5LSB
abovethelastcodetransition(111...110to 111...111). The
error is expressed as a percentage of full scale.
POSITIVE FULL-SCALE ERRORPositive full-scale error is the deviation of the last code transi-
tion (111...110 to 111...111) from the ideal input full-scale
voltage. For AIN1(+), the ideal full-scale input voltage is
(AIN1(–) + VREF/GAIN – 3/2 LSBs); for AIN2, the ideal full-
scale voltage is +4 · VREF/GAIN – 3/2 LSBs. Positive full-scale
error applies to both unipolar and bipolar analog input ranges.
UNIPOLAR OFFSET ERRORUnipolar offset error is the deviation of the first code transition
from the ideal voltage. For AIN1(+), the ideal input voltage is
(AIN1(–) + 0.5 LSB); for AIN2, the ideal input is 0.5 LSB
when operating in the unipolar mode.
BIPOLAR ZERO ERRORThis is the deviation of the midscale transition (0111...111
to 1000...000) fromtheideal input voltage. For AIN1(+), the
ideal input voltage is (AIN1(–)– 0.5LSB); for AIN2, the ideal
input is –0.5 LSB when operating in the bipolar mode.
BIPOLAR NEGATIVE FULL-SCALE ERRORThis is the deviation of the first code transition from the ideal
input voltage. For AIN1(+), the ideal input voltage is (AIN1(–)
– VREF/GAIN + 0.5 LSB); for AIN2, the ideal input voltage is
(–4 · VREF/GAIN + 0.5 LSB) when operating in the bipolar
mode.
POSITIVE FULL-SCALE OVERRANGEPositive full-scale overrange is the amount of overhead available
to handle input voltages on AIN1(+) input greater than
(AIN1(–) + VREF/GAIN) or on the AIN2 of greater than +4 ·
VREF/GAIN (for example, noise peaks or excess voltages due to
system gain errors in system calibration routines) without intro-
ducing errors due to overloading the analog modulator or to
overflowing the digital filter.
NEGATIVE FULL-SCALE OVERRANGEThis is the amount of overhead available to handle voltages on
AIN1(+) below (AIN1(–) – VREF/GAIN) or on AIN2 below
–4 · VREF/GAIN without overloading the analog modulator or
overflowing the digital filter. Note that the analog input will
accept negative voltage peaks on AIN1(+) even in the unipolar
mode provided that AIN1(+) is greater than AIN1(–) and
greater than VSS – 30␣mV.
OFFSET CALIBRATION RANGEIn the system calibration modes, the AD7712 calibrates its offset
with respect to the analog input. The offset calibration range
specification defines the range of voltages that the AD7712 can
accept and still accurately calibrate offset.
FULL-SCALE CALIBRATION RANGEThis is the range of voltages that the AD7712 can accept in the
system calibration mode and still correctly calibrate full-scale.
INPUT SPANIn system calibration schemes, two voltages applied in sequence
to the AD7712’s analog input define the analog input range.
The input span specification defines the minimum and maxi-
mum input voltages from zero to full-scale that the AD7712
can accept and still accurately calibrate gain.
CONTROL REGISTER (24 BITS)A write to the device with the A0 input low writes data to the control register. A read to the device with the A0 input low accesses the
contents of the control register. The control register is 24-bits wide and when writing to the register 24 bits of data must be written
otherwise the data will not be loaded to the control register. In other words, it is not possible to write just the first 12-bits of data into
the control register. If more than 24 clock pulses are provided before TFS returns high, then all clock pulses after the 24th clock
pulse are ignored. Similarly, a read operation from the control register should access 24 bits of data.
MSB
LSBX = Don’t Care.
AD7712
PGA GainGlG0Gain001(Default Condition After the Internal Power-On Reset)12041801613206411128
Channel SelectionChannelAIN1Low Level Input(Default Condition After the Internal Power-On Reset)AIN2High Level Input
Power-DownNormal Operation(Default Condition After the Internal Power-On Reset)Power-Down
Word LengthOutput Word Length16-Bit(Default Condition After Internal Power-On Reset)24-Bit
Burnout CurrentOff(Default Condition After Internal Power-On Reset)
1On
Bipolar/Unipolar Selection (Both Inputs)
B/U0 Bipolar(Default Condition After Internal Power-On Reset)
1 Unipolar
Filter Selection (FS11–FS0)The on-chip digital filter provides a Sinc3 (or (Sinx/x)3) filter response. The 12 bits of data programmed into these bits determine
the filter cutoff frequency, the position of the first notch of the filter and the data rate for the part. In association with the gain selec-
tion, it also determines the output noise (and hence the effective resolution) of the device.
The first notch of the filter occurs at a frequency determined by the relationship: filter first notch frequency = (fCLK IN/512)/code
where code is the decimal equivalent of the code in bits FS0 to FS11 and is in the range 19 to 2,000. With the nominal fCLK IN of
10 MHz, this results in a first notch frequency range from 9.76 Hz to 1.028 kHz. To ensure correct operation of the AD7712, the
value of the code loaded to these bits must be within this range. Failure to do this will result in unspecified operation of the device.
Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables I and II and Figure 2 show the effect of
the filter notch frequency and gain on the effective resolution of the AD7712. The output data rate (or effective conversion time) for
the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected at
50 Hz, then a new word is available at a 50 Hz rate or every 20 ms. If the first notch is at 1 kHz, a new word is available every 1 ms.
The settling time of the filter to a full-scale step input change is worst case 4 · 1/(output data rate). This settling time is to 100% of
the final value. For example, with the first filter notch at 50 Hz, the settling time of the filter to a full-scale step input change is
80 ms max. If the first notch is at 1 kHz, the settling time of the filter to a full-scale input step is 4 ms max. This settling time can be
reduced to 3 · l/(output data rate) by synchronizing the step input change to a reset of the digital filter. In other words, if the step
input takes place with SYNC low, the settling time will be 3 · l/(output data rate). If a change of channels takes place, the settling
time is 3 · l/(output data rate) regardless of the SYNC input.
The –3 dB frequency is determined by the programmed first notch frequency according to the relationship: filter –3 dB frequency
= 0.262 · first notch frequency.
Tables I and II show the output rms noise for some typical notch and –3 dB frequencies. The numbers given are for the bipolar
input ranges with a VREF of +2.5 V. These numbers are typical and are generated with an analog input voltage of 0 V. The output
noise from the part comes from two sources. First, there is the electrical noise in the semiconductor devices used in the implementa-
tion of the modulator (device noise). Secondly, when the analog input signal is converted into the digital domain, quantization noise
is added. The device noise is at a low level and is largely independent of frequency. The quantization noise starts at an even lower
level but rises rapidly with increasing frequency to become the dominant noise source. Consequently, lower filter notch settings
(below 60 Hz approximately) tend to be device noise dominated while higher notch settings are dominated by quantization noise.
Changing the filter notch and cutoff frequency in the quantization noise dominated region results in a more dramatic improvement
in noise performance than it does in the device noise dominated region as shown in Table I. Furthermore, quantization noise is
added after the PGA, so effective resolution is independent of gain for the higher filter notch frequencies. Meanwhile, device noise is
added in the PGA and, therefore, effective resolution suffers a little at high gains for lower notch frequencies.
At the lower filter notch settings (below 60 Hz), the no missing codes performance of the device is at the 24-bit level. At the higher
settings, more codes will be missed until at 1 kHz notch setting, no missing codes performance is only guaranteed to the 12-bit level.
However, since the effective resolution of the part is 10.5 bits for this filter notch setting, this no missing codes performance should
be more than adequate for all applications.
The effective resolution of the device is defined as the ratio of the output rms noise to the input full scale. This does not remain
constant with increasing gain or with increasing bandwidth. Table II shows the same table as Table I except that the output is now
expressed in terms of effective resolution (the magnitude of the rms noise with respect to 2 · VREF/GAIN, i.e., the input full scale). It
is possible to do post filtering on the device to improve the output data rate for a given –3 dB frequency and also to further reduce
the output noise (see Digital Filtering section).
Table I.Output Noise vs. Gain and First Notch Frequency10␣
NOTESThe default condition (after the internal power-on reset) for the first notch of filter is 60 Hz.For these filter notch frequencies, the output rms noise is primarily dominated by device noise and as a result is independent of the value of the reference voltage.
Therefore, increasing the reference voltage will give an increase in the effective resolution of the device (i.e., the ratio of the rms noise to the input full scale is
increased since the output rms noise remains constant as the input full scale increases).For these filter notch frequencies, the output rms noise is dominated by quantization noise and as a result is proportional to the value of the reference voltage.
Table II.Effective Resolution vs. Gain and First Notch Frequency
Filter and O/PNOTE
1Effective resolution is defined as the magnitude of the output rms noise with respect to the input full scale (i.e., 2 · VREF/GAIN). The above table applies for
a VREF of +2.5 V and resolution numbers are rounded to the nearest 0.5 LSB.
AD7712
CIRCUIT DESCRIPTIONThe AD7712 is a sigma-delta A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low frequency signals such as those in industrial control or pro-
cess control applications. It contains a sigma-delta (or charge
balancing) ADC, a calibration microcontroller with on-chip
static RAM, a clock oscillator, a digital filter and a bidirectional
serial communications port.
The part contains two analog input channels, one programmable
gain differential input and one programmable gain high level
single-ended input. The gain range on both inputs is from 1 to
128. For the AIN1 input, this means that the input can accept
unipolar signals of between 0 mV to +20 mV and 0 mV to
+2.5 V or bipolar signals in the range from –20 mV to –2.5 V
when the reference input voltage equals +2.5 V. The input volt-
age range for the AIN2 input is –4 · VREF/GAIN and is –10 V with
the nominal reference of +2.5 V and a gain of 1. The input
signal to the selected analog input channel is continuously
sampled at a rate determined by the frequency of the master
clock, MCLK IN, and the selected gain (see Table III). A
charge balancing A/D converter (Sigma-Delta Modulator) con-
verts the sampled signal into a digital pulse train whose duty
cycle contains the digital information. The programmable gain
function on the analog input is also incorporated in this sigma-
delta modulator with the input sampling frequency being modi-
fied to give the higher gains. A sinc3 digital low-pass filter
processes the output of the sigma-delta modulator and updates
the output register at a rate determined by the first notch fre-
quency of this filter. The output data can be read from the serial
port randomly or periodically at any rate up to the output regis-
ter update rate. The first notch of this digital filter (and hence its
–3 dB frequency) can be programmed via an on-chip control
register. The programmable range for this first notch frequency
is from 9.76 Hz to 1.028 kHz, giving a programmable range for
The basic connection diagram for the part is shown in Figure 3.
This shows the AD7712 in the external clocking mode with both
the AVDD and DVDD pins of the AD7712 being driven from the
analog +5 V supply. Some applications will have separate sup-
plies for both AVDD and DVDD, and in some of these cases, the
analog supply will exceed the +5 V digital supply (see Power
Supplies and Grounding section).
Figure 3.Basic Connection Diagram
Figure 2b.Plot of Output Noise vs. Gain and Notch
Frequency (Gains of 16 to 128)
NOTCH FREQUENCY – Hz
OUTPUT NOISE – Figure 2a.Plot of Output Noise vs. Gain and Notch
Frequency (Gains of 1 to 8)
Figures 2a and 2b give information similar to that outlined in Table I. In these plots, the output rms noise is shown for the full range
of available cutoffs frequencies rather than for some typical cutoff frequencies as in Tables I and II. The numbers given in these plots
are typical values at +25°C.
Oversampling is fundamental to the operation of sigma-delta
ADCs. Using the quantization noise formula for an ADC:
SNR = (6.02 · number of bits + 1.76) dB,
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
The AD7712 samples the input signal at a frequency of 39 kHz or
greater (see Table III). As a result, the quantization noise is
spread over a much wider frequency than that of the band of
interest. The noise in the band of interest is reduced still further
by analog filtering in the modulator loop, which shapes the
quantization noise spectrum to move most of the noise energy to
frequencies outside the bandwidth of interest. The noise perfor-
mance is thus improved from this 1-bit level to the performance
outlined in Tables I and II and in Figure 2.
The output of the comparator provides the digital input for the
1-bit DAC, so that the system functions as a negative feedback
loop that tries to minimize the difference signal. The digital data
that represents the analog input voltage is contained in the duty
cycle of the pulse train appearing at the output of the compara-
tor. It can be retrieved as a parallel binary data word using a
digital filter.
Sigma-delta ADCs are generally described by the order of the
analog low-pass filter. A simple example of a first order sigma-
delta ADC is shown in Figure 5. This contains only a first order
low-pass filter or integrator. It also illustrates the derivation of
the alternative name for these devices: Charge Balancing ADCs.
Figure 5.Basic Charge-Balancing ADC
It consists of a differential amplifier (whose output is the differ-
ence between the analog input and the output of a 1-bit DAC),
an integrator and a comparator. The term charge balancing,
comes from the fact that this system is a negative feedback loop
that tries to keep the net charge on the integrator capacitor at
zero by balancing charge injected by the input voltage with
charge injected by the 1-bit DAC. When the analog input is
zero, the only contribution to the integrator output comes from
the 1-bit DAC. For the net charge on the integrator capacitor to
be zero, the DAC output must spend half its time at +FS and
half its time at –FS. Assuming ideal components, the duty cycle
of the comparator will be 50%.
When a positive analog input is applied, the output of the 1-bit
DAC must spend a larger proportion of the time at +FS, so the
duty cycle of the comparator increases. When a negative input
voltage is applied, the duty cycle decreases.
The AD7712 uses a second-order sigma-delta modulator and a
digital filter that provides a rolling average of the sampled out-
put. After power-up, or if there is a step change in the input
The AD7712 provides a number of calibration options which
can be programmed via the on-chip control register. A calibra-
tion cycle may be initiated at any time by writing to this control
register. The part can perform self-calibration using the on-chip
calibration microcontroller and SRAM to store calibration
parameters. Other system components may also be included in
the calibration loop to remove offset and gain errors in the input
channel using the system calibration mode. Another option is a
background calibration mode where the part continuously per-
forms self-calibration and updates the calibration coefficients.
Once the part is in this mode, the user does not have to worry
about issuing periodic calibration commands to the device or
asking the device to recalibrate when there is a change in the
ambient temperature or power supply voltage.
The AD7712 gives the user access to the on-chip calibration
registers allowing the microprocessor to read the device’s cali-
bration coefficients and also to write its own calibration coeffi-
cients to the part from prestored values in E2PROM. This gives
the microprocessor much greater control over the AD7712’s
calibration procedure. It also means that the user can verify that
the device has performed its calibration correctly by comparing the
coefficients after calibration with prestored values in E2PROM.
The AD7712 can be operated in single supply systems provided
that the analog input voltage on the AIN1 input does not go
more negative than –30 mV. For larger bipolar signals on the
AIN1 input, a VSS of –5 V is required by the part. For battery
operation or low power systems, the AD7712 offers a standby
mode (controlled by the STANDBY pin) that reduces idle
power consumption to typically 100 mW.
THEORY OF OPERATIONThe general block diagram of a sigma-delta ADC is shown in
Figure 4. It contains the following elements:A sample-hold amplifier.A differential amplifier or subtracter.An analog low-pass filter.A 1-bit A/D converter (comparator).A 1-bit DAC.A digital low-pass filter.
DIGITAL DATA
S/H AMPFigure 4.General Sigma-Delta ADC
In operation, the analog signal sample is fed to the subtracter,
along with the output of the 1-bit DAC. The filtered difference
signal is fed to the comparator, whose output samples the differ-
ence signal at a frequency many times that of the analog signal
sampling frequency (oversampling).
AD7712Figure 6. Frequency Response of AD7712 Filter
Since the AD7712 contains this on-chip, low-pass filtering,
there is a settling time associated with step function inputs, and
data on the output will be invalid after a step change until the
settling time has elapsed. The settling time depends upon the
notch frequency chosen for the filter. The output data rate
equates to this filter notch frequency, and the settling time of
the filter to a full-scale step input is four times the output data
period. In applications using both input channels, the settling
time of the filter must be allowed to elapse before data from the
second channel is accessed.
Post FilteringThe on-chip modulator provides samples at a 19.5kHz output
rate. The on-chip digital filter decimates these samples to pro-
vide data at an output rate that corresponds to the programmed
first notch frequency of the filter. Since the output data rate
exceeds the Nyquist criterion, the output rate for a given band-
width will satisfy most application requirements. However,
there may be some applications which require a higher data rate
for a given bandwidth and noise performance. Applications that
need this higher data rate will require some post filtering follow-
ing the digital filter of the AD7712.
For example, if the required bandwidth is 7.86 Hz but the
required update rate is 100 Hz, the data can be taken from the
AD7712 at the 100 Hz rate giving a –3 dB bandwidth of
26.2 Hz. Post filtering can be applied to this to reduce the
bandwidth and output noise, to the 7.86 Hz bandwidth level,
while maintaining an output rate of 100 Hz.
Post filtering can also be used to reduce the output noise from
the device for bandwidths below 2.62 Hz. At a gain of 128, the
output rms noise is 250 nV. This is essentially device noise or
white noise, and since the input is chopped, the noise has a flat
frequency response. By reducing the bandwidth below 2.62 Hz,
the noise in the resultant passband can be reduced. A reduction
in bandwidth by a factor of two results in a √2 reduction in the
output rms noise. This additional filtering will result in a longer
settling time.
Input Sample RateThe modulator sample frequency for the device remains at
fCLK IN/512 (19.5 kHz @ fCLK IN = 10 MHz) regardless of the
selected gain. However, gains greater than ·1 are achieved by a
combination of multiple input samples per modulator cycle and
a scaling of the ratio of reference capacitor to input capacitor.
As a result of the multiple sampling, the input sample rate of
the device varies with the selected gain (see Table III). The
effective input impedance is 1/C · fS where C is the input sam-
pling capacitance and fS is the input sample rate.
Table III.Input Sampling Frequency vs. Gain22 ·
44 ·
88 ·
DIGITAL FILTERINGThe AD7712’s digital filter behaves like a similar analog filter,
with a few minor differences.
First, since digital filtering occurs after the A-to-D conversion
process, it can remove noise injected during the conversion
process. Analog filtering cannot do this.
On the other hand, analog filtering can remove noise superim-
posed on the analog signal before it reaches the ADC. Digital
filtering cannot do this, and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
and digital filter, even though the average value of the signal is
within limits. To alleviate this problem, the AD7712 has over-
range headroom built into the sigma-delta modulator and digital
filter which allows overrange excursions of 5% above the analog
input range. If noise signals are larger than this, consideration
should be given to analog input filtering, or to reducing the
input channel voltage so that its full scale is half that of the
analog input channel full scale. This will provide an overrange
capability greater than 100% at the expense of reducing the
dynamic range by 1 bit (50%).
Filter CharacteristicsThe cutoff frequency of the digital filter is determined by the
value loaded to bits FS0 to FS11 in the control register. At the
maximum clock frequency of 10 MHz, the minimum cutoff
frequency of the filter is 2.58 Hz while the maximum program-
mable cutoff frequency is 269 Hz.
Figure 6 shows the filter frequency response for a cutoff fre-
quency of 2.62 Hz, which corresponds to a first filter notch
frequency of 10 Hz. This is a (sinx/x)3 response (also called
sinc3) that provides >100 dB of 50 Hz and 60 Hz rejection.
Programming a different cutoff frequency via FS0–FS11 does
not alter the profile of the filter response; it changes the fre-
