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AD7709BRU
16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O Port
aREV. PrA January 2001
16-Bit Sigma Delta ADC with Current Sources,
Switchable Reference Inputs and I/O PortPRELIMINARY TECHNICAL DATA
16-BIT SINGLE CHANNEL SIGMA DELTA-ADC
Factory Calibrated (field calibration not required)
Output settles in one conversion cycle (single conver
sion mode)
Programmable Gain Front End
16-bit No Missing Codes
13-bit Pk-Pk Resolution @ 20Hz, 20mV Range
16-bit Pk-PK Resolution @ 20Hz, 2.56V Range
INTERFACE
Three-Wire Serial
SPITM, QSPITM, MICROWIRETM and DSP Compatible
Schmitt Trigger on SCLK
POWER
Specified for Single 3V and 5V operation
Normal : 2mA @ 3V
Powerdown : 20uA (32kHz Crystal Running)
On-Chip Functions
Rail-to-Rail Input Buffer and PGA
Switchable Reference Inputs
3 Configurable Current Sources
Low Side Power Swtches
Digital I/O Port
APPLICATIONS
Industrial Process Control
Instrumentation
Pressure Transducers
Portable Instrumentation
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD7709 is a complete analog front-end for low
frequency measurement applications. The AD7709
contains a 16-bit sigma delta ADC with PGA and can be
configured as 2 fully-differential input channels or 4
pseudo-differential input channels. Inputs signal ranges
from 20mV to 2.56V can be directly converted using the
AD7709. These signals can be converted directly from a
transducer without the need for signal conditioning. Other
on-chip features include three software configurable
current sources, switchable reference inputs, low side
power switches and a 4-bit digital I/O port.
The device operates from a 32kHz crystal with an on-
board PLL generating the required internal operating
frequency. The output data rate from the part is software
programmable. The pk-pk resolution from the part varies
with the programmed gain and output data rate.
The part operates from a single +3V or +5V supply.
When operating from +3V supplies, the power dissipation
for the part is XmW. The AD7709 are housed in a 24-
pin SOIC and TSSOP packages.
fi SPIand QSPI are a Registered Trademark of Motorola Inc.
FEATURES
XTAL1XTAL2REFIN2(+)REFIN2(-)VDD
REFIN1(+)REFIN1(-)
SW2/P2SW1/P1GND
AIN1
IOUT 1
IOUT 2
AIN2
AIN3 / P3
AIN4 / P4
AINCOM
DOUT
DIN
SCLK
RDY
RESET
PWRGND
AD7709-SPECIFICATIONS1(VDD = +3V or +5.0V , REFIN(+) = +2.5V; REFIN(-) = 0V;
XTAL1/XTAL2 = 32 kHz Crystal;
All specifications TMIN to TMAX unless otherwise noted.)PRELIMINARY TECHNICAL DATA
PARAMETERB GradeUnitsTest ConditionsOutput Update Rate5.4Hz min.
105Hz max. 0.021Hz (0.732msec.) increments
No Missing Codes16bits min.
Resolution13bits pk-pk+20mV range, 20Hz Update Ratebits pk-pk+2.56V range, 20Hz Update Rate
Output Noise and Update RatesSee Tables Below in ADC Description
Integral Nonlinearity15ppm of FSR max.
Offset ErrorTBD
Offset Error Drift Vs Temp10nV/°C typ.
Offset Error Drift Vs TimeTBDnV/1000 Hours typ.
Gain ErrorTBD
Gain Error Drift Vs Temp1ppm/°Ctyp.
Gain Error Drift Vs TimeTBDppm/1000 Hours typ.
Power Supply Rejection(PSR)90dB min.Input Range = ±20mVdB min.Input Range = ±2.56V
Common Mode Rejection(CMR)
On AIN90dB min.At DC, Range = ±20mV
On AIN90dB min.At DC, Range = ±2.56V
On REFIN90dB min.At DC, Range = ±20mV
On REFIN90dB min.At DC, Range = ±2.56V
Analog Input Current
DC Bias Current1nA max.
DC Bias Current DriftTBDnA typ.
DC Offset CurrentTBDnA typ.
DC Offset Current DriftTBDnA typ.
REFERENCE INPUTS (REFIN1& REFIN2)
Normal Mode
50Hz/60Hz Rejection60dB min.
Reference DC Input CurrentTBDμA typ.
REFIN(+) to REFIN(-) Voltage+2.5Vnom.REFIN referes to both REFIN1 and REFIN2
REFIN(+) to REFIN(-) Range+1V min.
VDDV max.
REFIN Common Mode RangeGND-30mVV min.
VDD+30mVV max.
REFIN Common Mode
50/60Hz RejectionTBDdB min.
ANALOG INPUTSNormal Mode 50Hz/60Hz Rejection60dB min.50/60Hz ±1Hz , 20Hz Update Rate
Common Mode 50/60Hz Rejection90dB min.50/60Hz ±1Hz, Range = ±20mVdB min.50/60Hz ±1Hz, Range = ±2.5V
Differential Input Voltage Ranges
±REFIN/GAINV nom.REFIN refers to both REFIN1 and
REFIN2.
REFIN=REFIN(+ )-REFIN(-)
GAIN=1to 128.
Pseudo-Differential Input Voltage Ranges
0V to REFIN/GAINV nom.
Full-scale Range Matching5uV typ.
Absolute Ain Voltage Limits
Buffered InputsGND+50mVV min.
VDD-50mVV max
Unbuffered InputsGND-30mVVmin
AD7709PRELIMINARY TECHNICAL DATA
LOGIC INPUTS
All Inputs Except SCLK and XTAL1
VINL, Input Low Voltage0.8V max.VDD = 5V
VINL, Input Low Voltage0.4V max.VDD = 3V
VINH, Input High Voltage2.0V min.VDD = 3V or 5V
SCLK Only (Schmitt Triggered Input)
VT(+)1.4/3V min/V maxVDD = 5V
VT(-)0.8/1.4V min/V maxVDD = 5V
VT(+)- VT(-)0.4/0.85V min/V maxVDD = 5V
VT(+)0.95/2.5V min/V maxVDD = 3V
VT(-)0.4/1.1V min/V maxVDD = 3V
VT(+)-VT(-)0.4/0.85V min/V maxVDD = 3V
XTAL1 Only
VINL, Input Low Voltage0.8V max.VDD = 5V
VINH, Input High Voltage3.5V min.VDD = 5V
VINL, Input Low Voltage0.4V max.VDD = 3V
VINH, Input High Voltage2.5V min.VDD = 3V
Input Currents±10μA max.VIN = 0V or VDD
Input Capacitance10pF typ.All Digital Inputs
LOGIC OUTPUTS (Excluding XTAL2)
VOH, Output High VoltageVDD- 0.6V min.VDD = 3V, ISOURCE = 100μA
VOL, Output Low Voltage0.4V max.VDD = 3V, ISINK = 100μA
VOH, Output High Voltage4V min.VDD = 5V, ISOURCE = 200μA
VOL, Output Low Voltage0.4V max.VDD = 5V, ISINK = 1.6mA
Floating State Leakage Current±10uA max.
Floating State Output Capacitance±10pF typ.
Data Output CodingBinaryUnipolar Mode
Offset BinaryBipolar Mode
EXCITATION CURRENT SOURCES
I1 and I2 Output Current200μA nom.
I3 Output Current25μA nom.
Initial Tolerance at 25°C±10% typ.
Drift20ppm/°C typ.
Initial Current Matching at 25°C±1%Matching between I1 and I2
Drift Matching1ppm/°C typ.
Line Regulation (VDD)TBDnA/V max.VDD = 5V±10%
Load RegulationTBDnA/V max.
Output ComplianceAVDD-0.5V max.
Low-Side Power Switches (SW1 and SW2)
Ron5Ω typVDD = 5VΩ typVDD = 3V
Allowable Current20mA maxPer Switch
SYSTEM CALIBRATION
Full-Scale Calibration Limit1.05 X FSV max.
Zero-Scale Calibration Limit-1.05 X FSV min.
Input Span0.8 X FSV min.
2.1 X FSV max.
START UP TIME
From Power-On500msec typ.
From Idle Mode1msec. typ.
From Power-Down Mode1msec. typ.
500msec. typ.Osc. powered down
PARAMETERB GradeUnitsTest Conditions
AD7709PRELIMINARY TECHNICAL DATA
PARAMETERB GradeUnitsTest Conditions
Power Supply CurrentsVDD Current (Normal Mode)TBDmAVDD=3V
VDD Current (Normal Mode)TBDmAVDD=5V
VDD Current (Idle Mode)TBDmAVDD=3V
VDD Current (Idle Mode)TBDmAVDD=5V
VDD Current (Power-Down Mode)20μA max.VDD=3V, 32.768kHz Osc. Running
VDD Current (Power-Down Mode)30μA max.VDD=5V, 32.768kHz Osc. Running
NOTESTemperature Range -40 °C to +85°C
PRELIMINARY TECHNICAL DATA
ORDERING GUIDE
ModelTemperaturePackagePackage Drawing
RangeDescriptionOptionAD7709BR-40°C to +85°CSOICR-24
AD7709BRU-40°C to +85°CTSSOPRU-24 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
VDD to GND.............................................-0.3V to +7V
Analog Input Voltage to GND...........-0.3V to VDD +0.3V
Reference Input Voltage to GND.......-0.3V to VDD +0.3V
AIN/REFIN Current (Indefinite)...........................30mA
Digital Input Voltage to GND...........-0.3V to VDD +0.3V
Digital Output Voltage to GND........-0.3V to VDD +0.3V
PWRGND to GND...............................-0.3V to +0.3V
Operating Temperature Range..................-40°C to 85°C
Storage Temperature Range....................-65°C to 150°C
Junction Temperature........................................+150°C
PACKAGE Power Dissipation........................TBD mW
θJA Thermal Impedance..................................90°C/W
Lead Temperature, Soldering
Vapor Phase (60sec)..................................+215°C
Infrared (15 sec).......................................+220°C
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7709 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
OUTLINE DIMENSIONS
24-lead plastic SOIC (R-24)
24-lead plastic TSSOP (RU-24)3 (
7 (
4 (
40)
PIN 1
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
(1.27)
BSC0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
AD7709PRELIMINARY TECHNICAL DATA
TIMING CHARACTERISTICS1, 2 (VDD = +3V ±10% or VDD = +5V ±10%;GND = 0 V:XTAL = 32.768kHz; Input Logic 0 = 0 V, Logic 1 = VDD
unless otherwise noted)
Limit at TMIN, TMAX
Parameter(B Version)UnitsConditions/Comments32.768kHz typCrystal Oscillator Frequency.50ns minRESET Pulse Width
Read Operation0ns minRDY to CS Setup Time0ns minCS Falling Edge to SCLK Active Edge Setup
Time340ns minSCLK Active Edge to Data Valid Delay3ns maxVDD = +4.5 V to +5.5 Vns maxVDD = +2.7 V to +3.6 V
t5A4, 50ns minCS Falling Edge to Data Valid Delay3ns maxVDD = +4.5 V to +5.5 Vns maxVDD = +2.7 V to +3.6 V100ns minSCLK High Pulse Width100ns minSCLK Low Pulse Width0ns minCS Rising Edge to SCLK Inactive Edge Hold
Time3610ns minBus Relinquish Time after SCLK Inactive Edge3ns max
t10100ns maxSCLK Active Edge to RDY High3, 7
Write Operationt110ns minCS Falling Edge to SCLK Active Edge Setup
Time3
t1230ns minData Valid to SCLK Edge Setup Time
t1325ns minData Valid to SCLK Edge Hold Time
t14100ns minSCLK High Pulse Width
t15100ns minSCLK Low Pulse Width
t160ns minCS Rising Edge to SCLK Edge Hold Time
NOTES
1Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2See Figures 1 and 2.
3SCLK active edge is falling edge of SCLK.
4These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the VOL or VOH limits.
5This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.
6These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove effects of charging or
discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
7RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to
the next output update.
PRELIMINARY TECHNICAL DATA
DINt12
t13
SCLK t16
DOUTt5A
SCLK RDY
Figure 1. Write Cycle Timing Diagram
Figure 2. Read Cycle Timing Diagram
AD7709PRELIMINARY TECHNICAL DATA
PIN CONFIGURATION
Pin Function Description
Pin NoMnemonicFunctionIOUT1Output for internal excitation current sources. A single current source or any
combination of the internal current sources I1,I2 and I3 can be switched to this
output.IOUT2Output for internal excitation current sources. A single current source or any
combination of the internal current sources I1,I2 and I3 can be switched to this
output.REFIN1(+)Positive reference input. REFIN(+) can lie anywhere between VDD and GND.
The nominal reference voltage (REFIN(+)-REFIN(-)) is 2.5V but the part is
functional with a reference range from 1V to VDD.REFIN1(-)Negative reference input. This reference input can lie anywhere between GND
and VDD-1V.AIN1Analog Input Channel 1. Programmable-gain analog input which can be used
as a pseudo-differential input when used with AINCOM or as the positive in-
put of a fully-differential input pair when used with AIN2. (see Communica-
tions Register section)AIN2Analog Input Channel 2. Programmable-gain analog input which can be used
as a pseudo-differential input when used with AINCOM or as the negative
input of a fully-differential input pair when used with AIN1. (see Communica-
tions Register section)AIN3/P3Analog Input Channel 3 or Digital Port Bit. Programmable-gain analog input
which can be used as a pseudo-differential input when used with AINCOM or
as the positive input of a fully-differential input pair when used with AIN4.
The second function of this bit is as a general purpose digital input bit.AIN4/P4Analog Input Channel 4 or digital port bit. Programmable-gain analog input
which can be used as a pseudo-differential input when used with AINCOM or
as the negative input of a fully-differential input pair when used with AIN3.
The second function of this bit is as a general purpose digital input bit.AINCOMAll analog inputs are referenced to this input when configured in pseudo-dif-
PRELIMINARY TECHNICAL DATAREFIN2(-)Negative reference input. This reference input can lie anywhere between GND
and VDD-1V.P2/SW2P2 can act as a general purpose Input/Output bit referenced between VDD and
GND or as a low-side power switch to PWRGND..PWRGNDGround point for the low-side power switches SW2 and SW1. PWRGND
must be tied to GND.P1/SW1P1 can act as a general purpose Output bit referenced between VDD and GND
or as a low-side power switch to PWRGND.RESETDigital input used to reset the ADC to its power-on-reset status. This pin has
a weak pull-up internally to DVDD.SCLKSerial clock input for data transfers to and from the ADC. The SCLK has a
schmitt triggered input making the interface suitable for opto-isolated applica-
tions. The serial clock can be continuous with all data transmitted in a con-
tinuous train of pulses. Alternatively, it can be noncontinuous clock with the
information being transmitted to or from the AD7709 in smaller batches of
data.CSChip Select Input. This is an active low logic input used to select the
AD7709. CS can be used to select the AD7709 in systems with more than one
device on the serial bus or as a frame synchronisation signal in communicating
with the device. CS can be hardwired low allowing the AD7709 to be operated
in three-wire mode with SCLK, DIN and DOUT used to interface with the
device.RDYRDY is a logic low status output from the AD7709. RDY is low if the ADC
has valid data in its data register. This output returns high on completion of a
read operation from the data register. If data is not read, RDY will return high
prior to the next update indicating to the user that a read operation should not
be initiated.DOUTSerial data output with serial data being read from the output shift register of
the ADC. The output shift register can contain data from any of the on-chip
data, calibration or control registers.DINSerial Data Input with serial data being written to the input shift register on
the AD7709. Data in this shift register is transferred to the control registers
within the ADC depending on the selection bits of the Communications regis-
ter.GNDGround Reference point for the AD7709.VDDSupply voltage, 3V or 5V nominal.XTAL2Output from the 32kHz crystal oscillator inverter.XTAL1Input to the 32kHz crystal oscillator inverter.
