AD7709ARU ,16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O Portapplications. It contains a 16-bit - ADC, selectable16-Bit p-p Resolution @ 20 Hz, 2.56 V Rangere ..
AD7709BRU ,16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O PortAPPLICATIONSFUNCTIONAL BLOCK DIAGRAMIndustrial Process ControlInstrumentationREFIN2(+) REFIN1(+) RE ..
AD7710AN ,Signal Conditioning ADCSPECIFICATIONSDD DD SSREF␣ IN(–) = AGND; MCLK IN = 10␣ MHz unless otherwise noted. All
AD7710AR ,Signal Conditioning ADCfeatures two differential analog inputs and a differen- removing a considerable amount of signal co ..
AD7710ARZ-REEL7 , Signal Conditioning ADC
AD7710SQ ,Signal Conditioning ADCFEATURESCharge Balancing ADCREF REF24 Bits No Missing CodesAV DV IN (–) IN (+) V REF OUTDD DD BIAS6 ..
ADM1028ARQ ,Remote Thermal Diode Monitor with Linear Fan ControlSPECIFICATIONS (T = T to T , V = V to V , unless otherwise noted.)A MIN MAX CC MIN MAXParameter Min ..
ADM1028ARQ-REEL ,Remote Thermal Diode and Linear Fan ControlSPECIFICATIONS (T = T to T , V = V to V , unless otherwise noted.)A MIN MAX CC MIN MAXParameter Min ..
ADM1028ARQ-REEL ,Remote Thermal Diode and Linear Fan ControlCHARACTERISTICSPositive Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . 6.5 VCC 16-Le ..
ADM1028ARQ-REEL7 ,Remote Thermal Diode and Linear Fan ControlGENERAL DESCRIPTIONOn-Chip Temperature Sensor The ADM1028 is a low-cost temperature monitor and fan ..
ADM1030ARQ ,Intelligent Temperature Monitor and PWM Fan ControllerSPECIFICATIONS A MIN MAX CC MIN MAXParameter Min Typ Max Unit Test Conditions/CommentsPOWER SUPPLYS ..
ADM1030ARQ-REEL ,Complete, ACPI Compliant ±1°C Remote Thermal Monitor with Integrated Fan ControllerFEATURES PRODUCT DESCRIPTION®Optimized for Pentium III: Allows Reduced Guardbanding The ADM1030 is ..
AD7709ARU
16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O Port
REV.A
16-Bit �-� ADC with
Switchable Current Sources
FUNCTIONAL BLOCK DIAGRAMIOUT1
IOUT2
XTAL2REFIN1(–)REFIN2(–)REFIN1(+)REFIN2(+)XTAL1
DOUT
RESET
RDY
SCLK
DIN
AIN1
AIN2
AIN3/P3
AIN4/P4
AINCOM
VDDGNDPWRGNDP1/SW1P2/SW2
FEATURES
16-Bit �-� ADC
Programmable Gain Front End
Simultaneous 50 Hz and 60 Hz Rejection at 20 Hz
Update Rate
VREF Select™ Allows Absolute and Ratiometric
Measurement Capability
ISOURCE Select™
16-Bit No Missing Codes
13-Bit p-p Resolution @ 20 Hz, 20 mV Range
16-Bit p-p Resolution @ 20 Hz, 2.56 V Range
INTERFACE
3-Wire Serial
SPI®, QSPI™, MICROWIRE™, and DSP Compatible
Schmitt Trigger on SCLK
POWER
Specified for Single 3 V and 5 V Operation
Normal: 1.25 mA Typ @ 3 V
Power-Down: 7 �A (32.768 kHz Crystal Running)
ON-CHIP FUNCTIONS
Rail-to-Rail Input Buffer and PGA
Selectable Reference Inputs
3 Switchable, Ratioed Current Sources for
VBE Measurements
4-Bit Digital I/O Port
Low-Side Power Switches
APPLICATIONS
Sensor Measurement
Temperature Measurement
Pressure Measurements
Weigh Scales
Portable Instrumentation
4–20 mA Loops
GENERAL DESCRIPTIONThe AD7709 is a complete analog front end for low frequency
measurement applications. It contains a 16-bit �-� ADC, selectable
reference inputs, three switchable matched excitation current
sources, low-side power switches, and a digital I/O port. The
16-bit channel with PGA accepts fully differential, unipolar,
and bipolar input signal ranges from 1.024 � REFIN/128 to
1.024 � REFIN. It can be configured as two fully differential
input channels or four pseudo-differential input channels. Signals
can be converted directly from a transducer without the need for
signal conditioning.
The device operates from a 32.768 kHz crystal with an on-chip
PLL generating the required internal operating frequency. The
output data rate from the part is software programmable. The
p-presolution from the part varies with the programmed gain
and output data rate.
The part operates from a single 3 V or 5 V supply. When
operating from 3 V supplies, the power dissipation for the part
is 3.75 mW. The AD7709 is housed in a 24-lead TSSOP package.
AD7709
TABLE OF CONTENTSFEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 6
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 8
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 9
TYPICAL PERFORMANCE CHARACTERISTICS . . . . 10
ADC CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . 11
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11S-D ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
NOISE PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . 13
ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Communications Register . . . . . . . . . . . . . . . . . . . . . . . . 14
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ADC Data Result Register . . . . . . . . . . . . . . . . . . . . . . . . 18
CONFIGURING THE AD7709 . . . . . . . . . . . . . . . . . . . . . 19
DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MICROCOMPUTER/MICROPROCESSOR
INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AD7709-to-68HC11 Interface . . . . . . . . . . . . . . . . . . . . . 21
AD7709-to-8051 Interface . . . . . . . . . . . . . . . . . . . . . . . . 21
AD7709-to-ADSP-2103/ADSP-2105 Interface . . . . . . . . 21
CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 22
Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 23
Bipolar/Unipolar Configuration . . . . . . . . . . . . . . . . . . . . 23
Data Output Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Excitation Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pressure Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . 26
3-Wire RTD Configurations . . . . . . . . . . . . . . . . . . . . . . 27
Smart Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AD7709
SPECIFICATIONS1(VDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = GND; GND = 0 V; XTAL1/XTAL2 =
32.768 kHz Crystal; all specifications TMIN to TMAX, unless otherwise noted.)See Notes on page 5.
AD7709LOGIC INPUTS
(continued)SPECIFICATIONS
LOGIC OUTPUTS (Excluding XTAL2)
I/O PORT
START-UP TIME
NOTESTemperature Range –40∞C to +85∞C.Guaranteed by design and/or characterization data on production release.Full-scale error applies to both positive and negative full scale.Simultaneous 50 Hz and 60 Hz rejection is achieved using 19.79 Hz update rate. Normal mode rejection in this case is 60 dB min.When the part is placed in power-down mode for a single conversion/second, at an update rate of 19.79 Hz, the current consumption is higher compared to when the
part is placed in standby mode as the crystal oscillator takes approximately 100 ms to begin clocking. The device will, therefore, use full current for the conversion
time and the 100 ms period required for the oscillator to begin clocking. However, if the conversion rate is lower, the current consumption will be reduced so that it
is worthwhile to use the power-down rather than the standby mode.
Specifications subject to change without notice.
AD7709
AD7709
TIMING CHARACTERISTICS1, 2Read Operation
NOTESSample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.See Figures 2 and 3.SCLK active edge is falling edge of SCLK.These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.This specification comes into play only if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.These numbers are derived from the measured time taken by the data output to change 0.5V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics table are the true bus relinquish
times of the part and as such are independent of external bus loading capacitances.RDY returns high after a read of the ADC. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur
close to the next output update.
(VDD = 2.7 V to 3.6 V or VDD = 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V,
Logic 1 = VDD unless otherwise noted.)
Figure 1.Load Circuit for Timing Characterization
Figure 2.Write Cycle Timing Diagram
Figure 3.Read Cycle Timing Diagram
AD7709
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS*(TA = 25∞C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
PWRGND to AGND . . . . . . . . . . . . . . –20 mV to +20 mV
Analog Input Voltage to GND . . . . . –0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . –0.3 V to VDD + 0.3 V
Total AIN/REFIN Current (Indefinite) . . . . . . . . . . 30 mA
Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to GND . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range . . . . . . . . . . –40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150∞CqJA Thermal Impedance . . . . . . . . . . . . . . . . . . . 97.9∞C/WqJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 14∞C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215∞C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDEAD7709BRU
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7709 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONSAD7709–Typical Performance CharacteristicsTPC 3. Noise Histogram
TPC 4.Typical Oscillator Power-Up
TPC 1.Typical Noise Plot on ±20 mV Input Range
TPC 2.RMS Noise vs. Reference Input
ADC CIRCUIT INFORMATION
OverviewThe AD7709 incorporates a �-� ADC channel with on-chip digital
filtering intended for the measurement of wide dynamic range, low
frequency signals such as those in weigh-scale, strain-gauge,
pressure transducer, or temperature measurement applications.
�-� ADC
This channel can be programmed to have one of eight input
voltage ranges from ±20 mV to ±2.56 V. This channel can be
configured as either two fully differential inputs (AIN1/AIN2
and AIN3/AIN4) or four pseudo-differential input channels
(AIN1/AINCOM, AIN2/AINCOM, AIN3/AINCOM, and
AIN4/AINCOM). Buffering the input channel means that the
part can accommodate significant source impedances on the
analog input and that R, C filtering (for noise rejection or RFI
reduction) can be placed on the analog inputs if required.
The ADC employs a �-� conversion technique to realize up to
16 bits of no-missing-codes performance. The �-� modulator
converts the sampled input signal into a digital pulse train whose
duty cycle contains the digital information. A Sinc3 programmable
low-pass filter is then employed to decimate the modulator output
data stream to give a valid data conversion result at programmable
output rates from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms).
A chopping scheme is also employed to minimize ADC channel
offset errors. A block diagram of the ADC input channel is shown
in Figure 4.
The sampling frequency of the modulator loop is many times
higher than the bandwidth of the input signal. The integrator in
the modulator shapes the quantization noise (which results from
the analog-to-digital conversion) so that the noise is pushed
toward one-half of the modulator frequency. The output of the
�-� modulator feeds directly into the digital filter. The digital
filter then band-limits the response to a frequency significantly
lower than one-half of the modulator frequency. In this manner,
the 1-bit output of the comparator is translated into a band-
limited, low noise output from the AD7709 ADC. The AD7709
filter is a low-pass, Sinc3, or (SIN(x)/x)3 filter whose primary
function is to remove the quantization noise introduced at the
modulator. The cutoff frequency and decimated output data
rate of the filter are programmable via the SF word loaded to the
filter register.
A chopping scheme is employed where the complete signal chain
is chopped, resulting in excellent dc offset and offset drift speci-
fications, and is extremely beneficial in applications where drift,
noise rejection, and optimum EMI rejection are important fac-
tors. With chopping, the ADC repeatedly reverses its inputs.
The decimated digital output words from the Sinc3 filters there-
fore have a positive offset and negative offset term included. As a
result, a final summing stage is included so that each output
word from the filter is summed and averaged with the previous
filter output to produce a new valid output result to be written to
the ADC data register.
The input chopping is incorporated into the input multiplexer
while the output chopping is accomplished by an XOR gate at
the output of the modulator. The chopped modulator bit stream
is applied to a Sinc3 filter. The programming of the Sinc3 deci-
mation factor is restricted to an 8-bit register SF, the actual
decimation factor is the register value × 8. The decimated out-
put rate from the Sinc3 filter (and the ADC conversion rate) will
therefore be:
where:
fADC is the ADC update rate.
SF is the decimal equivalent of the word loaded to the
filter register.
fMOD is the modulator sampling rate of 32.768 kHz.
Programming the filter register determines the update rate for the
ADC. The chop rate of the channel is half the output data rate.
The frequency response of the filter H(f) is as follows:
where:
fMOD = 32,768 Hz.
SF = value programmed into Filter Register.
fOUT = fMOD/(SF � 8 � 3)
The following shows plots of the filter frequency response for the
SF words shown in Table I. The overall frequency response is the
product of a Sinc3 and a sinc response. There are Sinc3 notches
at integer multiples of 3 � fADC, and there are sinc notches at odd
integer multiples of fADC/2. The 3 dB frequency for all values of SF
obeys the following equation:
The signal chain is chopped as shown in Figure 4. The chop
frequency is:
ANALOG
INPUT
DIGITAL
OUTPUT
fCHOPfINfMODfCHOPfADC
AD7709As shown in the block diagram, the Sinc3 filter outputs alternately
contain +VOS and –VOS, where VOS is the respective channel offset.
This offset is removed by performing a running average of 2, which
means that the settling time to any change in programming of
the ADC will be twice the normal conversion time, while an
asynchronous step change on the analog input will not be fully
reflected until the third subsequent output.
The allowable range for SF is 13 to 255, with a default of 69
(45H). The corresponding conversion rates, conversion times,
and settling times are shown in Table I. Note that the conver-
sion time increases by 0.732 ms for each increment in SF.
Figure5.Filter Profile with SF = 13
Table I.ADC Conversion and Settling Times for Various
SF WordsNormal mode rejection is the major function of the digital filter
on the AD7709. The normal mode 50 ± 1 Hz rejection with an
SF word of 82 is typically –100 dB. The 60 ± 1 Hz rejection with
SF = 68 is typically –100 dB. Simultaneous 50 Hz and 60Hz
rejection of better than 60 dB is achieved with an SF of 69.
Choosing an SF word of 69 places notches at both 50 Hz andHz. Figures 5 to 8 show the filter rejection for a selection
of SF words.
Figure 7.Filter Profile with Default SF = 69 Giving Filter
Notches at Both 50 Hz and 60 Hz
NOISE PERFORMANCETables II and III show the output rms noise and output peak-to-
peak resolution in bits (rounded to the nearest 0.5 LSB) for a
selection of output update rates. The numbers are typical and
generated at a differential input voltage of 0 V. The output update
rate is selected via the SF7–SF0 bits in the Filter Register. It is
important to note that the peak-to-peak resolution figures
represent the resolution for which there will be no code flicker
within a six-sigma limit. The output noise comes from two sources.
The first is the electrical noise in the semiconductor devices
(device noise) used in the implementation of the modulator.
Second, when the analog input is converted into the digital
domain, quantization noise is added. The device noise is at a low
Figure 9.On-Chip Registers
level and is independent of frequency. The quantization noise starts
at an even lower level but rises rapidly with increasing frequency
to become the dominant noise source. The numbers in the tables
are given for the bipolar input ranges. For the unipolar ranges,
the rms noise numbers will be the same as the bipolar range, but
the peak-to-peak resolution is now based on half the signal range,
which effectively means losing 1 bit of resolution.
ON-CHIP REGISTERSThe AD7709 is controlled and configured via a number of on-chip
registers, as shown in Figure 9 and described in more detail in the
following pages. In the following descriptions, set implies a Logic 1
state and cleared implies a Logic 0 state, unless otherwise stated.
Table II.Typical Output RMS Noise vs. Input Range and Update Rate for the AD7709 (Output RMS Noise in �V)
Table III.Peak-to-Peak Resolution vs. Input Range and Update Rate for the AD7709 (Peak-to-Peak Resolution in Bits)
AD7709
Communications Register (A1, A0 = 0, 0)The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the
Communications Register. The data written to the Communications Register determines whether the next operation is a read or
write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write
operation to the selected register is complete, the interface returns to where it expects a write operation to the Communications
Register. This is the default state of the interface, and on power-up or after a RESET, the AD7709 is in this default state waiting for
a write operation to the Communications Register. In situations where the interface sequence is lost, a write operation of at least 32
serial clock cycles with DIN high, returns the AD7709 to this default state by resetting the part. Table IV outlines the bit designations for
the Communications Register. CR0 to CR7 indicate the bit location, CR denoting the bits are in the Communications Register. CR7
denotes the first bit of the data stream.
Table IV.Communications Register Bit Designations
Table V.Register Selection Table
Status Register (A1, A0 = 0, 0; Power-On-Reset = 00H)The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communica-
tions Register, selecting the next operation to be a read and load bits A1–A0 with 0, 0. Table VI outlines the bit designations for the
Status Register. SR0 to SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first bit of the
data stream. The number in brackets indicates the power-on-reset default status of that bit.
Table VI. Status Register Bit Designations
AD7709
Table VII.Configuration Register Bit Designations
Configuration Register (A1, A0 = 0, 1; Power-On-Reset = 000007H)The Configuration Register is a 24-bit register from which data can either be read or to which data can be written. This register is used to
select the input channel and configure the input range, excitation current sources, and I/O port. Table VII outlines the bit designations
for this register. CONFIG23 to CONFIG0 indicate the bit location, CONFIG denoting the bits are in the Configuration Register.
CONFIG23 denotes the first bit of the data stream. The number in brackets indicates the power-on-reset default status of that bit. A
write to the Configuration Register has immediate effect and does not reset the ADC. Therefore, if a current source is switched
while the ADC is converting, the user will have to wait for the full settling time of the sinc3 filter before obtaining a fully settled output.
This equates to three outputs.
