AD7708BR ,8-/10-Channel, Low Voltage, Low Power, ADCsAPPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41ADC Control Register ..
AD7708BRU ,8-/10-Channel, Low Voltage, Low Power, ADCsapplications. The AD7718 contains aAD7718 Has 24-Bit Resolution 24-bit Σ-∆ ADC with PGA and can be ..
AD7709ARU ,16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O Portapplications. It contains a 16-bit - ADC, selectable16-Bit p-p Resolution @ 20 Hz, 2.56 V Rangere ..
AD7709BRU ,16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O PortAPPLICATIONSFUNCTIONAL BLOCK DIAGRAMIndustrial Process ControlInstrumentationREFIN2(+) REFIN1(+) RE ..
AD7710AN ,Signal Conditioning ADCSPECIFICATIONSDD DD SSREF␣ IN(–) = AGND; MCLK IN = 10␣ MHz unless otherwise noted. All
AD7710AR ,Signal Conditioning ADCfeatures two differential analog inputs and a differen- removing a considerable amount of signal co ..
ADM1028ARQ ,Remote Thermal Diode Monitor with Linear Fan ControlSPECIFICATIONS (T = T to T , V = V to V , unless otherwise noted.)A MIN MAX CC MIN MAXParameter Min ..
ADM1028ARQ-REEL ,Remote Thermal Diode and Linear Fan ControlSPECIFICATIONS (T = T to T , V = V to V , unless otherwise noted.)A MIN MAX CC MIN MAXParameter Min ..
ADM1028ARQ-REEL ,Remote Thermal Diode and Linear Fan ControlCHARACTERISTICSPositive Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . 6.5 VCC 16-Le ..
ADM1028ARQ-REEL7 ,Remote Thermal Diode and Linear Fan ControlGENERAL DESCRIPTIONOn-Chip Temperature Sensor The ADM1028 is a low-cost temperature monitor and fan ..
ADM1030ARQ ,Intelligent Temperature Monitor and PWM Fan ControllerSPECIFICATIONS A MIN MAX CC MIN MAXParameter Min Typ Max Unit Test Conditions/CommentsPOWER SUPPLYS ..
ADM1030ARQ-REEL ,Complete, ACPI Compliant ±1°C Remote Thermal Monitor with Integrated Fan ControllerFEATURES PRODUCT DESCRIPTION®Optimized for Pentium III: Allows Reduced Guardbanding The ADM1030 is ..
AD7708BR-AD7708BRU-AD7718BR
8-/10-Channel, Low Voltage, Low Power, ADCs
REV.0
8-/10-Channel, Low Voltage,
Low Power, �-� ADCs
FUNCTIONAL BLOCK DIAGRAM
DVDDXTAL1XTAL2
AIN1
AIN2
AIN3
AIN4
DOUT
DIN
SCLK
RDY
RESET
AVDD
DGNDP1
REFIN2(+)/AIN9REFIN1(+)REFIN2(–)/AIN10REFIN1(–)
AINCOM
AIN5
AIN6
AIN7
AIN8
AGND
FEATURES
8-/10-Channel, High Resolution �-� ADCs
AD7708 Has 16-Bit Resolution
AD7718 Has 24-Bit Resolution
Factory-Calibrated
Single Conversion Cycle Setting
Programmable Gain Front End
Simultaneous 50 Hz and 60 Hz Rejection
VREF Select™ Allows Absolute and Ratiometric
Measurement Capability
Operation Can Be Optimized for
Analog Performance (CHOP = 0) or
Channel Throughput (CHOP = 1)
INTERFACE
3-Wire Serial
SPITM, QSPITM, MICROWIRETM, and DSP-Compatible
Schmitt Trigger on SCLK
POWER
Specified for Single 3 V and 5 V Operation
Normal: 1.28 mA Typ @ 3 V
Power-Down: 30 �A (32 kHz Crystal Running)
On-Chip Functions
Rail-to-Rail Input Buffer and PGA
2-Bit Digital I/O Port
APPLICATIONS
Industrial Process Control
Instrumentation
Pressure Transducers
Portable Instrumentation
Smart TransmittersSPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
VREF Select is a trademark of Analog Devices, Inc.
GENERAL DESCRIPTIONThe AD7708/AD7718 are complete analog front-ends for low
frequency measurement applications. The AD7718 contains a
24-bit Σ-∆ ADC with PGA and can be configured as 4/5 fully-
differential input channels or 8/10 pseudo-differential input
channels. Two pins on the device are configurable as analog
inputs or reference inputs. The AD7708 is a 16-bit version of
the AD7718. Input signal ranges from 20 mV to 2.56V can be
directly converted using these ADCs. Signals can be converted
directly from a transducer without the need for signal conditioning.
The device operates from a 32 kHz crystal with an on-board PLL
generating the required internal operating frequency. The output
data rate from the part is software programmable. The peak-to-
peak resolution from the part varies with the programmed gain
and output data rate.
The part operates from a single 3 V or 5 V supply. When operating
from 3 V supplies, the power dissipation for the part is 3.84 mW typ.
Both parts are pin-for-pin compatible allowing an upgradable
path from 16 to 24 bits without the need for hardware modifica-
tions. The AD7708/AD7718 are housed in 28-lead SOIC and
TSSOP packages.
AD7708/AD7718FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .1
AD7718 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . .3
AD7708 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . .6
TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . .9
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . .10
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . .12
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . .13
ADC CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . .15
Signal Chain Overview (CHOP Enabled, CHOP = 0) . . .15
ADC NOISE PERFORMANCE CHOP ENABLED
(CHOP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Signal Chain Overview (CHOP Disabled CHOP = 1) . . .19
ADC NOISE PERFORMANCE CHOP DISABLED
(CHOP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Communications Register . . . . . . . . . . . . . . . . . . . . . . . . . .25
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Operating Characteristics when Addressing the
Mode and Control Registers . . . . . . . . . . . . . . . . . . . . . . .28
ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
I/O Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
ADC Data Result Register . . . . . . . . . . . . . . . . . . . . . . . . . .30
Unipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Bipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
ADC Offset Calibration Coefficient Registers . . . . . . . . . . .31
ADC Gain Calibration Coefficient Register . . . . . . . . . . . . .31
ID Register (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
User Nonprogrammable Test Registers . . . . . . . . . . . . . . . .31
Configuring the AD7708/AD7718 . . . . . . . . . . . . . . . . . . . .32
DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MICROCOMPUTER/MICROPROCESSOR
INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
AD7708/AD7718 to 68HC11 Interface . . . . . . . . . . . . . . . .34
AD7708/AD7718-to-8051 Interface . . . . . . . . . . . . . . . . . .35
AD7708/AD7718-to-ADSP-2103/ADSP-2105 Interface . . .36
BASIC CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . .36
Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Single-Ended Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Chop Mode of Operation (CHOP = 0) . . . . . . . . . . . . . . . .37
Nonchop Mode of Operation (CHOP = 1) . . . . . . . . . . . . .38
Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . .38
Bipolar/Unipolar Configuration . . . . . . . . . . . . . . . . . . . . . .38
Data Output Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Data Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Programmable Logic Controllers . . . . . . . . . . . . . . . . . . . . .41
Converting Single-Ended Inputs. . . . . . . . . . . . . . . . . . . . .42
Combined Ratiometric and Absolute Value
Measurement System . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Optimizing Throughput while Maximizing 50 Hz
and 60 Hz Rejection in a Multiplexed Data
Acquisition System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .44
TABLE OF CONTENTS
AD7708/AD7718
AD7718 SPECIFICATIONS1
(AVDD = 2.7 V to 3.6V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6V or 4.75 V to 5.25 V,
REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications TMIN to
TMAX unless otherwise noted.)
AD7718–SPECIFICATIONS1(AVDD = 2.7 V to 3.6V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6V or 4.75 V to 5.25 V, REFIN(+) =
2.5 V ; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications TMIN to TMAX unless otherwise noted.)ANALOG INPUTS
AD7708/AD7718NOTES
1Temperature range is –40°C to +85°C.
2Not production tested, guaranteed by design and/or characterization data at release.
3Following a self-calibration this error will be in the order of the noise for the programmed gain and update selected. A system calibration will completely remove this error.
4Recalibration at any temperature will remove these errors.
5I/O Port Logic Levels are with respect to AVDD and AGND.
Specifications are subject to change without notice.
AD7708/AD7718
AD7708 SPECIFICATIONS1
(AVDD = 2.7 V to 3.6V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6V or 4.75 V to 5.25 V,
REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffers Enabled. All specifications TMIN to
TMAX unless otherwise noted.)
AD7708/AD7718ANALOG INPUTS
NOTESTemperature range is –40°C to +85°C.Not production tested, guaranteed by design and/or characterization data at release.Following a self-calibration this error will be in the order of the noise for the programmed gain and update selected. A system calibration will completely
remove this error.Recalibration at any temperature will remove these errors.I/O Port Logic Levels are with respect to AVDD and AGND.
TIMING CHARACTERISTICS1, 2
(AVDD = 2.7 V to 3.6V or AVDD = 5 V � 5%; DVDD = 2.7 V to 3.6V or DVDD = 5 V � 5%; AGND =
DGND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.NOTESSample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage
level of 1.6V.See Figures 1 and 2.SCLK active edge is falling edge of SCLK.These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.These numbers are derived from the measured time taken by the data output to change 0.5V when loaded with the load circuit of Figure 1. The measured number is
then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true
bus relinquish times of the part and as such are independent of external bus loading capacitances.RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should
be taken that subsequent reads do not occur close to the next output update.
Specifications subject to change without notice.
Figure 1.Load Circuit for Timing Characterization
AD7708/AD7718
ABSOLUTE MAXIMUM RATINGS*(TA = 25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . –0.05 V to +0.05 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +5 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD +0.3 V
Reference Input Voltage to AGND . . –0.3 V to AVDD +0.3 V
Total AIN/REFIN Current (Indefinite) . . . . . . . . . . . . 30 mA
Digital Input Voltage to DGND . . . . –0.3 V to DVDD +0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD +0.3 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
SOIC Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . 71.4°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 23°C/W
TSSOP Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . 97.9°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . .14°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7708/AD7718 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Figure 2.Write Cycle Timing Diagram
Figure 3.Read Cycle Timing Diagram
AD7708/AD7718
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
AD7708/AD7718TPC 1.AD7718 Typical Noise Plot on ±20 mV Input Range
with 19.79 Hz Update Rate
TPC 2.AD7718 Noise Distribution Histogram
TPC 3.RMS Noise vs. Reference Input
(AD7718 andAD7708)
TPC 4.AD7718 No-Missing Codes Performance
TPC 5.AD7708 Typical Noise Plot on ±20 mV Input Range
TPC 6.AD7708 Noise Histogram
–Typical Performance Characteristics
ADC CIRCUIT INFORMATIONThe AD7708/AD7718 incorporates a 10-channel multiplexer
with a sigma-delta ADC, on-chip programmable gain amplifier
and digital filtering intended for the measurement of wide
dynamic range, low frequency signals such as those in weigh-scale,
strain-gauge, pressure transducer, or temperature measurement
applications. The AD7708 offers 16-bit resolution while the
AD7718 offers 24-bit resolution. The AD7718 is a pin-for-pin
compatible version of the AD7708. The AD7718 offers a direct
upgradable path from a 16-bit to a 24-bit system without requiring
any hardware changes and only minimal software changes.
These parts can be configured as four/five fully-differential
input channels or as eight/ten pseudo-differential input chan-
nels referenced to AINCOM. The channel is buffered and can
be programmed for one of eight input ranges from ±20 mV to
±2.56V. Buffering the input channel means that the part can
handle significant source impedances on the analog input and
that R, C filtering (for noise rejection or RFI reduction) can be
placed on the analog inputs if required. These input channels
are intended to convert signals directly from sensors without the
need for external signal conditioning.
The ADC employs a sigma-delta conversion technique to realize
up to 24 bits of no missing codes performance. The sigma-delta
modulator converts the sampled input signal into a digital pulse
train whose duty cycle contains the digital information. A Sinc3
programmable low-pass filter is then employed to decimate the
modulator output data stream to give a valid data conversion result
at programmable output rates. The signal chain has two modes
of operation, CHOP enabled and CHOP disabled. The CHOP bit
in the mode register enables and disables the chopping scheme.
Signal Chain Overview (CHOP Enabled, CHOP = 0)With CHOP = 0, chopping is enabled, this is the default and gives
optimum performance in terms of drift performance. With chopping
enabled, the available output rates vary from 5.35Hz (186.77 ms)
to 105.03 Hz (9.52 ms).A block diagram of the ADC input
channel with chop enabled is shown in Figure 4.
The sampling frequency of the modulator loop is many times
higher than the bandwidth of the input signal. The integrator in
the modulator shapes the quantization noise (which results from
the analog-to-digital conversion) so that the noise is pushed
toward one-half of the modulator frequency. The output of the
sigma-delta modulator feeds directly into the digital filter. The
digital filter then band-limits the response to a frequency signifi-
cantly lower than one-half of the modulator frequency. In this
manner, the 1-bit output of the comparator is translated into a
band limited, low noise output from the AD7708/AD7718 ADC.
The AD7708/AD7718 filter is a low-pass, Sinc3 or (sinx/x)3
filter whose primary function is to remove the quantization noise
introduced at the modulator. The cutoff frequency and deci-
mated output data rate of the filter are programmable via the SF
word loaded to the filter register. The complete signal chain is
chopped resulting in excellent dc offset and offset drift specifica-
tions and is extremely beneficial in applications where drift, noise
rejection, and optimum EMI rejection are important factors.
With chopping, the ADC repeatedly reverses its inputs. The
decimated digital output words from the Sinc3 filters, therefore,
have a positive offset and negative offset term included. As a
result, a final summing stage is included so that each output
word from the filter is summed and averaged with the previous
filter output to produce a new valid output result to be written
to the ADC data register. The programming of the Sinc3 deci-
mation factor is restricted to an 8-bit register SF, the actual
decimation factor is the register value times 8. The decimated
output rate from the Sinc3 filter (and the ADC conversion rate)
will therefore be
where
fADC in the ADC conversion rate.
SF is the decimal equivalent of the word loaded to the filter
register.
fMOD is the modulator sampling rate of 32.768 kHz.
The chop rate of the channel is half the output data rate:
As shown in the block diagram, the Sinc3 filter outputs alter-
nately contain +VOS and –VOS, where VOS is the respective
channel offset. This offset is removed by performing a running
average of two. This average by two means that the settling time
to any change in programming of the ADC will be twice the
normal conversion time, while an asynchronous step change on
the analog input will not be fully reflected until the third subse-
quent output.
The allowable range for SF is 13 to 255 with a default of 69
(45H). The corresponding conversion rates, conversion times,
and settling times are shown in Table I. Note that the conver-
sion time increases by 0.732 ms for each increment in SF.
SINC 3 FILTERANALOG
INPUT
DIGITAL
OUTPUT
fCHOPfINfMODfCHOPfADC
AD7708/AD7718
Table I.ADC Conversion and Settling Times for Various
SF Words with CHOP = 069 (Default)
The overall frequency response is the product of a sinc3 and a
sinc response. There are sinc3 notches at integer multiples of
3 × fADC and there are sinc notches at odd integer multiples
of fADC/2. The 3 dB frequency for all values of SF obeys the
following equation:
f (3 dB) = 0.24 × fADC
Normal-mode rejection is the major function of the digital filter
on the AD7708/AD7718. The normal mode 50 ±1 Hz rejection
with an SF word of 82 is typically –100dB. The 60 ± 1 Hz
rejection with SF = 68 is typically –100dB. Simultaneous 50 Hz
and 60 Hz rejection of better than 60dB is achieved with an SF
of 69. Choosing an SF word of 69 places notches at both 50 Hz
and 60 Hz. Figures 5 to 9 show the filter rejection for a selection
of SF words.
The frequency response of the filter H (f) is as follows:
where
fMOD = 32,768 Hz,
SF = value programmed into SF Register,
fOUT = fMOD/(SF × 8 × 3).
The following plots show the filter frequency response for a
variety of update rates from 5Hz to 105Hz.
Figure 5.Filter Profile with SF = 13
Figure 6.Filter Profile with SF = 82
Figure 7.Filter Profile with SF = 255
Figure 8.Filter Profile with Default SF = 69 Giving Filter
Notches at Both 50 Hz and 60 Hz
Figure 9.Filter Profile with SF = 68
ADC NOISE PERFORMANCE CHOP ENABLED
(CHOP = 0)Tables II to V show the output rms noise and output peak-to-
peak resolution in bits (rounded to the nearest 0.5 LSB) for a
selection of output update rates. The numbers are typical and
generated at a differential input voltage of 0 V with AVDD =
DVDD = 5 V and using a 2.5 V reference. The output update
rate is selected via the SF7–SF0 bits in the Filter Register. It is
important to note that the peak-to-peak resolution figures repre-
sent the resolution for which there will be no code flicker within
a six-sigma limit. The output noise comes from two sources. The
first is the electrical noise in the semiconductor devices (device
noise) used in the implementation of the modulator. Secondly,
when the analog input is converted into the digital domain,
quantization noise is added. The device noise is at a low level
and is independent of frequency. The quantization noise starts at
an even lower level but rises rapidly with increasing frequency to
become the dominant noise source. The numbers in the tables
are given for the bipolar input ranges. For the unipolar ranges
the rms noise numbers will be the same as the bipolar range, but
the peak-to-peak resolution is now based on half the signal range
which effectively means losing one bit of resolution.
AD7708/AD7718
Table II.Typical Output RMS Noise vs. Input Range and Update Rate for AD7718 with Chop Enabled (CHOP = 0);
Output RMS Noise in �V
Table III.Peak-to-Peak Resolution vs. Input Range and Update Rate for AD7718 with Chop Enabled (CHOP = 0);
Peak-to-Peak Resolution in Bits
Table IV.Typical Output RMS Noise vs. Input Range and Update Rate for AD7708 with Chop Enabled (CHOP = 0);
Output RMS Noise in �V
Table V.Peak-to-Peak Resolution vs. Input Range and Update Rate for AD7708 with Chop Enabled (CHOP = 0);
Peak-to-Peak Resolution in BitsSIGNAL CHAIN OVERVIEW CHOP DISABLED
(CHOP = 1)With CHOP =1 chopping is disabled. With chopping disabled
the available output rates vary from 16.06 Hz (62.26ms) to
1365.33 Hz (0.73 ms). The range of applicable SF words is from
3 to 255. When switching between channels with chop disabled,
the channel throughput is increased by a factor of two over the
case where chop is enabled. When used in multiplexed applica-
tions operation with chop disabled will offer the best throughput
time when cycling through all channels. The drawback with
chop disabled is that the drift performance is degraded and
calibration is required following a gain change or significant
temperature change. A block diagram of the ADC input
channel with chop disabled is shown in Figure 10. The
signal chain includes a mux, buffer, PGA, sigma-delta modu-
lator, and digital filter. The modulator bit stream is applied to
a Sinc3 filter. The programming of the Sinc3 decimation
factor is restricted to an 8-bit register SF, the actual decima-
tion factor is the register value times 8. The decimated output
rate from the Sinc3 filter (and the ADC conversion rate) will there-
fore be:
where
fADC is the ADC conversion rate,
SF is the decimal equivalent of the word loaded to the filter
register, valid range is from 3 to 255,
fMOD is the modulator sampling rate of 32.768 kHz.
The settling time to a step input is governed by the digital filter.
A synchronized step change will require a settling time of three
times the programmed update rate, a channel change can be
treated as a synchronized step change. An unsynchronized step
change will require four outputs to reflect the new analog input
at its output.
The allowable range for SF is 3 to 255 with a default of 69
(45H). The corresponding conversion rates, conversion times,
and settling times are shown in Table VI. Note that the conver-
sion time increases by 0.245 ms for each increment in SF.
Table VI.ADC Conversion and Settling Times for Various
SF Words with CHOP = 1The frequency response of the digital filter H (f) is as follows:
where
fMOD = 32,768 Hz,
SF = value programmed into SF SFR.
The following shows plots of the filter frequency response using
different SF words for output data rates of 16 Hz to 1.36 kHz.
There are sinc3 notches at integer multiples of the update rate.
The 3 dB frequency for all values of SF obeys the following
equation:
f (3 dB) = 0.262 × fADC
The following plots show frequency response of the AD7708/
AD7718 digital filter for various filter words. The AD7708/
AD7718 are targeted at multiplexed applications. One of the
key requirements in these applications is to optimize the SF
word to obtain the maximum filter rejection at 50 Hz and 60 Hz
while minimizing the channel throughput rate. Figure 12 shows
the AD7708/AD7718 optimized throughput while maximizing
50 Hz and 60 Hz rejection. This is achieved with an SF word of
75. In Figure 13, by using a higher SF word of 151, 50 Hz and
60 Hz rejection can be maximized at 60dB with a channel
throughput rate of 110 ms. An SF word of 255 gives maximum
rejection at both 50 Hz and 60 Hz but the channel throughput
rate is restricted to 186ms as shown in Figure 14.
Figure 10.ADC Channel Block Diagram with CHOP Disabled
AD7708/AD7718Figure 11.Frequency Response Operating with the
SF Word of 68
Figure 12.Optimizing Filter Response for Throughput
while Maximizing the Simultaneous 50 Hz and 60 Hz
Rejection
Figure 13.Optimizing Filter Response for Maximum
Simultaneous 50 Hz and 60 Hz Rejection
Figure 14.Frequency with Maximum SF Word = 255
ADC NOISE PERFORMANCE CHOP DISABLED
(CHOP = 1)Tables VII to X show the output rms noise and output peak-to-
peak resolution in bits (rounded to the nearest 0.5 LSB) for
some typical output update rates. The numbers are typical and
generated at a differential input voltage of 0 V. The output update
rate is selected via the SF7–SF0 bits in the Filter Register. It is
important to note that the peak-to-peak resolution figures represent
the resolution for which there will be no code flicker within a
six-sigma limit. The output noise comes from two sources. The
when the analog input is converted into the digital domain,
quantization noise is added. The device noise is at a low level
and is independent of frequency. The quantization noise starts
at an even lower level but rises rapidly with increasing frequency
to become the dominant noise source. The numbers in the
tables are given for the bipolar input ranges. For the unipolar
ranges the rms noise numbers will be the same as the bipolar
range, but the peak-to-peak resolution is now based on half the
Table VII.Typical Output RMS Noise vs. Input Range and Update Rate for AD7718 with Chop Disabled (CHOP = 1);
Output RMS Noise in �V
Table VIII.Peak-to-Peak Resolution vs. Input Range and Update Rate for AD7718 with Chop Disabled (CHOP = 1);
Peak-to-Peak Resolution in Bits
Table IX.Typical Output RMS Noise vs. Input Range and Update Rate for AD7708 with Chop Disabled (CHOP = 1);
Output RMS Noise in �V
Table X.Peak-to-Peak Resolution vs. Input Range and Update Rate for AD7708 with Chop Disabled (CHOP = 1);
Peak-to-Peak Resolution in Bits
AD7708/AD7718
ON-CHIP REGISTERSThe AD7708 and AD7718 are controlled and configured via
a number of on-chip registers which are shown in Figure 15.
The first of these registers is the communications register
which is used to control all operations on these converters. All
communications with these parts must start with a write to
the communications register to specify the next operation to
be performed. After a power-on or RESET, the device defaults
to waiting for a write to the communications register. The
STATUS register contains information pertaining to the operat-
ing conditions of the converter. The STATUS register is a read
only register. The MODE register is used to configure the con-
version mode, calibration, chop enable/disable, reference select,
channel configuration and buffered or unbuffered operation on
the AINCOM analog input. The MODE register is a read/write
register. The ADC Control register is a read/write register used
to select the active channel and program its input range and
bipolar/unipolar operation. The I/O control register is a read/
write register used to configure the operation of the 2-pin I/O
port. The filter register is a read/write register used to program
the data update rate of the converter. The ADC Data register is
a read only register that contains the result of a data conversion
on the selected channel. The ADC offset registers are read/write
registers that contain the offset calibration data. There are five
offset registers, one for each of the fully differential input channels.
When configured for pseudo-differential input mode the chan-
nels share offset registers. The ADC gain registers are read/write
registers that contain the gain calibration data. There are five
ADC gain registers, one for each of the fully differential input
channels. When configured for pseudo differential input mode
the channels share gain registers. The ADC contains Test registers
for factory use only, the user is advised not to alter the oper-
ating conditions of these registers. The ID register is a read only
register and is used for silicon identification purposes. The follow-
ing sections contains more in-depth detail on all of these registers.
In the following descriptions, SET implies a Logic 1 state and
CLEARED implies a Logic 0 state unless otherwise stated.
Figure 15.On-Chip Registers
