AD7707BR ,3 V/5 V, +-10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADCfeatures two low level pseudo- PRODUCT HIGHLIGHTSdifferential analog input channels, one high level ..
AD7707BRU ,3 V/5 V, +-10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADCspecifications T to T unless otherwise noted.)MIN MAX1Parameter B Version Units Conditions/Comments ..
AD7708BR ,8-/10-Channel, Low Voltage, Low Power, ADCsAPPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41ADC Control Register ..
AD7708BRU ,8-/10-Channel, Low Voltage, Low Power, ADCsapplications. The AD7718 contains aAD7718 Has 24-Bit Resolution 24-bit Σ-∆ ADC with PGA and can be ..
AD7709ARU ,16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O Portapplications. It contains a 16-bit - ADC, selectable16-Bit p-p Resolution @ 20 Hz, 2.56 V Rangere ..
AD7709BRU ,16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O PortAPPLICATIONSFUNCTIONAL BLOCK DIAGRAMIndustrial Process ControlInstrumentationREFIN2(+) REFIN1(+) RE ..
ADM1027ARQ-REEL7 ,Complete Systems Monitor and Multiple Fan Controller™dBCOOL Remote ThermalController and Voltage Monitor*ADM1027
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ADM1028ARQ ,Remote Thermal Diode Monitor with Linear Fan ControlSPECIFICATIONS (T = T to T , V = V to V , unless otherwise noted.)A MIN MAX CC MIN MAXParameter Min ..
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ADM1028ARQ-REEL ,Remote Thermal Diode and Linear Fan ControlCHARACTERISTICSPositive Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . 6.5 VCC 16-Le ..
AD7707BR-AD7707BRU
3 V/5 V, +-10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC
REV. A
3 V/5 V, 610 V Input Range, 1 mW
3-Channel 16-Bit, Sigma-Delta ADC
FUNCTIONAL BLOCK DIAGRAM
AVDDREF IN(–)REF IN(+)
AD7707
CHARGE
BALANCING
A/D CONVERTERA = 1<128
SERIAL INTERFACE
REGISTER BANKMCLK OUT
MCLK IN
AGNDDRDYRESET
AIN1
AIN2
LOCOM
AIN3
VBIAS
HICOM
DIN
DOUT
SCLK
DGND
30kV
5kV
15kV
30kV
5kV
DVDD
FEATURES
Charge Balancing ADC
16 Bits No Missing Codes
0.003% Nonlinearity
High Level (610 V) and Low Level (610 mV) Input
Channels
True Bipolar 6100 mV Capability on Low Level Input
Channels Without Requiring Charge Pumps
Programmable Gain Front End
Gains from 1 to 128
Three-Wire Serial Interface
SPI™, QSPI™, MICROWIRE™ and DSP Compatible
Schmitt Trigger Input on SCLK
Ability to Buffer the Analog Input
2.7 V to 3.3 V or 4.75 V to 5.25 V Operation
Power Dissipation 1 mW max @ 3␣V
Standby Current 8 mA max
20-Lead SOIC and TSSOP Packages
GENERAL DESCRIPTIONThe AD7707 is a complete analog front end for low frequency
measurement applications. This three-channel device can accept
either low level input signals directly from a transducer or high
level (–10 V) signals and produce a serial digital output. It
employs a sigma-delta conversion technique to realize up tobits of no missing codes performance. The selected input
signal is applied to a proprietary programmable gain front end
based around an analog modulator. The modulator output is
processed by an on-chip digital filter. The first notch of this
digital filter can be programmed via an on-chip control register
allowing adjustment of the filter cutoff and output update rate.
The AD7707 operates from a single 2.7 V to 3.3 V or 4.75 V to
5.25 V supply. The AD7707 features two low level pseudo-
differential analog input channels, one high level input channel
and a differential reference input. Input signal ranges of 0mV to
+20mV through 0V to +2.5V can be accommodated on both
low level input channels when operating with a VDD of 5 V and a
reference of 2.5 V. They can also handle bipolar input signal
ranges of –20mV through –2.5V, which are referenced to the
LCOM input. The AD7707, with a 3V supply and a 1.225V
reference, can handle unipolar input signal ranges of 0mV to
+10mV through 0V to +1.225V. Its bipolar input signal ranges
are –10mV through –1.225V.
The high level input channel can accept input signal ranges of10V, –5V, 0V to +10V and 0V to +5V. The AD7707 thus
performs all signal conditioning and conversion for a three-
channel system.
The AD7707 is ideal for use in smart, microcontroller or DSP-
based systems. It features a serial interface that can be config-
ured for three-wire operation. Gain settings, signal polarity and
update rate selection can be configured in software using the
input serial port. The part contains self-calibration and system
calibration options to eliminate gain and offset errors on the
part itself or in the system.
CMOS construction ensures very low power dissipation, and the
power-down mode reduces the standby power consumption to
20␣mW typ. These parts are available in a 20-lead wide body
(0.3inch) small outline (SOIC) package and a low profile 20-lead
TSSOP.
PRODUCT HIGHLIGHTSThe AD7707 consumes less than 1 mW at 3 V supplies andMHz master clock, making it ideal for use in low power
systems. Standby current is less than 8␣mA.On-chip thin-film resistors allow –10V, –5V, 0V to +10V
and 0V to +5V high level input signals to be directly accom-
modated on the analog inputs without requiring split supplies
or charge-pumps.The low level input channels allow the AD7707 to accept
input signals directly from a strain gage or transducer remov-
ing a considerable amount of signal conditioning.The part features excellent static performance specifications
with 16 bits, no missing codes, –0.003% accuracy and low
rms noise. Endpoint errors and the effects of temperature
drift are eliminated by on-chip calibration options, which
remove zero-scale and full-scale errors.SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
AD7707–SPECIFICATIONSSTATIC PERFORMANCE
Low Level Input Channels (AIN1 and AIN2)
LOW LEVEL ANALOG INPUTS/REFERENCE INPUTS
(AVDD = DVDD = +3 V or 5 V, REF IN(+) = +1.225␣V with AVDD = 3 V and +2.5 V with AVDD
= 5 V; REF␣IN(–) = GND; VBIAS = REFIN(+); MCLK IN = 2.4576␣MHz unless otherwise
noted. All specifications TMIN to TMAX unless otherwise noted.)
AD7707HIGH LEVEL ANALOG INPUT CHANNEL (AIN3)
LOGIC INPUTS
LOGIC OUTPUTS (Including MCLK OUT)
SYSTEM CALIBRATION
AD7707–SPECIFICATIONSNOTESTemperature range as follows: B Version, –40°C to +85°C.These numbers are established from characterization or design at initial product release.A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I and III for the low level input channels AIN1
and AIN2. This applies after calibration at the temperature of interest.Recalibration at any temperature will remove these drift errors.Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges.Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.Gain error does not include zero-scale errors. It is calculated as full-scale error–unipolar offset error for unipolar ranges and full-scale error–bipolar zero error for
bipolar ranges.Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if zero scale calibrations only were performed.Error is removed following a system calibration.This common-mode voltage range is allowed provided that the input voltage on analog inputs does not go more positive than AVDD + 30 mV or go more negative
than AGND – 100␣mV. Parts are functional with voltages down to AGND – 200 mV, but with increased leakage at high temperature.The analog input voltage range on AIN(+) is given here with respect to the voltage on LCOM on the low level input channels (AIN1 and AIN2) and is given with
respect to the HCOM input on the high level input channel AIN3. The absolute voltage on the low level analog inputs should not go more positive than AVDD +
100␣mV, or go more negative than GND␣– 100␣mV for specified performance. Input voltages of AGND – 200 mV can be accommodated, but with increased leakage
at high temperature.VREF = REF IN(+) – REF IN(–).These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.Sample tested at +25°C to ensure compliance.After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will
output all 0s.These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AVDD + 30␣mV or go more negative than AGND –
30␣mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation will vary depending on
the crystal or resonator type (see Clocking and Oscillator Circuit section).If the external master clock continues to run in standby mode, the standby current increases to 150␣mA typical at 5 V and 75 mA at 3 V. When using a crystal or
ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation
depends on the crystal or resonator type (see Standby Mode section).Measured at dc and applies in the selected passband. PSRR at 50␣Hz will exceed 120␣dB with filter notches of 25 Hz or 50␣Hz. PSRR at 60␣Hz will exceed 120␣dB
with filter notches of 20 Hz or 60␣Hz.PSRR depends on both gain and AVDD.
Low Level Input Channels, AIN1 and AIN2High Level Input Channel, AIN3
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2tCLKIN LO
Read Operation
NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.See Figures 16 and 17.fCLKIN Duty Cycle range is 45% to 55%. fCLKIN must be supplied whenever the AD7707 is not in Standby mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.The AD7707 is production tested with fCLKIN at 2.4576␣MHz (1␣MHz for some IDD tests). It is guaranteed by characterization to operate at 400␣kHz.These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.These numbers are derived from the measured time taken by the data output to change 0.5␣V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high, although care
should be taken that subsequent reads do not occur close to the next output update.
TO OUTPUT
PIN
+1.6VFigure 1.Load Circuit for Access Time and Bus Relinquish Time
(AVDD = DVDD = +2.7 V TO +5.25 V, AGND = DGND = 0 V; fCLKIN = 2.4576 MHz; Input
Logic = 0, Logic 1 = DVDD unless otherwise noted.)
AD7707
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7707 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3␣V to +7␣V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3␣V to +7␣V
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3␣V to +7␣V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3␣V to +7␣V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣V to +7 V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . –0.3␣V to +0.3␣V
AIN1, AIN2 Input Voltage to
LOCOM . . . . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3␣V
AIN3 Input Voltage to HICOM . . . . . . . . . . . –11 V to +30␣V
VBIAS to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3␣V
HICOM, LOCOM to AGND . . . . . . –0.3 V to AVDD + 0.3␣V
REF(+), REF(–) to AGND . . . . . . . . –0.3 V to AVDD + 0.3␣V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 139°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
␣␣␣␣Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
AIN3
AIN2
LOCOM
MCLK IN
MCLK OUT
AIN1
AVDD
RESET
HICOM
VBIAS
REF IN(+)
DVDD
DIN
DOUT
REF IN(–)
AGND
DRDY
SCLKDGND
AD7707
OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (5 V OPERATION)Table I shows the AD7707 output rms noise and peak-to-peak resolution in unbuffered mode for the selectable notch and –3␣dB
frequencies for the part, as selected by FS0, FS1 and FS2 of the Clock Register. The numbers given are for the bipolar input ranges
with a VREF of +2.5␣V and AVDD = 5 V. These numbers are typical and are generated at an analog input voltage of 0V. Table II
shows the rms noise and peak-to-peak resolution when operating in unbuffered mode. It is important to note that the peak-to-peak num-
bers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak noise. The
numbers given are for bipolar input ranges with a VREF of +2.5 V. These numbers are typical and are rounded to the nearest LSB.
The numbers apply for the CLK DIV bit of the Clock Register set to 0. The output noise comes from two sources. The first is the
electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the analog
input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independent of fre-
quency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise
source. The numbers in the tables are given for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be the
same as the bipolar range but the peak-to-peak resolution is now based on half the signal range which effectively means losing 1 bit of
resolution.
Table I.Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +5 V
AIN1 and AIN2 Unbuffered Mode Only
MCLK IN = 1 MHz
Table II.Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +5 V
AIN1 and AIN2 Buffered Mode Only
OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (3 V OPERATION)Table III shows the AD7707 output rms noise and peak-to-peak resolution in unbuffered mode for the selectable notch and –3␣dB
frequencies for the part, as selected by FS0, FS1 and FS2 of the Clock Register. The numbers given are for the bipolar input ranges
with a VREF of +1.225␣V and an AVDD = 3 V. These numbers are typical and are generated at an analog input voltage of 0V. Table
IV shows the rms noise and peak-to-peak resolution when operating in unbuffered mode. It is important to note that the peak-to-peak
numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak noise.
The numbers given are for bipolar input ranges with a VREF of +1.225 V and for either buffered or unbuffered mode. These numbers
are typical and are rounded to the nearest LSB. The numbers apply for the CLK DIV bit of the Clock Register set to 0. The first is
the electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the
analog input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independent of
frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant
noise source. The numbers in the tables are given for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be
the same as the bipolar range but the peak-to-peak resolution is now based on half the signal range which effectively means losingbit of resolution.
Table III.Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +3V
AIN1 and AIN2 Unbuffered Mode Only
AD7707
Table IV.Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +3V
AIN1 and AIN2 Buffered Mode Only
OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (5 V OPERATION)Table V shows the AD7707 output rms noise and peak-to-peak resolution in unbuffered for the selectable notch and –3␣dB
frequencies for the part, as selected by FS0, FS1 and FS2 of the Clock Register. The numbers given are for the –10V,5V, 0 to 5V and 0V to +10V ranges with a VREF of +2.5V, HBIAS = 2.5V, HICOM = AGND and AVDD = 5 V. These
numbers are typical and are generated at an analog input voltage of 0V. Table VI meanwhile shows the output rms noise and
peak-to-peak resolution in buffered mode. It is important to note that these numbers represent the resolution for which there will be
no code flicker. They are not calculated based on rms noise but on peak-to-peak noise. Operating the high level channel with a gain
of 2 in bipolar mode gives an operating range of –10V. Operating at a gain of 2 in unipolar mode gives a range of 0 V to
+10V. Operating the high level channel with a gain of 4 in bipolar mode gives the –5V operating range. Operating at a gain
of 4 in unipolar mode gives an operating range of 0 V to +5V. Noise for all input ranges is shown in Appendix 1. The out-
put noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise) used in the
implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization noise
is added. The device noise is at a low level and is independent of frequency. The quantization noise starts at an even lower
level but rises rapidly with increasing frequency to become the dominant noise source. The numbers in the tables are given
for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be the same as the bipolar range but the
peak-to-peak resolution is now based on half the signal range which effectively means losing 1 bit of resolution.
Table V.Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +5 V
AIN3 Unbuffered Mode Only
Table VI.Output RMS Noise/ Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +5 V
AIN3 Buffered Mode Only
OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (5 V OPERATION)Table VII shows the AD7707 output rms noise and peak-to-peak resolution for the selectable notch and –3␣dB frequencies for the
part, as selected by FS0, FS1 and FS2 of the Clock Register. The numbers given are for the –5V, 0V to +5V and 0V to +10V
ranges with a VREF of +1.225V, HBIAS = 1.225V, HICOM = AGND and AVDD = 3 V. These numbers are typical and are gener-
ated at an analog input voltage of 0V for unbuffered mode of operation. The above operating ranges are only achievable in unbuf-
fered mode when operating at 3V due to common-mode limitations on the input amplifier. It is important to note that these numbers
represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak noise. Operating
at a gain of 1 in unipolar mode provides a range of 0V to +10V. Operating the high level channel with a gain of 2 in bipolar mode
provides a –5V operating range. Operating at a gain of 2 in unipolar mode provides an operating range of 0V to +5V. The output
noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise) used in the implementation
of the modulator. Secondly, when the analog input is converted into the digital domain, quantization noise is added. The device
noise is at a low level and is independent of frequency. The quantization noise starts at an even lower level but rises rapidly with
increasing frequency to become the dominant noise source. The numbers in the tables are given for the bipolar input ranges. For the
unipolar ranges the rms noise numbers will be the same as the bipolar range but the peak-to-peak resolution is now based on half the
signal range which effectively means losing 1 bit of resolution.
Table VII.Output RMS Noise/ Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +3 V
AIN3 Unbuffered Mode Only
AD7707
READING NO.
CODE READ
2003004005006007008009001000Figure 2.Typical Noise Plot @ Gain = 128 with 50 Hz
Update Rate for Low Level Input Channel
READING NO.
CODE
2004006008001000Figure 3.Typical Noise Plot for AIN3, High Level Input
Channel
AIN3 – Volts
RMS NOISE – –22610Figure 4.Typical RMS Noise vs. Analog Input Voltage for
CODE
OCCURRENCE
100Figure 5.Histogram of Data in Figure 2
CODE
OCCURRENCE
3276732768Figure 6.Histogram of Data in Figure 3
INPUT VOLTAGE – mV
RMS NOISE –
0.1Figure 7.Typical RMS Noise vs. Analog Input Voltage for
Figure 9.Standby Current vs. Temperature
ON-CHIP REGISTERSThe AD7707 contains eight on-chip registers which can be accessed via the serial port of the part. The first of these is a Communica-
tions Register that controls the channel selection, decides whether the next operation is a read or write operation and also decides
which register the next read or write operation accesses. All communications to the part must start with a write operation to the
Communications Register. After power-on or RESET, the device expects a write to its Communications Register. The data written
to this register determines whether the next operation to the part is a read or a write operation and also determines to which register
this read or write operation occurs. Therefore, write access to any of the other registers on the part starts with a write operation to the
Communications Register followed by a write to the selected register. A read operation from any other register on the part (including
the Communications Register itself and the output data register) starts with a write operation to the Communications Register fol-
lowed by a read operation from the selected register. The Communications Register also controls the standby mode and channel
selection and the DRDY status is also available by reading from the Communications Register. The second register is a Setup Regis-
ter that determines calibration mode, gain setting, bipolar/unipolar operation and buffered mode. The third register is labelled the
Clock Register and contains the filter selection bits and clock control bits. The fourth register is the Data Register from which the
output data from the part is accessed. The final registers are the calibration registers which store channel calibration data. The regis-
ters are discussed in more detail in the following sections.
Communications Register (RS2, RS1, RS0 = 0, 0, 0)The Communications Register is an 8-bit register from which data can either be read or to which data can be written. All communi-
cations to the part must start with a write operation to the Communications Register. The data written to the Communications Reg-
ister determines whether the next operation is a read or write operation and to which register this operation takes place. Once the
subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to
the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7707 is in this
default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, if a
write operation of sufficient duration (containing at least 32 serial clock cycles) takes place with DIN high, the AD7707 returns to
this default state. Table VIII outlines the bit designations for the Communications Register.
Table VIII.Communications Register0/DRDYFor a write operation, a “0” must be written to this bit so that the write operation to the Communications Register
actually takes place. If a “1” is written to this bit, the part will not clock on to subsequent bits in the register. It will
stay at this bit location until a “0” is written to this bit. Once a “0” is written to this bit, the next seven bits will be
loaded to the Communications Register. For a read operation, this bit provides the status of the DRDY flag from
the part. The status of this bit is the same as the DRDY output pin.
RS2–RS0Register Selection Bits. These three bits select to which one of eight on-chip registers the next read or write opera-
tion takes place, as shown in Table IX, along with the register size. When the read or write operation to the se-
lected register is complete, the part returns to where it is waiting for a write operation to the Communications
Figure 8.Typical Crystal Oscillator Power-Up Time
AD7707
Table IX.Register SelectionR/WRead/Write Select. This bit selects whether the next operation is a read or write operation to the selected register.
A “0” indicates a write cycle for the next operation to the appropriate register, while a “1” indicates a read opera-
tion from the appropriate register.
STBYStandby. Writing a “1” to this bit puts the part into its standby or power-down mode. In this mode, the part con-
sumes only 8 mA of power supply current. The part retains its calibration coefficients and control word information
when in STANDBY. Writing a “0” to this bit places the part in its normal operating mode. The serial interface on
the AD7707 remains operational when the part is in STBY mode.
CH1–CH0Channel Select. These two bits select a channel for conversion or for access to the calibration coefficients as out-
lined in Table X. Three pairs of calibration registers on the part are used to store the calibration coefficients fol-
lowing a calibration on a channel. They are shown in Tables VII for the AD7707 to indicate which channel
combinations have independent calibration coefficients. With CH1 at Logic 1 and CH0 at a Logic 0, the part looks
at the LOCOM input internally shorted to itself. This can be used as a test method to evaluate the noise perfor-
mance of the part with no external noise sources. In this mode, the LOCOM input should be connected to an
external voltage within the allowable common-mode range for the part.
Table X.Channel Selection for AD7707
Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 01␣HexThe Setup Register is an eight-bit register from which data can either be read or to which data can be written. Table XI outlines the
bit designations for the Setup Register.
Table XI.Setup RegisterG2–G0Gain Selection Bits. These bits select the gain setting for the on-chip PGA as outlined in Table XII.
Table XII.Gain SelectionB/UBipolar/Unipolar Operation. A “0” in this bit selects Bipolar Operation. A “1” in this bit selects Unipolar Operation.
BUFBuffer Control. With this bit at “0,” the on-chip buffer on the analog input is shorted out. With the buffer shorted
out, the current flowing in the VDD line is reduced. When this bit is high, the on-chip buffer is in series with the
analog input allowing the input to handle higher source impedances.
FSYNCFilter Synchronization. When this bit is high, the nodes of the digital filter, the filter control logic and the calibra-
tion control logic are held in a reset state and the analog modulator is also held in its reset state. When this bit goes
low, the modulator and filter start to process data and a valid word is available in 3 · 1/ (output update rate), i.e.,
the settling time of the filter. This FSYNC bit does not affect the digital interface and does not reset the DRDY
output if it is low.
AD7707
Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset Status: 05␣HexThe Clock Register is an 8-bit register from which data can either be read or to which data can be written. Table XIII outlines the bit
designations for the Clock Register.
Table XIII.Clock RegisterZEROZero. A zero MUST be written to these bits to ensure correct operation of the AD7707. Failure to do so may
result in unspecified operation of the device.
CLKDISMaster Clock Disable Bit. A Logic 1 in this bit disables the master clock from appearing at the MCLK OUT pin.
When disabled, the MCLK OUT pin is forced low. This feature allows the user the flexibility of using the MCLK
OUT as a clock source for other devices in the system or of turning off the MCLK OUT as a power saving feature.
When using an external master clock on the MCLK IN pin, the AD7707 continues to have internal clocks and will
convert normally with the CLKDIS bit active. When using a crystal oscillator or ceramic resonator across the
MCLK IN and MCLK OUT pins, the AD7707 clock is stopped and no conversions take place when the CLKDIS
bit is active.
CLKDIVClock Divider Bit. With this bit at a Logic 1, the clock frequency appearing at the MCLK IN pin is divided by two
before being used internally by the AD7707. For example, when this bit is set to 1, the user can operate with a
4.9152 MHz crystal between MCLK IN and MCLK OUT and internally the part will operate with the specified
2.4576 MHz. With this bit at a Logic 0, the clock frequency appearing at the MCLK IN pin is the frequency used
internally by the part.
CLKClock Bit. This bit should be set in accordance with the operating frequency of the AD7707. If the device has a
master clock frequency of 2.4576 MHz (CLKDIV = 0) or 4.9152 MHz (CLKDIV = 1), then this bit should be set
to a “1.” If the device has a master clock frequency of 1 MHz (CLKDIV = 0) or 2 MHz (CLKDIV = 1), this bit
should be set to a “0.” This bit sets up the appropriate scaling currents for a given operating frequency and also
chooses (along with FS2, FS1 and FS0) the output update rate for the device. If this bit is not set correctly for the
master clock frequency of the device, then the AD7707 may not operate to specification.
FS2, FS1, FS0Filter Selection Bits. Along with the CLK bit, FS2, FS1 and FS0 determine the output update rate, filter
first notch and –3 dB frequency as outlined in Table XIV. The on-chip digital filter provides a sinc3 (or
Sinx/x3) filter response. Placing the first notch at 10 Hz places notches at both 50 and 60 Hz giving better
than 150 dB rejection at these frequencies. In association with the gain selection the filter cutoff also deter-
mines the output noise of the device. Changing the filter notch frequency, as well as the selected gain, im-
pacts resolution. Tables I to IV show the effect of filter notch frequency and gain on the output noise and
effective resolution of the part. The output data rate (or effective conversion time) for the device is equal to
the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected
at 50 Hz, a new word is available at a 50 Hz output rate or every 20 ms. If the first notch is at 500 Hz, a
new word is available every 2 ms. A calibration should be initiated when any of these bits are changed.
The settling time of the filter to a full-scale step input is worst case 4 · 1/(output data rate). For example,
with the filter first notch at 50 Hz, the settling time of the filter to a full-scale step input is 80 ms max. If
the first notch is at 500 Hz, the settling time is 8 ms max. This settling time can be reduced to 3 · 1/ (out-
put data rate) by synchronizing the step input change to a reset of the digital filter. In other words, if the step
input takes place with the FSYNC bit high, the settling time will be 3 · 1/(output data rate) from when the
FSYNC bit returns low.
The –3 dB frequency is determined by the programmed first notch frequency according to the relationship:
filter –3 dB frequency = 0.262 · filter first notch frequency
Table XIV.Output Update Rates*Assumes correct clock frequency on MCLK IN pin with CLKDIV bit set appropriately.
Data Register (RS2, RS1, RS0 = 0, 1, 1)The Data Register on the part is a 16-bit read-only register that contains the most up-to-date conversion result from the AD7707. If
the Communications Register sets up the part for a write operation to this register, a write operation must actually take place to re-
turn the part to where it is expecting a write operation to the Communications Register. However, the 16 bits of data written to the
part will be ignored by the AD7707.
Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset Status: 00␣HexThe part contains a Test Register that is used when testing the device. The user is advised not to change the status of any of the bits
in this register from the default (Power-on or RESET) status of all 0s as the part will be placed in one of its test modes and will not
operate correctly.
Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); Power-On/Reset Status: 1F4000␣HexThe AD7707 contains independent sets of zero-scale registers, one for each of the input channels. Each of these registers is a 24-bit
read/write register; 24 bits of data must be written otherwise no data will be transferred to the register. This register is used in con-
junction with its associated full-scale register to form a register pair. These register pairs are associated with input channel pairs as
outlined in Table VII. While the part is set up to allow access to these registers over the digital interface, the part itself no longer has
access to the register coefficients to correctly scale the output data. As a result, there is a possibility that after accessing the calibra-
tion registers (either read or write operation) the first output data read from the part may contain incorrect data. In addition, a write
to the calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by taking the
FSYNC bit in the mode register high before the calibration register operation and taking it low after the operation is complete.
Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1); Power-On/Reset Status: 5761AB␣HexThe AD7707 contains independent sets of full-scale registers, one for each of the input channels. Each of these registers is a 24-bit
read/write register; 24 bits of data must be written otherwise no data will be transferred to the register. This register is used in con-
junction with its associated zero-scale register to form a register pair. These register pairs are associated with input channel pairs as
outlined in Table X. While the part is set up to allow access to these registers over the digital interface, the part itself no longer has
access to the register coefficients to correctly scale the output data. As a result, there is a possibility that after accessing the calibra-
tion registers (either read or write operation) the first output data read from the part may contain incorrect data. In addition, a write
to the calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by taking
FSYNC bit in the mode register high before the calibration register operation and taking it low after the operation is complete.
AD7707
CALIBRATION SEQUENCESThe AD7707 contains a number of calibration options as previously outlined. Table XV summarizes the calibration types, the opera-
tions involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to moni-
tor when DRDY returns low at the end of the sequence. DRDY not only indicates when the sequence is complete, but also that the
part has a valid new sample in its data register. This valid new sample is the result of a normal conversion which follows the calibra-
tion sequence. The second method of determining when calibration is complete is to monitor the MD1 and MD0 bits of the Setup
Register. When these bits return to 0 (0 following a calibration command), it indicates that the calibration sequence is complete.
This method does not give any indication of there being a valid new result in the data register. However, it gives an earlier indication
than DRDY that calibration is complete. The duration to when the Mode Bits (MD1 and MD0) return to 0 00 represents the dura-
tion of the calibration carried out). The sequence to when DRDY goes low also includes a normal conversion and a pipeline delay,
tP, to correctly scale the results of this first conversion. tP will never exceed 2000 · tCLKIN. The time for both methods is given in the
table.
Table XV.Calibration SequencesSelf-Calibration
CIRCUIT DESCRIPTIONThe AD7707 is a sigma-delta A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low frequency signals such as those in industrial control or pro-
cess control applications. It contains a sigma-delta (or charge-
balancing) ADC, a calibration microcontroller with on-chip
static RAM, a clock oscillator, a digital filter and a bidirectional
serial communications port. The part consumes only 320 mA of
power supply current, making it ideal for battery-powered or
loop-powered instruments. On-chip thin-film resistors allow10V, –5V, 0V to +10V and 0 V to +5V high level input
signals to be directly accommodated on the analog input without
requiring split supplies, dc-dc converters or charge pumps. This
part operates with a supply voltage of 2.7 V to 3.3 V or 4.75 V
to 5.25 V.
The AD7707 contains two low level (AIN1 and AIN2) program-
mable-gain pseudo-differential analog input channels and one
high level (AIN3) single-ended input channel. For the low level
input channels the selectable gains are 1, 2, 4, 8, 16, 32, 64 and
128 allowing the part to accept unipolar signals of betweenmV to +20mV and 0 V to +2.5V, or bipolar signals in the
range from –20mV to –2.5V when the reference input voltage
equals +2.5V. With a reference voltage of +1.225V, the input
ranges are from 0 mV to +10mV to 0 V to +1.225V in unipolar
mode, and from –10mV to –1.225 V in bipolar mode. Note
that the signals are with respect to the LOCOM input.
The high level input channel can directly accept input signals of10 V with respect to HICOM when operating with 5V sup-
plies and a reference of 2.5V. With 3V supplies –5V can be
accommodated on the AIN3 input.
The input signal to the analog input is continuously sampled at a
rate determined by the frequency of the master clock, MCLK␣IN,
and the selected gain. A charge-balancing A/D converter
(Sigma-Delta Modulator) converts the sampled signal into a
digital pulse train whose duty cycle contains the digital informa-
tion. The programmable gain function on the analog input is
also incorporated in this sigma-delta modulator with the input
sampling frequency being modified to give the higher gains. A
sinc3 digital low-pass filter processes the output of the sigma-
delta modulator and updates the output register at a rate deter-
mined by the first notch frequency of this filter. The output data
can be read from the serial port randomly or periodically at any
rate up to the output register update rate. The first notch of this
digital filter (and hence its –3␣dB frequency) can be programmed
via the Setup Register bits FS0 and FS1. With a master clock
frequency of 2.4576 MHz, the programmable range for this first
notch frequency is from 10 Hz to 500 Hz, giving a program-
mable range for the –3␣dB frequency of 2.62 Hz to 131␣Hz.
With a master clock frequency of 1 MHz, the programmable
range for this first notch frequency is from 4 Hz to 200 Hz,
giving a programmable range for the –3␣dB frequency of 1.06␣Hz
to 52.4␣Hz.
The basic connection diagram for the AD7707 is shown in
Figure 10. An AD780 or REF192, precision +2.5 V reference,
provides the reference source for the part. On the digital side,
the part is configured for three-wire operation with CS tied to
DGND. A quartz crystal or ceramic resonator provide the mas-
ter clock source for the part. In most cases, it will be necessary
to connect capacitors on the crystal or resonator to ensure that it
does not oscillate at overtones of its fundamental operating
frequency. The values of capacitors will vary, depending on the
manufacturer’s specifications. A similar circuit is applicable for
operation with 3V supplies, in this case a 1.225V reference
(AD1580) should be used for specified performance.
ANALOG
+5V SUPPLY
LOW LEVEL
ANALOG
INPUT
HIGH LEVEL
ANALOG
INPUT
ANALOG +5V
SUPPLYDATA READYRECEIVE (READ)SERIAL DATASERIAL CLOCK
+5V
CRYSTAL OR
CERAMIC
RESONATOR
0.1mFFigure 10.Basic Connection Diagram for 5 V Operation
AD7707
ANALOG INPUT
Analog Input RangesThe AD7707 contains two low level pseudo-differential analog
input channels AIN1 and AIN2. These input pairs provide
programmable-gain, differential input channels that can handle
either unipolar or pseudo bipolar input signals. It should be
noted that the bipolar input signals are referenced to the
LOCOM input. The AD7707 also has a high level analog input
channel AIN 3 which is referenced to HICOM. Figure 11
shows the input structure on the high level input channel.
In normal 5V operation VBIAS is normally connected to 2.5V
and HICOM is connected to AGND. This arrangement ensures
that the voltages seen internally are within the common-mode
range of the buffer in buffered mode and within the supply
range in unbuffered mode. This device can be programmed to
operate in either buffered or unbuffered mode via the BUF bit
in the setup register. Note that the signals on AIN3 are with
respect to the HICOM input and not with respect to AGND or
DGND.
The differential voltage seen by the AD7707 when using the
high level input channel is the difference between AIN3(+) and
AIN3(–) on the mux as shown in Figure 11.
AIN3(+) = (AIN3 + 6 · VBIAS+ V (HICOM))/8
AIN3
VBIAS
HICOMFigure 11.AIN3 Input Structure
AIN3(–) = V (HICOM) + 0.75 · (VBIAS – V (HICOM))
In unbuffered mode, the common-mode range of the low level
input channels is from AGND – 100mV to AVDD +␣30mV.
This means that in unbuffered mode the part can handle both
unipolar and bipolar input ranges for all gains. Absolute volt-
ages of AGND – 100 mV can be accommodated on the analog
inputs without degradation in performance, but leakage current
increases appreciably with increasing temperature. In buffered
mode, the analog inputs can handle much larger source imped-
ances, but the absolute input voltage range is restricted to be-
tween AGND␣+ 50mV to AVDD – 1.5V which also places
restrictions on the common-mode range. This means that in
buffered mode there are some restrictions on the allowable
gains for bipolar input ranges. Care must be taken in setting up
the common-mode voltage and input voltage range so that the
above limits are not exceeded, otherwise there will be a degra-
dation in linearity performance.
In unbuffered mode, the analog inputs look directly into thepF input sampling capacitor, CSAMP. The dc input leakage
current in this unbuffered mode is 1␣nA maximum. As a result,
the analog inputs see a dynamic load that is switched at the
input sample rate (see Figure 12). This sample rate depends on
master clock frequency and selected gain. CSAMP is charged to
CSAMP must be charged through RSW and any additional source
impedances every input sample cycle. Therefore, in unbuffered
mode, source impedances mean a longer charge time for CSAMP
and this may result in gain errors on the part. Table XVI shows
the allowable external resistance/capacitance values, for unbuffered
mode, such that no gain error to the 16-bit level is introduced
on the part. Note that these capacitances are total capacitances
on the analog input. This external capacitance includes 10 pF
from pins and lead frame of the device.
AIN(+)
AIN(–)Figure 12.Unbuffered Analog Input Structure
Table XVI.External R, C Combination for No 16-Bit Gain
Error on Low Level Input Channels (Unbuffered Mode Only)
EXTERNAL CAPACITANCE – pF10000
EXTERNAL RESISTANCE – k10010000
400Figure 13.External R, C Combination for No 16-Bit Gain
Error on Low Level Input Channels (Unbuffered Mode Only)
In buffered mode, the analog inputs look into the high imped-
ance inputs stage of the on-chip buffer amplifier. CSAMP is
charged via this buffer amplifier such that source impedances do
not affect the charging of CSAMP. This buffer amplifier has an
offset leakage current of 1 nA. In buffered mode, large source
impedances result in a small dc offset voltage developed across
the source impedance, but not in a gain error.
