AD7705BN ,3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCsapplications. These two-/three-channelDINdevices can accept low level input signals directly from a ..
AD7705BN ,3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCsSpecifications for AIN and REF IN Unless Noted2Input Common-Mode Rejection (CMR)V = 5 VDD Gain = 1 ..
AD7705BR ,3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCsspecifications T to T unless otherwise noted.)DD MIN MAX1Parameter B Version Units Conditions/Comme ..
AD7705BRU ,3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCsFEATURESAD7705: Two Fully Differential Input Channel ADCsVDD REF IN(–) REF IN(+)AD7706: Three Pseud ..
AD7706BN ,3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCsfeatures two fully differ-20␣ m W typ. These parts are available in a 16-lead, 0.3 inch-wide,ential ..
AD7706BN ,3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCsGENERAL DESCRIPTIONMCLK IN SCLKThe AD7705/AD7706 are complete analog front ends for lowCLOCKGENERAT ..
ADM1026JST ,Complete Thermal and System Management ControllerSPECIFICATIONSParameter Min Typ Max Units Test Conditions/CommentsPOWER SUPPLYSupply Voltage, 3.3V ..
ADM1026JST-REEL ,Highly Integrated Thermal and System Monitor for Servers/High Reliability SystemsCharacteristics ........ 5 Analog Output.... 22 ESD Caution. 5 Fan Speed Measurement ..... 25 Pin C ..
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ADM1026JSTZ-REEL7 ,Highly Integrated Thermal and System Monitor for Servers/High Reliability SystemsSpecifications subject to change without notice. No license is granted by implication www.analog.c ..
AD7705B N-AD7705BN-AD7705BR-AD7705BRU-AD7706BN
3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs
REV.A
3 V/5 V, 1 mW
2-/3-Channel 16-Bit, Sigma-Delta ADCs
FUNCTIONAL BLOCK DIAGRAMFEATURES
AD7705: Two Fully Differential Input Channel ADCs
AD7706: Three Pseudo Differential Input Channel ADCs
16 Bits No Missing Codes
0.003% Nonlinearity
Programmable Gain Front End
Gains from 1 to 128
Three-Wire Serial Interface
SPI™, QSPI™, MICROWIRE™ and DSP Compatible
Schmitt Trigger Input on SCLK
Ability to Buffer the Analog Input
2.7 V to 3.3 V or 4.75 V to 5.25 V Operation
Power Dissipation 1 mW max @ 3␣V
Standby Current 8 mA max
16-Lead DIP, 16-Lead SOIC and TSSOP Packages
GENERAL DESCRIPTIONThe AD7705/AD7706 are complete analog front ends for low
frequency measurement applications. These two-/three-channel
devices can accept low level input signals directly from a trans-
ducer and produce a serial digital output. They employ a sigma-
delta conversion technique to realize up to 16 bits of no missing
codes performance. The selected input signal is applied to a
proprietary programmable gain front end based around an ana-
log modulator. The modulator output is processed by an on-
chip digital filter. The first notch of this digital filter can be
programmed via an on-chip control register allowing adjustment
of the filter cutoff and output update rate.
The AD7705/AD7706 operate from a single 2.7 V to 3.3 V or
4.75 V to 5.25 V supply. The AD7705 features two fully differ-
ential analog input channels while the AD7706 features three
pseudo differential input channels. Both devices feature a differ-
ential reference input. Input signal ranges of 0 mV to +20␣mV
through 0 V to +2.5␣V can be incorporated on both devices when
operating with a VDD of 5 V and a reference of 2.5 V. They can
also handle bipolar input signal ranges of –20␣mV through –2.5␣V,
which are referenced to the AIN(–) inputs on the AD7705 and to
the COMMON input on the AD7706. The AD7705/AD7706,
with 3 V supply and a 1.225 V reference, can handle unipolar
input signal ranges of 0 mV to +10␣mV through 0 V to +1.225␣V.
Its bipolar input signal ranges are –10␣mV through –1.225␣V.
The AD7705/AD7706 thus perform all signal conditioning and
conversion for a two- or three-channel system.
The AD7705/AD7706 are ideal for use in smart, microcontroller
or DSP-based systems. They feature a serial interface that can
be configured for three-wire operation. Gain settings, signal
polarity and update rate selection can be configured in software
using the input serial port. The part contains self-calibration and
system calibration options to eliminate gain and offset errors on
the part itself or in the system.
CMOS construction ensures very low power dissipation, and the
power-down mode reduces the standby power consumption to
20␣mW typ. These parts are available in a 16-lead, 0.3 inch-wide,
plastic dual-in-line package (DIP), a 16-lead wide body (0.3
inch) small outline (SOIC) package and also a low profile 16-
lead TSSOP.
PRODUCT HIGHLIGHTSThe AD7705/AD7706 consumes less than 1 mW at 3 V
supplies and 1␣MHz master clock, making it ideal for use in
low power systems. Standby current is less than 8␣mA.The programmable gain input allows the AD7705/AD7706
to accept input signals directly from a strain gage or trans-
ducer, removing a considerable amount of signal conditioning.The AD7705/AD7706 is ideal for microcontroller or DSP
processor applications with a three-wire serial interface re-
ducing the number of interconnect lines and reducing the
number of opto-couplers required in isolated systems.The part features excellent static performance specifications
with 16 bits, no missing codes, –0.003% accuracy and low
rms noise (<600␣nV). Endpoint errors and the effects of
temperature drift are eliminated by on-chip calibration op-
tions, which remove zero-scale and full-scale errors.
*. Patent Number 5,134,401.SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor.
VDDREF IN(–)REF IN(+)
MCLK IN
MCLK OUT
GNDDRDYRESET
DIN
DOUT
SCLK
ANALOG
INPUT
CHANNELS
AD7705/AD7706–SPECIFICATIONS (VDD = +3 V or 5 V, REF IN(+) = +1.225␣V with VDD = 3 V and +2.5 V
with VDD = 5 V; REF␣IN(–) = GND; MCLK IN = 2.4576␣MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)LOGIC INPUTS
AD7705/AD7706NOTESTemperature range as follows: B Version, –40°C to +85°C.These numbers are established from characterization or design at initial product release.A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I and III. This applies after calibration at the
temperature of interest.Recalibration at any temperature will remove these drift errors.Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error–Unipolar Offset Error for unipolar ranges and Full-Scale Error–Bipolar Zero Error for
bipolar ranges.Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero scale calibrations only were performed.This common-mode voltage range is allowed provided that the input voltage on analog inputs does not go more positive than VDD + 30 mV or go more negative than
GND – 30␣mV. Parts are functional with voltages down to GND – 200 mV, but with increased leakage at high temperature.The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(–) on the AD7705 and is given with respect to the COMMON input on the
AD7706. The absolute voltage on the analog inputs should not go more positive than VDD + 30␣mV, or go more negative than GND␣– 30␣mV for specified performance, input
voltages of GND – 200 mV can be accommodated, but with increased leakage at high temperature.VREF = REF IN(+) – REF IN(–).These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.Sample tested at +25°C to ensure compliance.After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will output all 0s.These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed VDD + 30␣mV or go more negative than GND – 30␣mV. The offset
calibration limit applies to both the unipolar zero point and the bipolar zero point.When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the VDD current and power dissipation will vary depending on the crystal or
resonator type (see Clocking and Oscillator Circuit section).If the external master clock continues to run in standby mode, the standby current increases to 150␣mA typical at 5 V and 75 mA at 3 V. When using a crystal or ceramic
resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal
or resonator type (see Standby Mode section).Measured at dc and applies in the selected passband. PSRR at 50␣Hz will exceed 120␣dB with filter notches of 25 Hz or 50␣Hz. PSRR at 60␣Hz will exceed 120␣dB with filter
notches of 20 Hz or 60␣Hz.PSRR depends on both gain and VDD.
AD7705/AD7706
TIMING CHARACTERISTICS1, 2Read Operation
NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.See Figures 16 and 17.fCLKIN Duty Cycle range is 45% to 55%. fCLKIN must be supplied whenever the AD7705/AD7706 is not in Standby mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.The AD7705/AD7706 is production tested with fCLKIN at 2.4576␣MHz (1␣MHz for some IDD tests). It is guaranteed by characterization to operate at 400␣kHz.These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.These numbers are derived from the measured time taken by the data output to change 0.5␣V when loaded with the circuit of Figure 1. The measured number is
then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and as such are independent of external bus loading capacitances.DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high, although care
should be taken that subsequent reads do not occur close to the next output update.
TO OUTPUT
PIN
50pF
ISINK (800mA AT VDD = +5V
100mA AT VDD = +3V)
+1.6V
ISOURCE (200mA AT VDD = +5V
100mA AT VDD = +3V)Figure 1.Load Circuit for Access Time and Bus Relinquish Time
(VDD = +2.7␣V to +5.25␣V; GND = 0 V; fCLKIN = 2.4576␣MHz; Input Logic 0 = 0 V, Logic 1 = VDD
unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3␣V to +7␣V
Analog Input Voltage to GND . . . . . . . .–0.3 V to VDD + 0.3␣V
Reference Input Voltage to GND . . . . .–0.3 V to VDD + 0.3␣V
Digital Input Voltage to GND . . . . . . . .–0.3 V to VDD + 0.3 V
Digital Output Voltage to GND . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (B Version) . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . .450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .105°C/W
Lead Temperature, (Soldering, 10 sec) . . . . . . . . . .+260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . .450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . .450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .139°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
␣␣␣␣Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4000␣V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
AD7705/AD7706
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS
OUTPUT NOISE (5 V OPERATION)Table I shows the AD7705/AD7706 output rms noise for the selectable notch and –3␣dB frequencies for the part, as selected by FS0
and FS1 of the Clock Register. The numbers given are for the bipolar input ranges with a VREF of +2.5␣V and VDD = 5 V. These
numbers are typical and are generated at an analog input voltage of 0␣V with the part used in either buffered or unbuffered mode. Table II
meanwhile shows the output peak-to-peak noise for the selectable notch and –3 dB frequencies for the part. It is important to note that
these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak
noise. The numbers given are for bipolar input ranges with a VREF of +2.5 V and for either buffered or unbuffered mode. These num-
bers are typical and are rounded to the nearest LSB. The numbers apply for the CLK DIV bit of the Clock Register set to 0.
Table I.Output RMS Noise vs. Gain and Output Update Rate @ 5 V
AD7705/AD7706
Table II.Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V
OUTPUT NOISE (3 V OPERATION)Table III shows the AD7705/AD7706 output rms noise for the selectable notch and –3␣dB frequencies for the part, as selected by
FS0 and FS1 of the Clock Register. The numbers given are for the bipolar input ranges with a VREF of +1.225␣V and a VDD = 3 V.
These numbers are typical and are generated at an analog input voltage of 0␣V with the part used in either buffered or unbuffered
mode. Table II meanwhile shows the output peak-to-peak noise for the selectable notch and –3 dB frequencies for the part. It is im-
portant to note that these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but
on peak-to-peak noise. The numbers given are for bipolar input ranges with a VREF of +1.225 V and for either buffered or unbuffered
mode. These numbers are typical and are rounded to the nearest LSB. The numbers apply for the CLK DIV bit of the Clock Regis-
ter set to 0.
Table III.Output RMS Noise vs. Gain and Output Update Rate @ 3 V
Table IV.␣ Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 3 V
READING NO.
CODE READ
2003004005006007008009001000Figure 2.Typical Noise Plot @ Gain = 128 with 50 Hz
Update Rate
FREQUENCY – MHz
– mA
0.60.81.01.21.41.61.82.02.22.42.6Figure 3.Typical IDD vs. MCLKIN Frequency @ 3 V
GAIN
IDD
– mA
0.948163264128Figure 4.Typical IDD vs. Gain and Clock Frequency @ 3 V
CODE
OCCURRENCE
100Figure 5.Histogram of Data in Figure 2
FREQUENCY – MHz
IDD
– mA
0.60.81.01.21.41.61.82.02.22.42.6Figure 6.Typical IDD vs. MCLKIN Frequency @ 5 V
Figure 7.Typical IDD vs. Gain and Clock Frequency @ 5 V
AD7705/AD7706
ON-CHIP REGISTERSThe AD7705/AD7706 contains eight on-chip registers which can be accessed via the serial port of the part. The first of these is a
Communications Register that controls the channel selection, decides whether the next operation is a read or write operation and
also decides which register the next read or write operation accesses. All communications to the part must start with a write opera-
tion to the Communications Register. After power-on or RESET, the device expects a write to its Communications Register. The
data written to this register determines whether the next operation to the part is a read or a write operation and also determines to
which register this read or write operation occurs. Therefore, write access to any of the other registers on the part starts with a write
operation to the Communications Register followed by a write to the selected register. A read operation from any other register on
the part (including the Communications Register itself and the output data register) starts with a write operation to the Communica-
tions Register followed by a read operation from the selected register. The Communications Register also controls the standby mode
and channel selection and the DRDY status is also available by reading from the Communications Register. The second register is a
Setup Register that determines calibration mode, gain setting, bipolar/unipolar operation and buffered mode. The third register is
labelled the Clock Register and contains the filter selection bits and clock control bits. The fourth register is the Data Register from
which the output data from the part is accessed. The final registers are the calibration registers which store channel calibration data.
The registers are discussed in more detail in the following sections.
Communications Register (RS2, RS1, RS0 = 0, 0, 0)The Communications Register is an 8-bit register from which data can either be read or to which data can be written. All communi-
cations to the part must start with a write operation to the Communications Register. The data written to the Communications Reg-
ister determines whether the next operation is a read or write operation and to which register this operation takes place. Once the
subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to
the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7705/AD7706 is
in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost,
if a write operation of sufficient duration (containing at least 32 serial clock cycles) takes place with DIN high, the AD7705 returns
to this default state. Table V outlines the bit designations for the Communications Register.
Table V.␣Communications Register0/DRDYFor a write operation, a “0” must be written to this bit so that the write operation to the Communications Register
actually takes place. If a “1” is written to this bit, the part will not clock on to subsequent bits in the register. It
will stay at this bit location until a “0” is written to this bit. Once a “0” is written to this bit, the next seven bits
will be loaded to the Communications Register. For a read operation, this bit provides the status of the DRDY flag
from the part. The status of this bit is the same as the DRDY output pin.
RS2–RS0Register Selection Bits. These three bits select to which one of eight on-chip registers the next read or write opera-
Figure 9.Standby Current vs. Temperature
Figure 8.Typical Crystal Oscillator Power-Up Time
Table VI.Register SelectionR/WRead/Write Select. This bit selects whether the next operation is a read or write operation to the selected register.
A “0” indicates a write cycle for the next operation to the appropriate register, while a “1” indicates a read opera-
tion from the appropriate register.
STBYStandby. Writing a “1” to this bit puts the part into its standby or power-down mode. In this mode, the part con-
sumes only 10 mA of power supply current. The part retains its calibration coefficients and control word informa-
tion when in STANDBY. Writing a “0” to this bit places the part in its normal operating mode.
CH1–CH0Channel Select. These two bits select a channel for conversion or for access to the calibration coefficients as out-
lined in Table VII. Three pairs of calibration registers on the part are used to store the calibration coefficients
following a calibration on a channel. They are shown in Tables VII for the AD7705 and Table VIII for the AD7706
to indicate which channel combinations have independent calibration coefficients. With CH1 at Logic 1 and CH0
at a Logic 0, the part looks at the AIN1(–) input internally shorted to itself on the AD7705 or at COMMON
internally shorted to itself on the AD7706. This can be used as a test method to evaluate the noise performance of
the part with no external noise sources. In this mode, the AIN1(–)/COMMON input should be connected to
an external voltage within the allowable common-mode range for the part.
Table VII.Channel Selection for AD7705
Table VIII.Channel Selection for AD7706
AD7705/AD7706
Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 01␣HexThe Setup Register is an eight bit register from which data can either be read or to which data can be written. Table IX outlines the
bit designations for the Setup Register.
Table IX.Setup RegisterG2–G0Gain Selection Bits. These bits select the gain setting for the on-chip PGA as outlined in Table X.
Table X.Gain SelectionB/UBipolar/Unipolar Operation. A “0” in this bit selects Bipolar Operation. A “1” in this bit selects Unipolar Operation.
BUFBuffer Control. With this bit at “0,” the on-chip buffer on the analog input is shorted out. With the buffer shorted
out, the current flowing in the VDD line is reduced. When this bit is high, the on-chip buffer is in series with the
analog input allowing the input to handle higher source impedances.
FSYNCFilter Synchronization. When this bit is high, the nodes of the digital filter, the filter control logic and the calibra-
tion control logic are held in a reset state and the analog modulator is also held in its reset state. When this bit
goes low, the modulator and filter start to process data and a valid word is available in 3 · 1/(output update rate),
i.e., the settling time of the filter. This FSYNC bit does not affect the digital interface and does not reset the
DRDY output if it is low.
Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset Status: 05␣HexThe Clock Register is an 8-bit register from which data can either be read or to which data can be written. Table XI outlines the bit
designations for the Clock Register.
Table XI.Clock RegisterZEROZero. A zero MUST be written to these bits to ensure correct operation of the AD7705/AD7706. Failure to do so
may result in unspecified operation of the device.
CLKDISMaster Clock Disable Bit. A Logic 1 in this bit disables the master clock from appearing at the MCLK OUT pin.
When disabled, the MCLK OUT pin is forced low. This feature allows the user the flexibility of using the MCLK
OUT as a clock source for other devices in the system or of turning off the MCLK OUT as a power saving feature.
When using an external master clock on the MCLK IN pin, the AD7705/AD7706 continues to have internal
clocks and will convert normally with the CLKDIS bit active. When using a crystal oscillator or ceramic resonator
across the MCLK IN and MCLK OUT pins, the AD7705/AD7706 clock is stopped and no conversions take place
when the CLKDIS bit is active.
CLKDIVClock Divider Bit. With this bit at a Logic 1, the clock frequency appearing at the MCLK IN pin is divided by two
before being used internally by the AD7705/AD7706. For example, when this bit is set to 1, the user can operate
with a 4.9152 MHz crystal between MCLK IN and MCLK OUT and internally the part will operate with the
specified 2.4576 MHz. With this bit at a Logic 0, the clock frequency appearing at the MCLK IN pin is the fre-
quency used internally by the part.
CLKClock Bit. This bit should be set in accordance with the operating frequency of the AD7705/AD7706. If the device
has a master clock frequency of 2.4576 MHz (CLKDIV = 0) or 4.9152 MHz (CLKDIV = 1), then this bit should
be set to a “1.” If the device has a master clock frequency of 1 MHz (CLKDIV = 0) or 2 MHz (CLKDIV = 1),
this bit should be set to a “0.” This bit sets up the appropriate scaling currents for a given operating frequency and
also chooses (along with FS1 and FS0) the output update rate for the device. If this bit is not set correctly for the
master clock frequency of the device, then the AD7705/AD7706 may not operate to specification.
FS1, FS0Filter Selection Bits. Along with the CLK bit, FS1 and FS0 determine the output update rate, filter first notch and
–3 dB frequency as outlined in Table XII. The on-chip digital filter provides a sinc3 (or Sinx/x3) filter response. In
association with the gain selection, it also determines the output noise of the device. Changing the filter notch
frequency, as well as the selected gain, impacts resolution. Tables I to IV show the effect of filter notch frequency
and gain on the output noise and effective resolution of the part. The output data rate (or effective conversion
time) for the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch
of the filter is selected at 50 Hz, a new word is available at a 50 Hz output rate or every 20 ms. If the first notch is
at 500 Hz, a new word is available every 2 ms. A calibration should be initiated when any of these bits are changed.
The settling time of the filter to a full-scale step input is worst case 4 · 1/(output data rate). For example, with the
filter first notch at 50 Hz, the settling time of the filter to a full-scale step input is 80 ms max. If the first notch is at
500 Hz, the settling time is 8 ms max. This settling time can be reduced to 3 · 1/(output data rate) by synchroniz-
ing the step input change to a reset of the digital filter. In other words, if the step input takes place with the FSYNC bit
high, the settling-time will be 3 · 1/(output data rate) from when the FSYNC bit returns low.
The –3 dB frequency is determined by the programmed first notch frequency according to the relationship:
filter –3 dB frequency = 0.262 · filter first notch frequency
Table XII.Output Update Rates
AD7705/AD7706
Data Register (RS2, RS1, RS0 = 0, 1, 1)The Data Register on the part is a 16-bit read-only register that contains the most up-to-date conversion result from the AD7705/
AD7706. If the Communications Register sets up the part for a write operation to this register, a write operation must actually take
place to return the part to where it is expecting a write operation to the Communications Register. However, the 16 bits of data
written to the part will be ignored by the AD7705/AD7706.
Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset Status: 00␣HexThe part contains a Test Register that is used when testing the device. The user is advised not to change the status of any of the bits
in this register from the default (Power-on or RESET) status of all 0s as the part will be placed in one of its test modes and will not
operate correctly.
Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); Power-On/Reset Status: 1F4000␣HexThe AD7705/AD7706 contains independent sets of zero-scale registers, one for each of the input channels. Each of these registers is
a 24-bit read/write register; 24 bits of data must be written otherwise no data will be transferred to the register. This register is used
in conjunction with its associated full-scale register to form a register pair. These register pairs are associated with input channel
pairs as outlined in Table VII. While the part is set up to allow access to these registers over the digital interface, the part itself no
longer has access to the register coefficients to correctly scale the output data. As a result, there is a possibility that after accessing the
calibration registers (either read or write operation) the first output data read from the part may contain incorrect data. In addition, a
write to the calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by
taking the FSYNC bit in the mode register high before the calibration register operation and taking it low after the operation is
complete.
Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1); Power-On/Reset Status: 5761AB␣HexThe AD7705/AD7706 contains independent sets of full-scale registers, one for each of the input channels. Each of these registers is a
24-bit read/write register; 24 bits of data must be written otherwise no data will be transferred to the register. This register is used in
conjunction with its associated zero-scale register to form a register pair. These register pairs are associated with input channel pairs
as outlined in Table VII. While the part is set up to allow access to these registers over the digital interface, the part itself no longer
has access to the register coefficients to correctly scale the output data. As a result, there is a possibility that after accessing the cali-
bration registers (either read or write operation) the first output data read from the part may contain incorrect data. In addition, a
write to the calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by
taking FSYNC bit in the mode register high before the calibration register operation and taking it low after the operation is complete.
CALIBRATION SEQUENCESThe AD7705/AD7706 contains a number of calibration options as previously outlined. Table XIII summarizes the calibration types,
the operations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is
to monitor when DRDY returns low at the end of the sequence. DRDY not only indicates when the sequence is complete, but also
that the part has a valid new sample in its data register. This valid new sample is the result of a normal conversion which follows the
calibration sequence. The second method of determining when calibration is complete is to monitor the MD1 and MD0 bits of the
Setup Register. When these bits return to 0 (0 following a calibration command), it indicates that the calibration sequence is com-
plete. This method does not give any indication of there being a valid new result in the data register. However, it gives an earlier
indication than DRDY that calibration is complete. The duration to when the Mode Bits (MD1 and MD0) return to 0 (0 represents
the duration of the calibration carried out). The sequence to when DRDY goes low also includes a normal conversion and a pipeline
delay, tP, to correctly scale the results of this first conversion. tP will never exceed 2000 · tCLKIN. The time for both methods is given
in the table.
Table XIII.Calibration Sequences
CIRCUIT DESCRIPTIONThe AD7705/AD7706 is a sigma-delta A/D converter with on-
chip digital filtering, intended for the measurement of wide
dynamic range, low frequency signals such as those in industrial
control or process control applications. It contains a sigma-delta
(or charge-balancing) ADC, a calibration microcontroller with
on-chip static RAM, a clock oscillator, a digital filter and a bi-
directional serial communications port. The part consumes only
320␣mA of power supply current, making it ideal for battery-
powered or loop-powered instruments. These parts operate with
a supply voltage of 2.7 V to 3.3 V or 4.75 V to 5.25 V.
The AD7705 contains two programmable-gain fully differential
analog input channels, while the AD7706 contains three pseudo
differential analog input channels. The selectable gains on these
inputs are 1, 2, 4, 8, 16, 32, 64 and 128 allowing the part to
accept unipolar signals of between 0 mV to +20␣mV and 0 V to
+2.5␣V, or bipolar signals in the range from –20␣mV to –2.5␣V
when the reference input voltage equals +2.5␣V. With a refer-
ence voltage of +1.225␣V, the input ranges are from 0 mV to
+10␣mV to 0 V to +1.225␣V in unipolar mode, and from –10␣mV
to –1.225 V in bipolar mode. Note that the bipolar ranges are
with respect to AIN(–) on the AD7705, and with respect to
COMMON on the AD7706, and not with respect to GND.
The input signal to the analog input is continuously sampled
at a rate determined by the frequency of the master clock,
MCLK␣IN, and the selected gain. A charge-balancing A/D
converter (Sigma-Delta Modulator) converts the sampled signal
into a digital pulse train whose duty cycle contains the digital
information. The programmable gain function on the analog
input is also incorporated in this sigma-delta modulator with the
input sampling frequency being modified to give the higher
gains. A sinc3 digital low-pass filter processes the output of the
sigma-delta modulator and updates the output register at a rate
determined by the first notch frequency of this filter. The out-
put data can be read from the serial port randomly or periodi-
cally at any rate up to the output register update rate. The first
notch of this digital filter (and hence its –3␣dB frequency) can
be programmed via the Setup Register bits FS0 and FS1. With
a master clock frequency of 2.4576␣MHz, the programmable
range for this first notch frequency is from 50␣Hz to 500␣Hz,
giving a programmable range for the –3␣dB frequency of
13.1␣Hz to 131␣Hz. With a master clock frequency of 1␣MHz,
the programmable range for this first notch frequency is from
20␣Hz to 200␣Hz, giving a programmable range for the –3␣dB
frequency of 5.24␣Hz to 52.4␣Hz.
The basic connection diagram for the AD7705 is shown in
Figure 10. This shows the AD7705 being driven from the ana-
log +5␣V supply. An AD780, precision +2.5 V reference, pro-
vides the reference source for the part. On the digital side, the
part is configured for three-wire operation with CS tied to
GND. A quartz crystal or ceramic resonator provide the master
clock source for the part. In most cases, it will be necessary to
connect capacitors on the crystal or resonator to ensure that it
does not oscillate at overtones of its fundamental operating fre-
quency. The values of capacitors will vary, depending on the
manufacturer’s specifications. The same setup applies to the
AD7706.
ANALOG
+5V SUPPLY
DIFFERENTIAL
ANALOG
INPUT
DIFFERENTIAL
ANALOG
INPUT
ANALOG +5V
SUPPLYDATA READYRECEIVE (READ)SERIAL DATASERIAL CLOCK
+5V
CRYSTAL OR
CERAMIC
RESONATORFigure 10.AD7705 Basic Connection Diagram
AD7705/AD7706
ANALOG INPUT
Analog Input RangesThe AD7705 contains two differential analog input pairs
AIN1(+), AIN1(–) and AIN2(+), AIN2(–). These input pairs
provide programmable-gain, differential input channels that
can handle either unipolar or bipolar input signals. It should be
noted that the bipolar input signals are referenced to the re-
spective AIN(–) input of each input pair. The AD7706 contains
three pseudo differential analog input pairs AIN1, AIN2 and
AIN3, which are referenced to the COMMON input on the part.
In unbuffered mode, the common-mode range of the input is
from GND to VDD, provided that the absolute value of the
analog input voltage lies between GND␣–␣30␣mV and VDD30␣mV. This means that in unbuffered mode the part can
handle both unipolar and bipolar input ranges for all gains.
Absolute voltages of GND – 200 mV can be accommodated on
the analog inputs at 25°C without degradation in performance,
but leakage current increases appreciably with increasing tem-
perature. In buffered mode, the analog inputs can handle
much larger source impedances, but the absolute input voltage
range is restricted to between GND␣+ 50␣mV to VDD – 1.5 V
which also places restrictions on the common-mode range. This
means that in buffered mode there are some restrictions on the
allowable gains for bipolar input ranges. Care must be taken in
setting up the common-mode voltage and input voltage range
so that the above limits are not exceeded, otherwise there will
be a degradation in linearity performance.
In unbuffered mode, the analog inputs look directly into thepF input sampling capacitor, CSAMP. The dc input leakage
current in this unbuffered mode is 1␣nA maximum. As a result,
the analog inputs see a dynamic load that is switched at the
input sample rate (see Figure 11). This sample rate depends on
master clock frequency and selected gain. CSAMP is charged to
AIN(+) and discharged to AIN(–) every input sample cycle.
The effective on-resistance of the switch, RSW, is typically 7␣kW.
CSAMP must be charged through RSW and through any external
source impedances every input sample cycle. Therefore, in
unbuffered mode, source impedances mean a longer charge time
for CSAMP and this may result in gain errors on the part. Table
XIV shows the allowable external resistance/capacitance values,
for unbuffered mode, such that no gain error to the 16-bit level
is introduced on the part. Note that these capacitances are
total capacitances on the analog input, external capacitance
plus 10 pF capacitance from the pins and lead frame of the device.
AIN(+)
AIN(–)Figure 11.Unbuffered Analog Input Structure
Table XIV.External R, C Combination for No 16-Bit Gain
Error (Unbuffered Mode Only)In buffered mode, the analog inputs look into the high-impedance
inputs stage of the on-chip buffer amplifier. CSAMP is charged
via this buffer amplifier such that source impedances do not
affect the charging of CSAMP. This buffer amplifier has an offset
leakage current of 1 nA. In this buffered mode, large source
impedances result in a small dc offset voltage developed across
the source impedance, but not in a gain error.
Input Sample RateThe modulator sample frequency for the AD7705/AD7706
remains at fCLKIN/128 (19.2␣kHz @ fCLKIN = 2.4576␣MHz) re-
gardless of the selected gain. However, gains greater than 1 are
achieved by a combination of multiple input samples per modu-
lator cycle and a scaling of the ratio of reference capacitor to
input capacitor. As a result of the multiple sampling, the input
sample rate of the device varies with the selected gain (see Table
XV). In buffered mode, the input is buffered before the input
sampling capacitor. In unbuffered mode, where the analog
input looks directly into the sampling capacitor, the effective
input impedance is 1/CSAMP · fS where CSAMP is the input sam-
pling capacitance and fS is the input sample rate.
Table XV.Input Sampling Frequency vs. Gain
Bipolar/Unipolar InputsThe analog inputs on the AD7705/AD7706 can accept either
unipolar or bipolar input voltage ranges. Bipolar input ranges do
not imply that the part can handle negative voltages on its analog
input, since the analog input cannot go more negative than
–30 mV to ensure correct operation of these parts. The input
channels are fully differential. As a result, on the AD7705, the
voltage to which the unipolar and bipolar signals on the AIN(+)
input are referenced is the voltage on the respective AIN(–)
input. On the AD7706, the voltages applied to the analog input
channels are referenced to the COMMON input. For example, if
AIN1(–) is +2.5␣V and the AD7705 is configured for unipolar
operation with a gain of 2 and a VREF of +2.5␣V, the input voltage
range on the AIN1(+) input is +2.5␣V to +3.75␣V. If AIN1(–) is
+2.5␣V and the AD7705 is configured for bipolar mode with a
gain of 2 and a VREF of +2.5␣V, the analog input range on the
AIN1(+) input is +1.25␣V to +3.75 V (i.e., 2.5␣V – 1.25␣V). If
AIN1(–) is at GND, the part cannot be configured for bipolar
ranges in excess of –30␣mV.
