AD7703BR ,LC2MOS 20-Bit A/D ConverterSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE(T = +25°C ..
AD7703CN ,LC2MOS 20-Bit A/D ConverterSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE(T = +25°C ..
AD7703CR ,LC2MOS 20-Bit A/D Converterapplications, or battery-powered portablesynchronous modes suitable for interfacing to shift regist ..
AD7705B N ,3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCsspecificationswith 16 bits, no missing codes, – 0.003% accuracy and low*Protected by U.S. Patent Nu ..
AD7705BN ,3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCsapplications. These two-/three-channelDINdevices can accept low level input signals directly from a ..
AD7705BN ,3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCsSpecifications for AIN and REF IN Unless Noted2Input Common-Mode Rejection (CMR)V = 5 VDD Gain = 1 ..
ADM1025ARQZ ,Remote Multichannel Temperature Sensor, Power Supply Voltage Monitor with Serial InterfaceAPPLICATIONSvoltage, overvoltage, and overtemperature conditions.Network Servers and Personal Compu ..
ADM1026 ,Highly Integrated Thermal and System Monitor for Servers/High Reliability SystemsSPECIFICATIONSA MIN MAX CC MIN MAXParameter Min Typ Max Test Conditions/Comments UnitPOWER SUPPLYSu ..
ADM1026 ,Highly Integrated Thermal and System Monitor for Servers/High Reliability Systems3ADM1026Table 3. PIN ASSIGNMENTPin No. Mnemonic Type Description17 INT Digital Output Interrupt Req ..
ADM1026JST ,Complete Thermal and System Management ControllerSPECIFICATIONSParameter Min Typ Max Units Test Conditions/CommentsPOWER SUPPLYSupply Voltage, 3.3V ..
ADM1026JST-REEL ,Highly Integrated Thermal and System Monitor for Servers/High Reliability SystemsCharacteristics ........ 5 Analog Output.... 22 ESD Caution. 5 Fan Speed Measurement ..... 25 Pin C ..
ADM1026JST-REEL7 ,Highly Integrated Thermal and System Monitor for Servers/High Reliability SystemsCharacteristics 8 NAND Tree Tests 31 Product Description........ 10 Using the ADM1026 ... 33 Funct ..
AD7703AN-AD7703AR-AD7703BN-AD7703BR-AD7703CN-AD7703CR
LC2MOS 20-Bit A/D Converter
REV.D
LC2MOS
20-Bit A/D Converter
FEATURES
Monolithic 20-Bit ADC
0.0003% Linearity Error
20-Bit No Missed Codes
On-Chip Self-Calibration Circuitry
Programmable Low-Pass Filter
0.1 Hz to 10 Hz Corner Frequency
0 to +2.5 V or +2.5 V Analog Input Range
4 kSPS Output Data Rate
Flexible Serial Interface
Ultralow Power
APPLICATIONS
Industrial Process Control
Weigh Scales
Portable Instrumentation
Remote Data Acquisition
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS1. The AD7703 offers 20-bit resolution coupled with
outstanding 0.0003% accuracy.
2. No missing codes ensures true, usable, 20-bit dynamic range,
removing the need for programmable gain and level-setting
circuitry.
3. The effects of temperature drift are eliminated by on-chip
self-calibration, which removes zero and gain error. External
circuits can also be included in the calibration loop to remove
system offsets and gain errors.
4. A flexible synchronization allows the AD7703 to interface
directly to the serial ports of industry standard
microcontrollers and DSP processors.
5. Low operating power consumption and an ultralow power
standby mode make the AD7703 ideal for loop powered
remote sensing applications, or battery-powered portable
instruments.
GENERAL DESCRIPTIONThe AD7703 is a 20-bit ADC which uses a sigma delta conver-
sion technique. The analog input is continuously sampled by an
analog modulator whose mean output duty cycle is proportional
to the input signal. The modulator output is processed by an
on-chip digital filter with a six-pole Gaussian response, which
updates the output data register with 20-bit binary words at
word rates up to 4 kHz. The sampling rate, filter corner fre-
quency and output word rate are set by a master clock input
that may be supplied externally, or by an on-chip gate oscillator.
The inherent linearity of the ADC is excellent, and endpoint
accuracy is ensured by self-calibration of zero and full scale
which may be initiated at any time. The self-calibration scheme
can also be extended to null system offset and gain errors in the
input channel.
The output data is accessed through a serial port, which has two
synchronous modes suitable for interfacing to shift registers or
the serial ports of industry standard microcontrollers.
CMOS construction ensures low power dissipation, and a power
down mode reduces the idle power consumption to only 10 mW.
AD7703–SPECIFICATIONS
(TA = +258C; AVDD = DVDD = +5 V; AVSS = DVSS = –5 V; VREF = +2.5 V; fCLKIN = 4.096 MHz;
BP/UP = +5 V; MODE = +5 V; AIN Source Resistance = 1 kV1 with 1 nF to AGND at AIN unless otherwise noted.)
NOTESThe AIN pin presents a very high impedance dynamic load which varies with clock frequency. A ceramic 1 nF capacitor from the AIN to AGND is necessary. Source
resistance should be 750 Ω or less.Temperature Ranges are as follows: A, B, C Versions: –40°C to +85°C; S Version: –55°C to +125°C.Applies after calibration at the temperature of interest. Full-Scale Error applies for both unipolar and bipolar input ranges.Total drift over the specified temperature range after calibration at power-up at +25°C. This is guaranteed by design and/or characterization. Recalibration at any
temperature will remove these errors.In unipolar mode the offset can have a negative value (–VREF) such that the unipolar mode can mimic bipolar mode operation.The specifications for input overrange and for input span apply additional constraints on the offset calibration range.For unipolar mode, input span is the difference between full scale and zero scale. For bipolar mode, input span is the difference between positive and negative
full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ±(VREF + 0.1).All digital outputs unloaded. All digital inputs at 5 V CMOS levels.Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter.CLKIN is stopped. All digital inputs are grounded.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
DVDD to AVDD . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
DVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –6 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
Digital Input Voltage to DGND . . . .–0.3 V to DVDD + 0.3 V
Analog Input Voltage to AGND . . . . . . . . . . .AVSS – 0.3 V to
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .AVDD + 0.3 V
Input Current to Any Pin Except Supplies1 . . . . . . . .±10 mA
Operating Temperature Range
Industrial (A, B, C Versions) . . . . . . . . . . .–40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . .+300°C
Power Dissipation (DIP Package) to +75°C . . . . . . .450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . .10 mW/°C
Power Dissipation (SOIC Package) to +75°C . . . . . .250 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . .15 mW/°C
NOTES
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE*N = Plastic DIP; R = SOIC; Q = Cerdip.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
AD7703
AD7703
(AVDD = DVDD = +5 V 6 10%; AVSS = DVSS = –5 V 6 10%; AGND = DGND = 0 V; fCLKIN =
4.096 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted.)TIMING CHARACTERISTICS1, 2SSC MODE
NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.See Figures 1 to 6.CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7703 is not in SLEEP mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.The AD7703 is production tested with fCLKIN at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.Specified using 10% and 90% points on waveform of interest.In order to synchronize several AD7703s together using the SLEEP pin, this specification must be met.t4 and t13 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.t9, t10, t15 and t16 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is
then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the tune quoted in the Timing Characteristics is the
true bus relinquish time of the part and as such is independent of external bus loading capacitances.If CS is returned high before all 20 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be as
great as 4 CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high sooner than
4 CLKIN cycles plus 160 ns after CS goes low.SDATA is clocked out on the falling edge of the SCLK input.
Figure 2. Calibration Control Timing
IOL
1.6mA
+2.1V
OUTPUT
PIN
100pF
IOH
200µAFigure 1.Load Circuit for Access Time and Bus Relinquish
SDATAFigure 5a. SEC Mode Data Hold Time
SDATAFigure 4. SSC Mode Data Hold Time
Figure 5b. SEC Mode Timing Diagram
TERMINOLOGY
LINEARITY ERRORThis is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end-
points of the transfer function are zero-scale (not to be confused
with bipolar zero), a point 0.5 LSB below the first code transi-
tion (000 . . . 000 to 000 . . . 001) and full scale, a point 1.5 LSB
above the last code transition (111 . . . 110 to 111 . . . 111).
The error is expressed as a percentage of full scale.
DIFFERENTIAL LINEARITY ERRORThis is the difference between any code’s actual width and the
ideal (1 LSB) width. Differential linearity error is expressed in
LSBs. A differential linearity specification of ±1 LSB or less
guarantees monotonicity.
POSITIVE FULL-SCALE ERRORPositive full-scale error is the deviation of the last code transition
(111 . . . 110 to 111 . . . 111) from the ideal (VREF –3/2 LSBs).
It applies to both positive and negative analog input ranges.
UNIPOLAR OFFSET ERRORUnipolar offset error is the deviation of the first code transition
from the ideal (AGND + 0.5 LSB) when operating in the uni-
polar mode.
BIPOLAR ZERO ERRORThis is the deviation of the midscale transition (0111 . . . 111 to
1000 . . . 000) from the ideal (AGND – 0.5 LSB) when operat-
ing in the bipolar mode.
BIPOLAR NEGATIVE FULL-SCALE ERRORThis is the deviation of the first code transition from the ideal
AD7703
PIN FUNCTION DESCRIPTION
Table I.Bit Weight Table (2.5 V Reference Voltage)
PIN CONFIGURATION
DIP, Cerdip, SOIC
MODE
SC1
DGND
CLKOUT
CLKIN
AGND
DVSS
AVSS
AIN
SDATA
SCLK
SC2
CAL
AVDD
DVDD
DRDY
BP/UP
THEORY OF OPERATIONThe general block diagram of a sigma-delta ADC is shown in
Figure 8. It contains the following elements:
1. A sample-hold amplifier
2. A differential amplifier or subtracter
3. An analog low-pass filter
4. A 1-bit A/D converter (comparator)
5. A 1-bit DAC
6. A digital low-pass filter
In operation, the sampled analog signal is fed to the subtracter,
along with the output of the 1-bit DAC. The filtered difference
signal is fed to the comparator, whose output samples the
difference signal at a frequency many times that of the analog
signal frequency (oversampling).
Oversampling is fundamental to the operation of sigma-delta
ADCs. Using the quantization noise formula for an ADC:
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
The AD7703 samples the input signal at 16 kHz, which spreads
the quantization noise from 0 kHz to 8 kHz. Since the specified
analog input bandwidth of the AD7703 is only 0 Hz to 10 Hz,
the noise energy in this bandwidth would be only 1/800 of the
total quantization noise, assuming that the noise energy was
spread evenly throughout the spectrum. It is reduced still
further by analog filtering in the modulator loop, which shapes
the quantization noise spectrum to move most of the noise
energy to frequencies above 10 Hz. The SNR performance in
the 0 Hz to 10 Hz range is conditioned to the 20-bit level in this
fashion.
The output of the comparator provides the digital input for the
1-bit DAC, so the system functions as a negative feedback loop
which minimizes the difference signal. The digital data that
represents the analog input voltage is in the duty cycle of the
pulse train appearing at the output of the comparator. It can be
retrieved as a parallel binary data word using a digital filter.
Sigma-delta ADCs are generally described by the order of the
analog low-pass filter. A simple example of a first order sigma-
delta ADC is shown in Figure 8. This contains only a first-order
low-pass filter or integrator.
The AD7703 uses a second-order sigma-delta modulator and a
digital filter that provides a rolling average of the sampled
output. After power-up or if there is a step change in the input
GENERAL DESCRIPTIONThe AD7703 is a 20-bit A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low frequency signals such as those representing chemical,
physical or biological processes. It contains a charge-balancing
(sigma-delta) ADC, calibration microcontroller with on-chip
static RAM, a clock oscillator and a serial communications port.
The analog input signal to the AD7703 is continuously sampled
at a rate determined by the frequency of the master clock,
CLKIN. A charge-balancing A/D converter (sigma-delta modu-
lator) converts the sampled signal into a digital pulse train
whose duty cycle contains the digital information. A six-pole
Gaussian digital low-pass filter processes the output of the
sigma-delta modulator and updates the 20-bit output register at
a 4 kHz rate. The output data can be read from the serial port
randomly or periodically at any rate up to 4 kHz.
Figure 7. Typical System Connection Diagram
The AD7703 can perform self-calibration using the on-chip
calibration microcontroller and SRAM to store calibration
parameters. A calibration cycle may be initiated at any time
using the CAL control input.
Other system components may also be included in the
calibration loop to remove offset and gain errors in the input
channel.
For battery operation, the AD7703 also offers a standby mode
that reduces idle power consumption to typically 10 μW.
AD7703
DIGITAL FILTERINGThe AD7703’s digital filter behaves like an analog filter, with a
few minor differences.
First, since digital filtering occurs after the A to D conversion
process, it can remove noise injected during the conversion
process. Analog filtering cannot do this.
On the other hand, analog filtering can remove noise superim-
posed on the analog signal before it reaches the ADC. Digital
filtering cannot do this and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
and digital filter, even though the average value of the signal is
within limits. To alleviate this problem, the AD7703 has over-
range headroom built into the sigma-delta modulator and digital
filter which allows overrange excursions of 100 mV. If noise sig-
nals are larger than this, consideration should be given to analog
input filtering, or to reducing the gain in the input channel so
that a full-scale input (2.5 V) gives only a half-scale input to the
AD7703 (1.25 V). This will provide an overrange capability
greater than 100% at the expense of reducing the dynamic range
by 1 bit (50%).
FILTER CHARACTERISTICSThe cutoff frequency of the digital filter is fCLK/409600. At the
maximum clock frequency of 4.096 MHz, the cutoff frequency
of the filter is 10 Hz and the data update rate is 4 kHz.
Figure 9 shows the filter frequency response. This is a 6-pole
Gaussian response that provides 55 dB of 60 Hz rejection for a
10 Hz cutoff frequency. If the clock frequency is halved to give a
5 Hz cutoff, 60 Hz rejection is better than 90 dB.
Figure 9. Frequency Response of AD7703 Filter
Since the AD7703 contains this low-pass filtering, there is a set-
tling time associated with step function inputs, and data will be
invalid after a step change until the settling time has elapsed.
The AD7703 is, therefore, unsuitable for high speed multiplex-
ing, where channels are switched and converted sequentially at
high rates, as switching between channels can cause a step
change in the input. However, slow multiplexing of the AD7703
is possible, provided that the settling time is allowed to elapse
before data for the new channel is accessed.
The output settling of the AD7703 in response to a step input
change is shown in Figure 10. The Gaussian response has fast
settling with no overshoot, and the worst-case settling time to
±0.0007% is 125 ms with a 4.096 MHz master clock frequency.
USING THE AD7703
SYSTEM DESIGN CONSIDERATIONSThe AD7703 operates differently from successive approxima-
tion ADCs or integrating ADCs. Since it samples the signal con-
tinuously, like a tracking ADC, there is no need for a start convert
command. The 20-bit output register is updated at a 4 kHz rate,
and the output can be read at any time, either synchronously or
asynchronously.
CLOCKINGThe AD7703 requires a master clock input, which may be an
external TTL/CMOS compatible clock signal applied to the
CLKIN pin (CLKOUT not used). Alternatively, a crystal of the
correct frequency can be connected between CLKIN and
CLKOUT, when the clock circuit will function as a crystal
controlled oscillator.
Figure 11 shows a simple model of the on-chip gate oscillator
and Table II gives some typical capacitor values to be used with
various resonators.
