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AD7701
16-Bit Sigma-Delta ADC
REV.D
2MOS
16-Bit A/D Converter
FEATURES
Monolithic 16-Bit ADC
0.0015% Linearity Error
On-Chip Self-Calibration Circuitry
Programmable Low-Pass Filter
0.1 Hz to 10 Hz Corner Frequency
0 Vto +2.5 V or 62.5 V Analog Input Range
4 kSPS Output Data Rate
Flexible Serial Interface
Ultralow Power
APPLICATIONS
Industrial Process Control
Weigh Scales
Portable Instrumentation
Remote Data Acquisition
GENERAL DESCRIPTIONThe AD7701 is a 16-bit ADC which uses a sigma-delta conver-
sion technique. The analog input is continuously sampled by an
analog modulator whose mean output duty cycle is proportional
to the input signal. The modulator output is processed by an
on-chip digital filter with a six-pole Gaussian response, which
updates the output data register with 16-bit binary words at
word rates up to 4 kHz. The sampling rate, filter corner fre-
quency and output word rate are set by a master clock input
that may be supplied externally, or by a crystal-controlled on-
chip clock oscillator.
The inherent linearity of the ADC is excellent, and endpoint
accuracy is ensured by self-calibration of zero and full scale
which may be initiated at any time. The self-calibration scheme
can also be extended to null system offset and gain errors in the
input channel.
The output data is accessed through a flexible serial port, which
has an asynchronous mode compatible with UARTs and two
synchronous modes suitable for interfacing to shift registers or
the serial ports of industry-standard microcontrollers.
CMOS construction insures low power dissipation, and a power
down mode reduces the idle power consumption to only 10 μW.
PRODUCT HIGHLIGHTSThe AD7701 offers 16-bit resolution coupled with outstand-
ing 0.0015% accuracy.No missing codes ensures true, usable, 16-bit dynamic range,
removing the need for programmable gain and level-setting
circuitry.The effects of temperature drift are eliminated by on-chip
self-calibration, which removes zero and gain error. External
circuits can also be included in the calibration loop to
remove system offsets and gain errors.A flexible synchronous/asynchronous interface allows the
AD7701 to interface directly to UARTs or to the serial ports
of industry-standard microcontrollers.Low operating power consumption and an ultralow power
standby mode make the AD7701 ideal for loop-powered
remote sensing applications, or battery-powered portable
instruments.
FUNCTIONAL BLOCK DIAGRAM
(TA = +258C; AVDD = DVDD = +5 V; AVSS = DVSS = –5 V; VREF = +2.5 V; fCLKIN =
4.096MHz; Bipolar Mode: MODE = +5 V; AIN Source Resistance = 1k V1 with 1 nF to
AGND at AIN, unless otherwise noted.)AD7701–SPECIFICATIONS
NOTES
11The AIN pin presents a very high impedance dynamic load which varies with clock frequency.
12Temperature ranges are as follows: A, B Versions; –40°C to +85°C; S, T Versions; –55°C to +125°C.
13Apply after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges.
14Total drift over the specified temperature range since calibration at power-up at +25°C. This is guaranteed by design and/or characterization. Recalibration at any
temperature will remove these errors.
15In unipolar mode the offset can have a negative value (–VREF) such that the unipolar mode can mimic bipolar mode operation.
16The specifications for input overrange and for input span apply additional constraints on the offset calibration range.
17For unipolar mode, input span is the difference between full scale and zero scale. For bipolar mode, input span is the difference between positive and negative
full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ±(VREF +0.1)
18All digital outputs unloaded. All digital inputs at 5 V CMOS levels.
19Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter.
10CLKIN is stopped. All digital inputs are grounded.
Specifications subject to change without notice.
AD7701
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this device features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DVDD to AVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
DVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD +0.3 V
Analog Input
Voltage to AGND . . . . . . . . AVSS – 0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . ±10 mA
Operating Temperature Range
Commercial Plastic (A, B Versions) . . . . . –40°C to +85°C
Industrial Cerdip (A, B Versions) . . . . . . . –40°C to +85°C
Extended Cerdip (S, T Versions) . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
AD7701
ORDERING GUIDE
PIN FUNCTION DESCRIPTION4, 17
6DVSS
DIP, Cerdip, SOIC
MODE
SC1
DGND
CLKOUT
CLKIN
AGND
DVSS
AVSS
AIN
VREF
SDATA
SCLK
SC2
CAL
AVDD
DVDD
DRDY
BP/UP
SLEEP
SSOP
MODE
SC1
DGND
CLKOUT
CLKIN
AGND
DVSS
AVSS
SDATA
SCLK
SC2
CAL
AVDD
DVDD
DRDY
PIN CONFIGURATIONS
TIMING CHARACTERISTICS1, 2SSC Mode
t11
t12
t13
t15
AC Mode
t17
NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.See Figures 1 to 6.CLKIN Duty Cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7701 is not in SLEEP mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.The AD7701 is production tested with fCLKIN at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.Specified using 10% and 90% points on waveform of interest.In order to synchronize several AD7701s together using the SLEEP pin, this specification is met.t4 and t13 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.t9, t10, t15 and t16 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is
then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the
true bus relinquish time of the part and as such as independent of external bus loading capacitance.If CS is returned high before all 16 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be as
great as 4 CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high sooner than
4 CLKIN cycles plus 160 ns after CS goes low.SDATA is clocked out on the falling edge of the SCLK input.
(AVDD = DVDD = +5 V 6 10%; AVSS = DVSS = –5 V 6 10%; AGND = DGND = O V;
fCLKIN = 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DVDD)
AD7701
1.6mA
200mA
100pF
OUTPUT
PIN
IOH
2.1V+
IOLFigure 1.Load Circuit for Access
Time and Bus Relinquish Time
SDATAFigure 3.SSC Mode Data Hold
Time
Figure 2a.Calibration Control Timing
SDATAFigure 4a.SEC Mode Data Hold Time
TERMINOLOGY
LINEARITY ERRORThis is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are Zero-Scale (not to be
confused with Bipolar Zero), a point 0.5 LSB below the first
code transition (000 . . . 000 to 000 . . . 001) and Full-Scale, a
point 1.5 LSB above the last code transition (111 . . . 110 to
111 . . . 111). The error is expressed as a percentage of full
scale.
DIFFERENTIAL LINEARITY ERRORThis is the difference between any code’s actual width and the
ideal (1 LSB) width. Differential Linearity Error is expressed in
LSBs. A differential linearity specification of ±1 LSB or less
guarantees monotonicity.
POSITIVE FULL-SCALE ERRORPositive Full-Scale Error is the deviation of the last code
transition (111 . . . 110 to 111 . . . 111) from the ideal (VREF
–3/2 LSBs). It applies to both positive and negative analog input
ranges and it is expressed in microvolts.
BIPOLAR ZERO ERRORThis is the deviation of the midscale transition (0111 . . . 111 to
1000 . . . 000) from the ideal (AGND – 0.5 LSB) when
operating in the bipolar mode. It is expressed in microvolts.
BIPOLAR NEGATIVE FULL-SCALE ERRORThis is the deviation of the first code transition from the ideal
(–VREF + 0.5 LSB), when operating in the bipolar mode. It is
expressed in microvolts.
POSITIVE FULL-SCALE OVERRANGEPositive Full-Scale Overrange is the amount of overhead avail-
able to handle input voltages greater than +VREF ( for example,
noise peaks or excess voltages due to system gain errors in
system calibration routines) without introducing errors due to
overloading the analog modulator or overflowing the digital
filter. It is expressed in millivolts.
NEGATIVE FULL-SCALE OVERRANGEThis is the amount of overhead available to handle voltages
below –VREF without overloading the analog modulator or
Figure 5.SSC Mode Timing Diagram
Figure 6.
The AD7701 can perform self-calibration using the on-chip
calibration microcontroller and SRAM to store calibration
parameters. A calibration cycle may be initiated at any time
using the CAL control input.
Other system components may also be included in the
calibration loop to remove offset and gain errors in the input
channel.
For battery operation, the AD7701 also offers a standby mode
that reduces idle power consumption to typically 10 μW.
THEORY OF OPERATIONThe general block diagram of a sigma-delta ADC is shown in
Figure 8. It contains the following elements.A sample-hold amplifier.A differential amplifier or subtracter.An analog low-pass filter.A 1-bit A/D converter (comparator).A 1-bit DAC.A digital low-pass filter.
In operation, the analog signal sample is fed to the subtracter,
along with the output of the 1-bit DAC. The filtered difference
signal is fed to the comparator, whose output samples the
difference signal at a frequency many times that of the analog
signal sampling frequency (oversampling).
Oversampling is fundamental to the operation of sigma-delta
ADCs. Using the quantization noise formula for an ADC:
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
The AD7701 samples the input signal at 16 kHz, which spreads
the quantization noise from 0 to 8 kHz. Since the specified
analog input bandwidth of the AD7701 is only 0 to 10 Hz, the
noise energy in this bandwidth would be only 1/800 of the total
quantization noise, even if the noise energy was spread evenly
throughout the spectrum. It is reduced still further by analog
filtering in the modulator loop, which shapes the quantization
noise spectrum to move most of the noise energy to frequencies
above 10 Hz. The SNR performance in the 0 to 10 Hz range is
conditioned to the 16-bit level in this fashion.
The output of the comparator provides the digital input for the
1-bit DAC, so that the system functions as a negative feedback
loop that tries to minimize the difference signal. The digital data
that represents the analog input voltage is contained in the duty
cycle of the pulse train appearing at the output of the compara-
OFFSET CALIBRATION RANGEIn the system calibration modes (SC2 low) the AD7701
calibrates its offset with respect to the AIN pin. The Offset
Calibration Range specification defines the range of voltages,
expressed as a percentage of VREF that the AD7701 can accept
and still calibrate offset accurately.
FULL-SCALE CALIBRATION RANGEThis is the range of voltages that the AD7701 can accept in the
system calibration mode and still calibrate full-scale correctly.
INPUT SPANIn system calibration schemes, two voltages applied in sequence
to the AD7701’s analog input define the analog input range.
The input span specification defines the minimum and maxi-
mum input voltages from zero to full-scale that the AD7701 can
accept and still calibrate gain accurately. The input span is ex-
pressed as a percentage of VREF.
GENERAL DESCRIPTIONThe AD7701 is a 16-bit A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low frequency signals such as those representing chemical,
physical or biological processes. It contains a charge-balancing
(sigma-delta) ADC, calibration microcontroller with on-chip
static RAM, a clock oscillator and a serial communications port.
The analog input signal to the AD7701 is continuously sampled
at a rate determined by the frequency of the master clock,
CLKIN. A charge-balancing A/D converter (Sigma-Delta
Modulator) converts the sampled signal into a digital pulse train
whose duty cycle contains the digital information. A six-pole
Gaussian digital low-pass filter processes the output of the
modulator and updates the 16-bit output register at a 4 kHz
rate. The output data can be read from the serial port randomly
or periodically at any rate up to 4 kHz.
AD7701
FILTER CHARACTERISTICSThe cutoff frequency of the digital filter is fCLK /409600. At the
maximum clock frequency of 4.096 MHz, the cutoff frequency
of the filter is 10 Hz and the output rate is 4 kHz.
Figure 10 shows the filter frequency response. This is a 6-pole
Gaussian response that provides 55 dB of 60 Hz rejection for a
10 Hz cutoff frequency. If the clock frequency is halved to give a
5 Hz cutoff, 60 Hz rejection is better than 90 dB. A normalized
s-domain pole-zero plot of the filter is shown in Figure 11.
The response of the filter is defined by:
H(x) = [1+ 0.693x2 + 0.240x4 + 0.0555x6 + 0.00962x8
+ 0.00133x10 + 0.000154x12] –0.5
where:
x = f/f3 dB, f3 dB = fCLKIN/409600,
and
f is the frequency of interest.
Figure 11. Normalized Pole-Zero Plot of AD7701 Filter
Since the AD7701 contains this on-chip, low-pass filtering,
there is a settling time associated with step function inputs, and
data will be invalid after a step change until the settling time has
elapsed. The AD7701 is therefore unsuitable for high speed
multiplexing, where channels are switched and converted se-
quentially at high rates, as switching between channels can
cause a step change in the input. Rather, it is intended for dis-
tributed converter systems using one ADC per channel.
Sigma-delta ADCs are generally described by the order of the
analog low-pass filter. A simple example of a first order sigma-
delta ADC is shown in Figure 9. This contains only a first-order
low-pass filter or integrator. It also illustrates the derivation of
the alternative name for these devices: Charge-Balancing ADCs.
Figure 9.SEC Basic Charge-Balancing ADC
The term charge-balancing comes from the fact that this system
is a negative feedback loop that tries to keep the net charge on
the integrator capacitor at zero, by balancing charge injected by
the input voltage with charge injected by the 1-bit DAC. When
the analog input is zero, the only contribution to the integrator
output comes from the 1-bit DAC. For the net charge on the
integrator capacitor to be zero, the DAC output must spend half
its time at +1 V and half its time at –1 V. Assuming ideal
components, the duty cycle of the comparator will be 50%.
When a positive analog input is applied, the output of the 1-bit
DAC must spend a larger proportion of the time at +1 V, so the
duty cycle of the comparator increases. When a negative input
voltage is applied, the duty cycle decreases.
The AD7701 uses a second-order sigma-delta modulator and a
sophisticated digital filter that provides a rolling average of the
sampled output. After power-up or if there is a step change in
the input voltage, there is a settling time that must elapse before
valid data is obtained.
DIGITAL FILTERINGThe AD7701’s digital filter behaves like a similar analog filter,
with a few minor differences.
First, since digital filtering occurs after the A to D conversion
process, it can remove noise injected during the conversion
process. Analog filtering cannot do this.
On the other hand, analog filtering can remove noise super-
imposed on the analog signal before it reaches the ADC. Digital
filtering cannot do this and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
and digital filter, even though the average value of the signal is
within limits. To alleviate this problem, the AD7701 has over-
range headroom built into the sigma-delta modulator and digital
filter which allows overrange excursions of 100 mV. If noise
signals are larger than this, consideration should be given to
analog input filtering, or to reducing the gain in the input
channel so that a full-scale input (2.5 V) gives only a half-scale
