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AD768AR-REEL-AD768ARZ
16-Bit, 30 MSPS D/A Converter
FUNCTIONAL BLOCK DIAGRAM
(MSB)
DB15
DB0
(LSB)
CLOCKNCREFCOMREFOUTIREFINNR
VEE
LADCOM
IOUTB
IOUTA
DCOMVDD
REV.B
FEATURES
30 MSPS Update Rate
16-Bit Resolution
Linearity:1/2 LSB DNL @ 14 Bits
1 LSB INL @ 14 Bits
Fast Settling: 25ns Full-Scale Settling to 0.025%
SFDR @ 1MHz Output: 86dBc
THD @ 1 MHz Output: 71 dBc
Low Glitch Impulse: 35pV-s
Power Dissipation: 465mW
On-Chip 2.5V Reference
Edge-Triggered Latches
Multiplying Reference Capability
APPLICATIONS
Arbitrary Waveform Generation
Communications Waveform Reconstruction
Vector Stroke Display
16-Bit, 30MSPS
D/A Converter
PRODUCT DESCRIPTION
The AD768 is a 16-bit, high speed digital-to-analog converter
(DAC) that offers exceptional ac and dc performance. The
AD768 is manufactured on ADI’s Advanced Bipolar CMOS
(ABCMOS) process, combining the speed of bipolar transistors,
the accuracy of laser-trimmable thin film resistors, and the effi-
ciency of CMOS logic. A segmented current source architecture
is combined with a proprietary switching technique to reduce
glitch energy and maximize dynamic accuracy. Edge triggered
input latches and a temperature compensated bandgap reference
have been integrated to provide a complete monolithic DAC
solution.
The AD768 is a current-output DAC with a nominal full-scale
output current of 20mA and a 1kΩ output impedance. Differ-
ential current outputs are provided to support single-ended
or differential applications. The current outputs may be tied
directly to an output resistor to provide a voltage output, or fed
to the summing junction of a high speed amplifier to provide a
buffered voltage output. Also, the differential outputs may be
interfaced to a transformer or differential amplifier.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD768 can be driven by
the on-chip reference or by a variety of external reference volt-
ages based on the selection of an external resistor. An external
capacitor allows the user to optimally trade off reference band-
width and noise performance.
The AD768 operates on ±5V supplies, typically consuming
465mW of power. The AD768 is available in a 28-pin SOIC
package and is specified for operation over the industrial tem-
perature range.
PRODUCT HIGHLIGHTSThe low glitch and fast settling time provide outstanding
dynamic performance for waveform reconstruction or digital
synthesis requirements, including communications.The excellent dc accuracy of the AD768 makes it suitable for
high speed A/D conversion applications.On-chip, edge-triggered input CMOS latches interface
readily to CMOS logic families. The AD768 can support up-
date rates up to 40 MSPS.A temperature compensated, 2.5V bandgap reference is
included on-chip allowing for generation of the reference
input current with the use of a single external resistor. An ex-
ternal reference may also be used.The current output(s) of the AD768 may be used singly or
differentially, either into a load resistor, external op amp
summing junction or transformer.Proper selection of an external resistor and compensation
capacitor allow the performance-conscious user to optimize
the AD768 reference level and bandwidth for the target
application.
AD768–SPECIFICATIONS
Monotonicity (13-Bit)GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE
ANALOG OUTPUT
REFERENCE OUTPUT
TEMPERATURE COEFFICIENTS
DIGITAL INPUTS
AC LINEARITY
(TMIN to TMAX , VDD = +5.0 V, VEE = –5.0 V, LADCOM, REFCOM, DCOM = 0 V, IREFIN = 5 mA,
CLOCK = 10MHz, unless otherwise noted)
NOTESMeasured at IOUTA, driving a virtual ground.Nominal FS output current is 4× the current at IREFIN. Therefore, nominal FS current is 20mA when IREFIN = 5mA.Output current is defined as total current available for IREFIN and any external load.Reference bandwidth is a function of external cap at NR pin. Refer to compensation section of data sheet for details.Excludes internal reference drift.Includes internal reference drift.Measured as unbuffered voltage output (1V range) with FS current into 50Ω load at IOUTB.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Reference Input Current (IREFIN)
Digital Inputs (DB0–DB15, CLOCK)
Analog Outputs (IOUTA, IOUTB)
Maximum Junction Temperature
Storage Temperature
*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating for extended periods may affect device
reliability.
AD768
ORDERING GUIDE
Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD768 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD768
WAFER TEST LIMITS1
NOTESElectrical test are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal
yield loss, yield after packaging is not guaranteed for standard product dice.Limits extrapolated from testing of individual bit errors.Die offers latch control pad. Edge triggered latches become level triggered when latch control and clock pads are high.Die substrate is connected to VEE.
PIN DESCRIPTIONS
Type: AI = Analog Input; DI = Digital Input; AO = Analog Output; P = Power.
(TA = +258C, VDD = +5.0 V, VEE = –5.0 V, IREFIN = 5 mA, unless otherwise noted)
DICE CHARACTERISTICS3, 4
PIN CONFIGURATION
NC = NO CONNECT
IOUTA
VDD (+5V)
VEE (–5V)
IOUTB
LADCOM
REFOUT
DB13
DB14
DB15 (MSB)REFCOM
IREFIN
(LSB) DB0
DB1
DB2
DB3DB10
DB11
DB12
DB4
DB5
DB6
DB7
DB9
DCOM
CLOCK
DB8
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is re-
ported in ppm per degree C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the
input signal and the peak spurious signal over the specified
bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal. It is ex-
pressed as a percentage or in decibels (dB).
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients which are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-sec.
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the ac-
tual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalizedfullscale,associatedwith a1LSBchangeindigitalinput code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s. The ideal
outputcurrentspan is4×thecurrent applied to the IREFIN pin.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
CREFCOMP
+5V
–5V
IOUTA
IOUTB192013141718789101112CLOCK
DB15DB14DB13
DB12DB11DB10
DB9DB8
DB7
DB6DB5DB4
DB3DB2DB1DB0
Figure 1.Functional Block Diagram and Basic Hookup
FUNCTIONAL DESCRIPTION
The AD768 is a current-output DAC with a nominal full-scale
current of 20mA and a 1kΩ output impedance. Differential
outputs are provided to support single-ended or differential
applications. The DAC architecture combines segmented cur-
rent sources for the top four bits (MSBs) and a 1kΩ R-2R lad-
der for the lower 12 bits (LSBs). The DAC current sources are
implemented with laser-trimmable thin film resistors for excel-
lent dc linearity. A proprietary switching technique is utilized to
The digital interface offers CMOS compatible edge-triggered
input latches that interface readily to CMOS logic and supports
clock rates up to 40MSPS. A temperature compensated 2.5V
bandgap reference is integrated on-chip to drive the AD768 ref-
erence input current with the use of a single external resistor.
The functional block diagram in Figure 1 is a simple representa-
tion of the internal circuitry to aid the understanding of the
AD768’s operation. The DAC transfer function is described,
and followed by a detailed description of each key portion of the
AD768
Note the AD768 is optimized for operation at an input current
of 5mA. Both linearity and dynamic performance at other input
currents may be somewhat degraded. Figure 4 shows typical dc
linearity over a range of input currents. Figure 5 shows typical
SFDR (to Nyquist) performance over a range of input currents
and CLOCK input rates for a 1 MHz output frequency.
ERROR – LSB
IREFIN – mA1.02.03.04.05.0INL
DNL
Figure 4.INL/DNL vs. IREFIN Current
SFDR – dB
CLOCK = 10 MSPS
CLOCK = 20 MSPS
CLOCK = 30 MSPS
CLOCK = 40 MSPS
DAC TRANSFER FUNCTION
The AD768 may be used in either current-output mode with the
output connected to a virtual ground, or voltage-output mode
with the output connected to a resistive load.
In current output mode,
IOUT = (DAC CODE/65536) × (IREFIN × 4)
In voltage output mode,
VOUT = IOUT × RLOADiRLAD
where:
DAC CODE is the decimal representation of the DAC inputs;
an integer between 0 and 65535.
IREFIN is the current applied at the IREFIN pin, determined by
VREF/RREF.
Substituting for IOUT and IREFIN,
VOUT= –VREF × (DAC CODE/65536) × 4 × [(RLOADiRLAD)/RREF]
These equations clarify an important aspect of the AD768
transfer function; the full-scale current output of the DAC is
proportional to a current input. The voltage output is then a
function of the ratio of (RLOADiRLAD)/RREF, allowing for cancel-
lation of resistor drift by selection of resistors with matched
characteristics.
REFERENCE INPUT
The IREFIN pin is a current input node with low impedance to
REFCOM. This input current sets the magnitude of the DAC
current sources such that the full-scale output current is exactly
four times the current applied at IREFIN. For the nominal in-
put current of 5mA, the nominal full-scale output current ismA.
The 5mA reference input current can be generated from the
on-chip 2.5V reference with an external resistor of 500 Ω from
REFOUT to IREFIN. If desired, a variety of external reference
voltages may be used based on the selection of an appropriate
resistor. However, to maintain stability of the reference ampli-
fier, the external impedance at IREFIN must be kept below
1kΩ.
REFCOM
IREFIN
VEEVEE
Figure 2.Equivalent Reference Input Circuit
The IREFIN current can be varied from 1 mA to 7 mA which
subsequently will result in a proportional change in the DAC
full-scale. Since the operating currents within the DAC vary
with IREFIN, so does the power dissipation. Figure 3 illustrates
that relationship.
REFERENCE OUTPUT
The internal 2.5V bandgap reference is provided for generation
of the IREFIN current, and must be compensated externally with
a capacitor of 0.1μF or greater from REFOUT to REFCOM. If
an external reference is used, REFOUT should be tied directly
to the positive supply voltage, VDD. This effectively turns off the
internal reference, eliminating the need for the external capaci-
tor at REFOUT. The reference is specified to drive a nominal
load of 5mA with a maximum of 15mA. Operation with a
heavier load will result in degradation of supply rejection and
reference voltage accuracy. Therefore, the reference output
should be buffered with an amplifier when additional load cur-
rent is required. A properly sized pull-up resistor can also be
used to source additional current to the load. The resistors value
should be selected such that REFOUT will always source a
minimum of 5 mA to IREFIN and the additional load.
CREFCOMP
1µF
Figure 6.Typical Reference Hookup
TEMPERATURE CONSIDERATIONS
Note that the reference plays a key role in the overall tempera-
ture performance of the AD768. Any drift of IREFIN shows up
directly in IOUT. When the output is taken as a current, the drift
of IREFIN (which depends on both VREF and RREF) must be mini-
mized. This can be done by using the internal temperature com-
pensated reference for VREF and a low temperature coefficient
resistor for RREF. If the output is taken as a voltage, it is a func-
tion of a resistor ratio, not an absolute resistor value. By select-
ing resistors with matched temperature coefficients for RREF
and RLOAD, the drift in the resistor values will cancel, providing
optimal drift performance.
REFERENCE NOISE REDUCTION AND MULTIPLYING
BANDWIDTH
For application flexibility and multiplying capabilities, the refer-
ence amplifier is designed to offer adjustable bandwidth that can
be reduced by connecting an external capacitor from the NR
node to the negative supply pin, VEE. This capacitor limits the
bandwidth and acts as a filter to reduce the noise contribution
from the reference amplifier.
The noise reduction capacitor, CNR, is not required for stability
and does not affect the settling time of the DAC output. With-
out this capacitor, the IREFIN bandwidth is 15MHz allowing
high frequency modulation of the DAC full-scale range through
the reference input node. Figure 7 shows the relationship be-
tween the external noise reduction capacitor and the –3 dB
bandwidth of the reference amplifier.
Figure 7.External Noise Reduction Capacitor vs. –3 dB
Bandwidth
The sensitivity of the NR node requires that care be taken in
capacitor placement. The capacitor should be located as physi-
cally close to the package pins as possible and lead lengths
should be minimized. For this purpose, the use of a chip
capacitor is recommended. For applications that do not require
high frequency modulation at IREFIN, it is recommended that
a capacitor on the order of 1μF be connected from NR to VEE.
If the reference input is purely dc, noise may be minimized with
multiple capacitors, such as 1μF and 0.1μF, to more effectively
filter both high and low frequency disturbances.
ANALOG OUTPUTS
The AD768 offers two analog outputs; IOUTA is trimmed for
optimal INL and DNL performance and has a full-scale output
when all bits are high. For applications that require the specified
dc accuracy, IOUTA should be used. IOUTB is the comple-
mentary output with full-scale output when all bits are low.
Both IOUTA and IOUTB provide similar dynamic perfor-
mance. Refer to Figures 8 and 9 for typical INL and DNL per-
formance curves. The outputs can also be used differentially.
Refer to the section “Applying the AD768” for examples of vari-
ous output configurations.
AD768
DIGITAL INPUT CODE – k06510203040
DNL ERROR – LSB6051525354555
Figure 9.Typical DNL Performance
The outputs have a compliance range of –1.2V to +5.0V with
respect to LADCOM. The current steering output stages will
remain functional over this range. Operation beyond the maxi-
mum compliance limits may cause either output stage saturation
or breakdown, resulting in nonlinear performance. The rated dc
and ac performance specifications are for an output voltage of
0 V to –1 V.
The current in LADCOM is proportional to IREFIN and has been
carefully configured to be independent of digital code when the
output is connected to a virtual ground. This minimizes any det-
rimental effects of ladder ground resistance on linearity. For
optimal dc linearity, IOUTA should be connected directly to a
virtual ground, and IOUTB should be grounded. An example of
this configuration is provided in the section “Buffered Voltage
Output.” If IOUTA is driving a resistive load directly, then
IOUTB should be terminated with an equal impedance. This
will ensure the current in LADCOM remains constant with digi-
tal code, and is recommended for improved dc linearity in the
unbuffered voltage output configuration.
As shown in Figure 10, there is an equivalent output impedance
of 1kΩ in parallel with 3pF at each output terminal. If the out-
put voltage deviates from the ladder common voltage, an error
current flows through this 1kΩ impedance. This is a linear effect
which does not change with input code, so it appears as a gain
error. With 50Ω output termination, the resulting gain error is
approximately –5%. An example of this configuration is pro-
vided in the section Unbuffered Voltage Output.
Figure 10.Equivalent Analog Output Circuit
DIGITAL INPUTS
The AD768 digital inputs consist of 16 data input pins and a
clock pin. The 16-bit parallel data inputs follow standard posi-
tive binary coding, where DB15 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). IOUTA pro-
duces full-scale output current when all data bits are at logic 1.
IOUTB is the complementary output, with full-scale when all
data bits are at logic 0. The full-scale current is split between
the two outputs as a function of the input code.
The digital interface is implemented using an edge-triggered
master slave latch. The DAC output is updated following the
rising edge of the clock, and is designed to support a clock rate
as high as 40MSPS. The clock can be operated at any duty
cycle that meets the specified minimum latch pulse width. The
setup and hold times can also be varied within the clock cycle as
long as the specified minimums are met, although the location
of these transition edges may affect digital feedthrough. The
digital inputs are CMOS compatible with logic thresholds set to
approximately half the positive supply voltage. The small input
current requirements allow for easy interfacing to unbuffered
CMOS logic. Figure 11 shows the equivalent digital input
circuit.
VCC
VEE
DIGITAL
INPUT
VCC
DCOM
Figure 11.Equivalent Digital Input Circuit
Digital input signals to the DAC should be isolated from the
analog output as much as possible. Interconnect distances to the
DAC inputs should be kept as short as possible. Termination
resistors may improve performance if the digital lines become
too long. To minimize digital feedthrough, the inputs should be
free from glitches and ringing, and may be further improved
with a reduction of edge speed.
Figure 14.Rise and Fall
Characteristics
Figure 17.Typical SFDR
(With a Window)
FREQUENCY – Hz
OUTPUT – dB
–20
Figure 20.Intermodulation
Distortion
OUTPUT – V
TIME – 2ns/Div
Figure 13.Glitch Impulse at Major
Carry0.13241
OUTPUT – dB
FREQUENCY – MHz
–100
Figure 16.Typical Spectral
Performance
FREQUENCY – MHz
THD – dB
–70
Figure 19.THD vs. FOUT
Figure 12.Settling Time
FREQUENCY – MHz
THD – dB
–707891030
Figure 15.THD vs. Clock Frequency
at FOUT = 1 MHz10
FREQUENCY – MHz
SFDR
Figure 18.SFDR (Within a Window)
vs. FOUT
OUTPUT – dB
ERROR BAND – %
TIME – ns
AD768
APPLYING THE AD768
OUTPUT CONFIGURATIONS
The following sections illustrate some typical output configura-
tions for the AD768. While most figures take the output at
IOUTA, IOUTB can be interchanged in all cases. Unless other-
wise noted, it is assumed that IREFIN and full-scale currents are
set to nominal values.
For application that require the specified dc accuracies, proper
resistor selection is required. In addition to absolute resistor tol-
erances, resistor self-heating can result in unexpected errors. For
optimal INL, the buffered voltage output is recommended as
shown in Figure 23. In this configuration, self-heating of RFB
may cause a change in gain, producing a bow in the INL curve.
This effect can be minimized by selection of a low temperature
coefficient resistor.
UNBUFFERED VOLTAGE OUTPUT CONFIGURATIONS
Figure 21 shows the AD768 configured to provide a unipolar
output range of approximately 0V to –1V. The nominal full-
scale current of 20mA flows through the parallel combination
of the 50Ω RL resistor and the 1kΩ DAC output resistance
(from the R-2R ladder), for a combined 47.6Ω. This produces
an ideal full-scale voltage of –0.952V with respect to LADCOM.
In addition, the 1kΩ DAC output resistance has a tolerance of20% which may vary the full-scale gain by ±1%. This linear
variation results in a gain error which can be easily compensated
for by adjusting IREFIN.
Figure 21.0V to –1V Unbuffered Voltage Output
In this configuration, it is important to note the restrictions from
the output compliance limits. The maximum negative voltage
compliance is –1.2V, prohibiting use of a 100Ω load to produce
a 0V to –2V output swing. One additional consideration for
operation in this mode is integral nonlinearity. As the voltage at
the output node changes, the finite output impedance of the
DAC current steering switches gives rise to small changes in the
output current that vary with output voltage, producing a bow
(up to 8 LSBs) in the INL. For optimal INL performance, the
buffered voltage output mode is recommended.
The INL is also slightly dependent on the termination of the
unused output (IOUTB) as described in the ANALOG OUT-
PUT section. To eliminate this effect, IOUTB should be termi-
nated with the same impedance as IOUTA, so both outputs see
the same resistive divider to ground. This will keep the current
in LADCOM constant, minimizing any code-dependent IR
drops within the DAC ladder that may give rise to additional
nonlinearities.
AC-Coupled Output
Configuring the output as shown in Figure 22 provides a bipolar
DAC output is the parallel combination of the AD768’s output
impedance, RL, and bias resistor RB. The nominal output swing
with the values given in Figure 22 is ±0.5V assuming RB >> RL.
The gain of the circuit will be a function of the tolerances of the
impedances RLAD, RB, and RL.
Choosing the value of RB and C will depend primarily on the
desired –3dB high pass cutoff frequency and the bias current,
IB, of the subsequent stage connected to RB. The –3dB fre-
quency can be approximated by the equation,
f–3dB = 1/[2 × π × (RB + RLiRLAD) × C].
The dc offset of the output is a function of the bias current of
the subsequent stage and the value of RB. For example, if
C = 390pF, RB = 20kΩ, and IB = 1.0μA, the –3 dB frequency
is approximately 20.4 kHz and the dc offset would be 20mV.C
Figure 22.0.5V to –0.5V Unbuffered AC-Coupled Output
BUFFERED VOLTAGE OUTPUT CONFIGURATIONS
Unipolar Configuration
For positive output voltages, or voltage ranges greater than
allowed by output compliance limits, some type of external
buffer is needed. A wide variety of amplifiers may be selected
based on considerations such as speed, accuracy and cost. The
AD9631 is an excellent choice when dynamic performance is
important, offering low distortion up to 10MHz. Figure 23
shows the implementation of 0V to +2V full-scale unipolar
buffered voltage output. The amplifier establishes a summing
node at ground for the DAC output. The buffered output volt-
age results from the DAC output current flowing through the
amplifier’s feedback resistor, RFB. In this case, the 20mA full-
scale current across RFB (100Ω) produces an output voltage
range of 0V through +2V. The same configuration using a pre-
cision amplifier such as the AD845 is recommended for optimal
dc linearity.
Figure 23.Unipolar 0V to +2 V Buffered Voltage Output
Buffered Output Using a Current Divider
The configuration shown in Figure 23 may not be possible in
cases where the amplifier cannot supply the requisite 20mA
feedback current. As an alternative, Figure 24 shows amplifier
A1 in conjunction with a resistive current divider. The values of
RFF and RL are chosen to limit the current, I3, which must be

Partno	Mfg	Dc	Qty	Available	Descript
AD768AR-REEL \|AD768ARREEL	AD	N/a	828	avai	16-Bit, 30 MSPS D/A Converter
AD768ARZ	AD	N/a	200	avai	16-Bit, 30 MSPS D/A Converter
AD768ARZ	ADI	N/a	2	avai	16-Bit, 30 MSPS D/A Converter