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AD7688
500 kSPS 16- BIT Differential PulSAR® A/D Converter in µSOIC/QFN
16-Bit, 1.5 LSB INL, 500 kSPS PulSAR™
Differential ADC in MSOP/QFN
FEATURES
16-bit resolution with no missing codes
Throughput: 500 kSPS
INL: ±0.4 LSB typ, ±1.5 LSB max (±0.0023 % of FSR)
S/(N + D): 95 dB @ 20 kHz
THD: −115 dB @ 20 kHz
True differential analog input range: ±VREF
0 V to VREF with VREF up to VDD on both inputs
No pipeline delay
Single-supply 5V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI®/QSPI™/µWire/DSP compatible
Daisy chain multiple ADCs and BUSY indicator
Power dissipation
4 mW @ 5 V/100 kSPS,
4 µW @ 5 V/100 SPS
Stand-by current: 1 nA
Rev Pr I
10-lead package: MSOP (MSOP-8 size) and
QFN (LFCSP), 3 mm × 3 mm same space as SOT-23
Pin-for-pin compatible with the AD7685, AD7687, and
AD7686
APPLICATIONS
Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process control
APPLICATION DIAGRAM Figure 1.
Table 1. MSOP, QFN (LFCSP)/SOT-23 16-Bit PulSAR ADC
GENERAL DESCRIPTION The AD7688 is a 16-bit, charge redistribution successive
approximation, analog-to-digital converter (ADC) that operates
from a single 5V power supply, VDD. It contains a low power,
high speed, 16-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
aperture delay track-and-hold circuit. On the CNV rising edge,
it samples the voltage difference between IN+ and IN- pins. The
voltages on these pins usually swing in opposite phase between
0 V to REF. The reference voltage, REF, is applied externally and
can be set up to the supply voltage.
Its power scales linearly with throughput.
The SPI compatible serial interface also features the ability,
using the SDI input, to daisy chain several ADCs on a single 3-
wire bus and provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate
supply VIO.
The AD7688 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
TABLE OF CONTENTS
Specifications.....................................................................................3
Timing Specifications.......................................................................5
Absolute Maximum Ratings............................................................6
ESD Caution..................................................................................6
Pin Configuration and Function Descriptions.............................7
Terminology......................................................................................8
Typical Performance Characteristics.............................................9
Circuit Information....................................................................12
Converter Operation..................................................................12
Typical Connection Diagram...................................................13
Digital Interface..........................................................................17
Application Hints...........................................................................24
Layout..........................................................................................24
Evaluating the AD7688’s Performance....................................24
Outline Dimensions.......................................................................25
Ordering Guide..........................................................................26
REVISION HISTORY
5/04—Revision I: Preliminary
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted.
Table 2.
LSB means least significant bit. With the ±5 V input range, one LSB is 152.6 µV.
2 See section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. TerminologyAll specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
4 fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at −7 dB below full-scale.
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted.
Table 3.
With all digital inputs forced to VIO or GND as required.
2 During acquisition phase. Contact Analog Devices for extended temperature range.
TIMING SPECIFICATIONS
−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
Table 4. 1 See and for load conditions. Figure 2Figure 3
ABSOLUTE MAXIMUM RATINGS
Table 5.
1 See the Analog Input section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
500µAIOL
500µAIOH
1.4VTO SDO
50pF
02968-P
rH-002
Figure 2. Load Circuit for Digital Interface Timing
NOTES
1. 2V IF VIO ABOVE 2.5V, VIO– 0.5V IF VIO BELOW 2.5V.
2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
02968-P
rH-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4.10-Lead MSOP and QFN (LFCSP) Pin Configuration
Table 6. Pin Function Descriptions
AI = Analog Input, DI = Digital Input, DO = Digital Output, and P = Power
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs 1/2 LSB before
the first code transition. Positive full scale is defined as a level 1
1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line ). Figure 21
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Zero error is the difference between the ideal midscale voltage,
i.e., 0 V, from the actual voltage producing the midscale output
code, i.e., 0 LSB.
Gain Error
The first transition (from 100 . . . 00 to 100 . . . 01) should occur
at a level 1/2 LSB above the nominal negative full scale
(−4.999924 V for the ±5 V range). The last transition (from
011…10 to 011…11) should occur for an analog voltage 1 1/2
LSB below the nominal full scale (4.999771 V for the ±5 V
range.) The gain error is the deviation of the difference between
the actual level of the last transition and the actual level of the
first transition from the difference between the idea levels.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula ])02.676./dBDENOB
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in dB.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Transient Response
The time required for the ADC to accurately acquire its input
after a full-scale step function was applied.
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5. Integral Nonlinearity vs. Code
Figure 6. Histogram of a DC Input at the Code Center
Figure 7. FFT Plot
Figure 8. Differential Nonlinearity vs. Code
Figure 9. Histogram of a DC Input at the Code Center
Figure 10. S/[N + D] vs. Frequency
Figure 11. SNR vs. Temperature
Figure 12. THD vs. Frequency
Figure 13. THD, SFDR vs. Temperature
Figure 14. SNR and THD vs. Input Level
Figure 15. Operating Currents vs. Supply
Figure 16. Power-Down Currents vs. Temperature
Figure 17. Operating Currents vs. Temperature
Figure 18. Offset and Gain Error vs. Temperature
Figure 19. tDSDO vs. Capacitance Load and Supply
SW+
IN+
LSB
SWITCHES CONTROL
CNV
REF
GND
IN–
SW–
LSB2CCC
02968-P
rH-005
Figure 20. ADC Simplified Schematic
igure 20
CIRCUIT INFORMATION
The AD7688 is a fast, low power, single-supply, precise 16-bit
ADC using a successive approximation architecture.
The AD7688 is capable of converting 500,000 samples per
second (500 kSPS) and powers down between conversions.
When operating at 100 SPS, for example, it consumes typically
4µW, ideal for battery-powered applications.
The AD7688 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7688 is specified from 4.5 V to 5.5 V, and can be
interfaced to either 5 V, 3.3 V, 2.5 V, or 1.8 V digital logic. It is
housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that
combines space savings and allows flexible configurations.
It is pin-for-pin-compatible with the AD7685, AD7686, and
AD7687.
CONVERTER OPERATION
The AD7688 is a successive approximation ADC based on a
charge redistribution DAC. F shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN− captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each element
of the capacitor array between GND and REF, the comparator
input varies by binary weighted voltage steps (VREF/2, VREF/4 . . .
VREF/65536). The control logic toggles these switches, starting
with the MSB, in order to bring the comparator back into a
balanced condition. After the completion of this process, the
part returns to the acquisition phase and the control logic
generates the ADC output code and a BUSY signal indicator.
Because the AD7688 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Transfer Functions
The ideal transfer characteristic for the AD7688 is shown in
and . Figure 21
Figure 21. ADC Ideal Transfer Function
Table 7
Table 7. Output Codes and Ideal Input Voltages
02973-P
rH-
ADC CODE
(TWOS
COMP
NT)
ANALOG INPUT
+FS– 1.5 LSB–FS
–FS + 0.5 LSB 1 This is also the code for an overranged analog input (VIN+ – VIN above VREF –
VGND).
2 This is also the code for an underranged analog input (VIN+ – VIN below −VREF
+ VGND).
TYPICAL CONNECTION DIAGRAM Figure 22
shows an example of the recommended connection
diagram for the AD7688 when multiple supplies are available.
Analog Input Figure 23
Figure 23. Equivalent Analog Input Circuit
shows an equivalent circuit of the input structure of
the AD7688.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V because this will cause these diodes to become
forward-biased and start conducting current. However, these
diodes can handle a forward-biased current of 130 mA
maximum. For instance, these conditions could eventually
occur when the input buffer’s (U1) supplies are different from
VDD. In such a case, an input buffer with a short-circuit current
limitation can be used to protect the part.
This analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected,
as shown in , which represents the typical CMRR over
frequency.
Figure 24
Figure 24. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs IN+ and IN- can be modeled as a parallel combination of
capacitor C1 and the network formed by the series connection
of R1 and C2. C1 is primarily the pin capacitance. R1 is typically
600 Ω and is a lumped component made up of some serial
resistors and the on resistance of the switches. C2 is typically
30 pF and is mainly the ADC sampling capacitor. During the
conversion phase, where the switches are opened, the input
impedance is limited to C1. R1 and C2 make a 1-pole, low-pass
filter that reduces undesirable aliasing effect and limits the
noise.
When the source impedance of the driving circuit is low, the
AD7688 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency, as shown in Figure 25
Figure 25. THD vs. Analog Input Frequency and Source Resistance
