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AD7680BRM
100 kSPS, 16-Bit PulSAR® ADC in 6 Lead SOT-23
3 mW, 100 kSPS,
16-Bit ADC in 6-Lead SOT-23
Rev. 0
FEATURES
Fast throughput rate: 100 kSPS
Specified for VDD of 2.5 V to 5.5 V
Low power
3 mW typ at 100 kSPS with 2.5 V supply
3.9 mW typ at 100 kSPS with 3 V supply
16.7 mW typ at 100 kSPS with 5 V supply
Wide input bandwidth
86 dB SNR at 10 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI®/QSPI™/µWire/DSP compatible
Standby mode: 0.5 µA max
6-Lead SOT-23 and 8-Lead MSOP packages
APPLICATIONS
Battery-powered systems:
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Remote data acquisition systems
High speed modems
Optical sensors
FUNCTIONAL BLOCK DIAGRAM VIN
VDD
GND
SCLK
SDATA
Figure 1.
Table 1. MSOP/SOT-23 16-Bit PulSAR ADC
GENERAL DESCRIPTION The AD7680 is a 16-bit, fast, low power, successive approximation
ADC. The part operates from a single 2.5 V to 5.5 V power
supply and features throughput rates up to 100 kSPS. The part
contains a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 7 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
The AD7680 uses advanced design techniques to achieve very
low power dissipation at fast throughput rates. The reference for
the part is taken internally from VDD, which allows the widest
dynamic input range to the ADC. Thus, the analog input range
for this part is 0 V to VDD. The conversion rate is determined by
the SCLK frequency.
PRODUCT HIGHLIGHTS 1. First 16-bit ADC in a SOT-23 package.
2. High throughput with low power consumption.
3. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced when a power-down mode is used while not
converting. The part also features a shutdown mode to
maximize power efficiency at lower throughput rates.
Power consumption is 0.5 µA max when in shutdown.
4. Reference derived from the power supply.
5. No pipeline delays.
This part features a standard successive approximation ADC
with accurate control of the sampling instant via a CS input and
once-off conversion control.
TABLE OF CONTENTS Specifications.....................................................................................3
Timing Specifications.......................................................................6
Absolute Maximum Ratings............................................................7
ESD Caution..................................................................................7
Pin Configurations and Function Descriptions...........................8
Terminology......................................................................................9
Typical Performance Characteristics...........................................10
Circuit Information........................................................................12
Converter Operation..................................................................12
Analog Input...............................................................................12
ADC Transfer Function.................................................................13
Typical Connection Diagram...................................................13
Digital Inputs..........................................................................13
Modes of Operation.......................................................................14
Normal Mode..............................................................................14
Power-Down Mode....................................................................15
Power vs. Throughput Rate...........................................................16
Serial Interface................................................................................17
AD7680 to ADSP-218x..............................................................18
Application Hints...........................................................................19
Grounding and Layout..............................................................19
Evaluating the AD7680 Performance......................................19
Outline Dimensions.......................................................................20
Ordering Guide..........................................................................20
REVISION HISTORY Revision 0: Initial Version
SPECIFICATIONS1
Table 2. VDD = 4.5 V to 5.5 V, fSCLK = 2.5 MHz, fSAMPLE = 100 kSPS, unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted Temperature range as follows: B Version: −40°C to +85°C.
SPECIFICATIONS1
Table 3. VDD = 2.5 V to 4.096 V, fSCLK = 2.5 MHz, fSAMPLE = 100 kSPS, unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted. 1 Temperature range as follows: A, B Versions: −40°C to +85°C. See the Terminology section.
3 Sample tested during initial release to ensure compliance. See the Power vs. Throughput Rate section.
TIMING SPECIFICATIONS1
Table 4. VDD = 2.5 V to 5.5 V; TA = TMIN to TMAX, unless otherwise noted. Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40. Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4 t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading. See Power vs. Throughput Rate section.
200µAIOL
200µAIOH
1.6VTO OUTPUT
PINCL
50pF
Figure 2. Load Circuit for Digital Output Timing Specification
ABSOLUTE MAXIMUM RATINGS
Table 5. TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SDATA
SCLK
VDD
GND
VIN
SOT-23
Figure 3. SOT-23 Pin Configuration
03643-0-022
NC = NO CONNECT
AD7680
MSOP
TOP VIEW
(Not to Scale)
VDD
GND
GND
VIN
SDATA
SCLKFigure 4. MSOP Pin Configuration
Table 6. Pin Function Descriptions TERMINOLOGY
Integral Nonlinearity This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point
1/2 LSB below the first code transition, and full scale, a point
1/2 LSB above the last code transition.
Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Gain Error This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., VREF − 1 LSB) after the offset
error has been adjusted out.
Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end
of conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1 LSB, after the end of the conversion.
See the Serial Interface section for more details.
Signal-to-(Noise + Distortion) Ratio This is the measured ratio of signal-to-(noise + distortion) at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2, excluding dc). The ratio
depends on the number of quantization levels in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical signal-to-(noise + distortion) ratio for an ideal N-bit
converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for a 16-bit converter, this is 98 dB.
Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7680, it is defined as dBTHD=log20)(
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities creates distortion products
at the sum and difference frequencies of mfa ± nfb where m, n =
0, 1, 2, 3. Intermodulation distortion terms are those for which
neither m nor n are equal to zero. For example, the second-order
terms include (fa + fb) and (fa − fb), while the third-order terms
include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa −2fb).
The AD7680 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dBs.
TYPICAL PERFORMANCE CHARACTERISTICS Figure 5 shows a typical FFT plot for the AD7680 at 100 kSPS
sample rate and 10 kHz input frequency. Figure 6 shows the
signal-to-(noise + distortion) ratio performance versus the
input frequency for various supply voltages while sampling at
100 kSPS with an SCLK of 2.5 MHz.
Figure 7 shows a graph of the total harmonic distortion versus
the analog input frequency for various supply voltages, while
Figure 8 shows a graph of the total harmonic distortion versus
the analog input frequency for various source impedances (see
the Analog Input section). Figure 9 and Figure 10 show the
typical INL and DNL plots for the AD7680.
–160010k20k30k40k
FREQUENCY (kHz)
50k
Figure 5. AD7680 Dynamic Performance at 100 kSPS
INAD (d10
INPUT FREQUENCY (kHz)
100
Figure 6. AD7680 SINAD vs. Analog Input Frequency
for Various Supply Voltages at 100 kSPS
HD (d10
INPUT FREQUENCY (kHz)
110
Figure 7. AD7680 THD vs. Analog Input Frequency
for Various Supply Voltages at 100 kSPS
THD (dB)10
INPUT FREQUENCY (kHz)
110
Figure 8. AD7680 THD vs. Analog Input Frequency
for Various Source Impedances
