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AD7678ACP
18-Bit,100 kSPS PulSAR® A/D Converter
18-Bit, 2.5 LSB INL, 100 kSPS SAR ADCRev. 0
FEATURES
18-bit resolution with no missing codes
No pipeline delay (SAR architecture)
Differential input range: ±VREF (VREF up to 5 V)
Throughput: 100 kSPS
INL: ±2.5 LSB max (±9.5 ppm of full scale)
Dynamic range: 103 dB typ (VREF = 5 V)
S/(N+D): 100 dB typ @ 2 kHz (VREF = 5 V)
Parallel (18-,16-, or 8-bit bus) and serial 5 V/3 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
On-board reference buffer
Single 5 V supply operation
Power dissipation: 18 mW @ 100 kSPS
180 µW @ 1 kSPS
48-lead LQFP or 48-lead LFCSP package
Pin-to-pin compatible upgrade of AD7674/AD7676/AD7679
APPLICATIONS
CT scanners
High dynamic data acquisition
Geophone and hydrophone sensors Σ-∆ replacement (low power, multichannel)
Instrumentation
Spectrum analysis
Medical instruments
GENERAL DESCRIPTION The AD7678 is an 18-bit, 100 kSPS, charge redistribution SAR,
fully differential analog-to-digital converter that operates on a
single 5 V power supply. The part contains a high speed 18-bit
sampling ADC, an internal conversion clock, an internal
reference buffer, error correction circuits, and both serial and
parallel system interface ports.
The part is available in 48-lead LQFP or 48-lead LFCSP
packages with operation specified from –40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
D[17:0]
BUSY
MODE0
OGND
OVDD
DGNDDVDD
AVDD
AGND
REFREFGND
IN+
IN–
RESET
CNVST
PDBUF
REFBUFIN
MODE103084–0–001
Figure 1. Functional Block Diagram
Table 1. PulSAR Selection
PRODUCT HIGHLIGHTS 1. High Resolution, Fast Throughput.
The AD7678 is a 100 kSPS, charge redistribution, 18-bit
SAR ADC (no latency).
2. Excellent Accuracy.
The AD7678 has a maximum integral nonlinearity of
2.5 LSB with no missing 18-bit codes.
3. Serial or Parallel Interface.
Versatile parallel (18-, 16-, or 8-bit bus) or 2-wire serial
interface arrangement compatible with both 3 V and
5 V logic.
TABLE OF CONTENTS Specifications.....................................................................................3
Timing Specifications.......................................................................5
Absolute Maximum Ratings............................................................7
Pin Configuration and Functional Descriptions..........................8
Definition of Specifications...........................................................11
Typical Performance Characteristics...........................................12
Circuit Information........................................................................15
Converter Operation..................................................................15
Typical Connection Diagram...................................................17
Power Dissipation versus Throughput....................................19
Conversion Control....................................................................19
Digital Interface..........................................................................20
Parallel Interface.........................................................................20
Serial Interface............................................................................20
Master Serial Interface...............................................................21
Slave Serial Interface..................................................................22
Microprocessor Interfacing......................................................24
Application Hints...........................................................................25
Layout..........................................................................................25
Evaluating the AD7678’s Performance....................................25
Outline Dimensions.......................................................................26
Ordering Guide..........................................................................26
REVISION HISTORY Revision 0: Initial Version
SPECIFICATIONS
Table 2. –40°C to +85°C, VREF = 4.096 V, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted. 1 See section. Analog Inputs LSB means Least Significant Bit. With the ±4.096 V input range, 1 LSB is 31.25 µV.
3 See section. The nominal gain error is not centered at zero and is +0.273% of FSR. This specification is the deviation from this nominal
value. These specifications do not include the error contribution from the external reference, but do include the error contribution from the reference buffer if used.
Definition of Specifications
4 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
5 Data format parallel or serial 18-bit. Conversion results are available immediately after completed conversion.
7 The maximum should be the minimum of 5.25 V and DVDD + 0.3 V. Tested in Parallel Reading mode.
9 Contact factory for extended temperature range.
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted. In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2In Serial Master Read during Convert mode. See for Serial Master Read after Convert mode. Table 4
Table 4. Serial Clock Timings in Master Read after Convert ABSOLUTE MAXIMUM RATINGS
Table 5. AD7678 Absolute Maximum Ratings1 1Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
2See An section. alog InputsSpecification is for device in free air: 48-Lead LQFP: θJA = 91°C/W,
θJC = 30°C/W. Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W.
OUTPUTPIN
60pF1
500µAIOH
1.4V
IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOADCL OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.03084–0–002
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, CL = 10 pF
03084–0–003
Figure 3. Voltage Reference Levels for Timing
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
AGND
CNVST
RESET
DGND
AGND
AVDD
MODE0
MODE1
D0/OB/2C
NC
NC=NOCONNECT
D1/A0
D2/A1
D4/DIVSCLK[0]
BUSY
D17
D16
D15
D5/DIVSCLK[1]D14
DBUF
FBUFINAGNDIN+NCNCNCIN–RE
FGND
/INT
/IN
VSYN
D8/INVSCLK
/RDC/S
OGND
DGND
10/SD
11/SC
12/SYN
/RDE03084–0–004
Figure 4. 48-Lead LQFP and 48-Lead LFCSP (ST-48 and CP-48)
Table 6. Pin Function Descriptions
1AI = Analog Input; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power.
Table 7. Data Bus Interface Definitions R[0:17] is the 18-bit ADC value stored in its output register.
DEFINITION OF SPECIFICATIONS
Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Gain Error The first transition (from 000…00 to 000…01) should occur for
an analog voltage ½ LSB above the nominal –full scale
(–4.095991 V for the ±4.096 V range). The last transition (from
111…10 to 111…11) should occur for an analog voltage
1½ LSB below the nominal full scale (4.095977 V for the
±4.096 V range). The gain error is the deviation of the differ-
ence between the actual level of the last transition and the
actual level of the first transition from the difference between
the ideal levels.
Zero Error The zero error is the difference between the ideal midscale
input voltage (0 V) from the actual voltage producing the
midscale output code.
Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave
input, and is expressed in bits. It is related to S/(N+D) by the
following formula:
ENOB = (S/[N+D]dB – 1.76)/6.02
Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal, and is
expressed in decibels.
Dynamic Range Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured with the inputs shorted together. The
value for dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (S/[N+D]) S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
Aperture Delay Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response Transient response is the time required for the AD7678 to
achieve its rated accuracy after a full-scale step function is
applied to its input.
TYPICAL PERFORMANCE CHARACTERISTICS
CODE
INL-LSB (18-Bit)
–0.5–1.0
Figure 5. Integral Nonlinearity vs. Code
CODE IN HEX
COUNTS
50000Figure 6. Histogram of 131,072 Conversions of a
DC Input at the Code Transition
FREQUENCY (kHz)
AMP
ITUDE
(dB of Full S–40
–120–160
Figure 7. FFT (11 kHz Tone)
CODE
DNL-LS
(1
-Bi
–0.503084-0-008
Figure 8. Differential Nonlinearity vs. Code
CODE IN HEX
COUNTS
80000Figure 9. Histogram of 131,072 Conversions of a
DC Input at the Code Center
FREQUENCY (kHz)
NR AND S
/[N+D] (dB)
100ENOB (
Figure 10. SNR, S/(N+D), and ENOB vs. Frequency
FREQUENCY (kHz)
THD, HARMONICS
(dB)
–100–130
Figure 11. THD and Harmonics vs. Frequency
INPUT LEVEL (dB)
NR RE
RRE
D TO FULL S
CALE
(dB)
100103
Figure 12. SNR and S/(N+D) vs. Input Level
NR,
/[N+D] (dB)TEMPERATURE (°C)
Figure 13. SNR, S/(N+D), and ENOB vs. Temperature
TEMPERATURE (°C)
THD, HARMONICS
(dB)
–140–100
Figure 14. THD and Harmonics vs. Temperature
SAMPLING RATE (SPS)
RATING CURRE
NT (
0.01Figure 15. Operating Current vs. Sampling Rate
TEMPERATURE (°C)
R-DOWN OP
RATING CURRE
NTS
(nA)
60003084-0-021
Figure 16. Power-Down Operating Currents vs. Temperature
TEMPERATURE (°C)
RO E
RROR, GAIN E
RROR (LS
–50–20
Figure 17. Zero Error and Gain Error vs. Temperature
CL (pF)
DE
LAY
(ns03084-0-024
Figure 18. Typical Delay vs. Load Capacitance CL
