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AD7676AST
16-Bit +-1 LSB INL, 500 kSPS, Differential ADC
REV.0
16-Bit, �1 LSB INL,
500 kSPS, Differential ADC
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Throughput: 500 kSPS
INL: �1 LSB Max (�0.0015% of Full-Scale)
16 Bits Resolution with No Missing Codes
S/(N+D): 94 dB Typ @ 45 kHz
THD: –110 dB Typ @ 45 kHz
Differential Input Range: �2.5 V
Both AC and DC Specifications
No Pipeline Delay
Parallel (8/16 Bits) and Serial 5 V/3 V Interface
SPI™/QSPI™/MICROWIRE™/DSP Compatible
Single 5 V Supply Operation
67 mW Typical Power Dissipation, 15 �W @ 100 SPS
Power-Down Mode: 7 �W Max
Package: 48-Lead Quad Flat Pack (LQFP)
Pin-to-Pin Compatible with the AD7675
APPLICATIONS
CT Scanners
Data Acquisition
Instrumentation
Spectrum Analysis
Medical Instruments
Battery-Powered Systems
Process Control
GENERAL DESCRIPTIONThe AD7676 is a 16-bit, 500 kSPS, charge redistribution SAR,
fully differential analog-to-digital converter that operates from a
single 5 V power supply. The part contains a high-speed 16-bit
sampling ADC, an internal conversion clock, error correction
circuits, and both serial and parallel system interface ports.
The AD7676 is hardware factory calibrated and is comprehensively
tested to ensure such ac parameters as signal-to-noise ratio (SNR)
and total harmonic distortion (THD), in addition to the more
traditional dc parameters of gain, offset, and linearity.
It is fabricated using Analog Devices’ high-performance, 0.6
micron CMOS process and is available in a 48-lead LQFP with
operation specified from –40°C to +85°C.
PRODUCT HIGHLIGHTSExcellent INL
The AD7676 has a maximum integral nonlinearity of 1.0 LSB
with no missing 16-bit code.Superior AC Performances
The AD7676 has a minimum dynamic of 92 dB, 94 dB typical.Fast Throughput
The AD7676 is a 500 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.Single-Supply Operation
The AD7676 operates from a single 5 V supply and typically
dissipates only 67mW. It consumes 7 µW maximum when in
power-down.Serial or Parallel Interface
Versatile parallel (8 or 16 bits) or 2-wire serial interface
arrangement compatible with either 3 V or 5 V logic.
*Patent pending
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Inc.
AD7676–SPECIFICATIONS(–40�C to +85�C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)NOTESLSB means Least Significant Bit. With the ±2.5 V input range, one LSB is 76.3 µV.See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
TIMING SPECIFICATIONSNOTESIn serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.In serial master read during convert mode. See Table I for serial master read after convert mode.
Specifications subject to change without notice.
(–40�C to +85�C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
AD7676
Table I.Serial Clock Timings in Master Read after Convert
ABSOLUTE MAXIMUM RATINGS1Analog Inputs
IN+2, IN–2, REF, REFGND . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .AVDD + 0.3 V to AGND – 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . .±0.3 V
SupplyVoltages
AVDD,DVDD, OVDD . . . . . . . . . . . . . . . . . . . . . . . . .7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . .±7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±7 V
Digital Inputs . . . . . . . . . . . . . . . . .–0.3 V to DVDD + 0.3 V
InternalPowerDissipation3 . . . . . . . . . . . . . . . . . . . . 700 mW
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range
(Soldering10sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.See Analog Input section.Specification is for device in free air: 48-Lead LQFP: �JA = 91°C/W, �JC = 30°C/W.
Figure 1.Load Circuit for Digital Interface Timing
Figure 2.Voltage Reference Levels for Timings
ORDERING GUIDENOTESThis board can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/
demonstration purposes.This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7676 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
PIN FUNCTION DESCRIPTIONSAD7676
PIN FUNCTION DESCRIPTIONS (continued)NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
DEFINITION OF SPECIFICATIONS
INTEGRAL NONLINEARITY ERROR (INL)Integral Nonlinearity is the maximum deviation of a straight line
drawn through the transfer function of the actual ADC. The
deviation is measured from the middle of each code.
DIFFERENTIAL NONLINEARITY ERROR (DNL)In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
+FULL-SCALE ERRORThe last transition (from 011...10 to 011...11 in two’s
complement coding) should occur for an analog voltage 1 1/2 LSB
below the nominal +full scale (+2.499886 V for the ±2.5 V range).
The +full-scale error is the deviation of the actual level of the
last transition from the ideal level.
–FULL-SCALE ERRORThe first transition (from 100...00 to 100...01 in two’s
complement coding) should occur for an analog voltage 1 1/2 LSB
above the nominal –full scale (–2.499962 V for the ±2.5 V range).
The –full-scale error is the deviation of the actual level of the
last transition from the ideal level.
BIPOLAR ZERO ERRORThe bipolar zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the midscale
output code.
SPURIOUS FREE DYNAMIC RANGE (SFDR)The difference, in decibels (dB), between the rms amplitude of
EFFECTIVE NUMBER OF BITS (ENOB)ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula:
and is expressed in bits.
TOTAL HARMONIC DISTORTION (THD)THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
SIGNAL-TO-NOISE RATIO (SNR)SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
SIGNAL-TO-(NOISE + DISTORTION) RATIO (S/[N+D])S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
APERTURE DELAYAperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
TRANSIENT RESPONSEThe time required for the AD7676 to achieve its rated accuracy
after a full-scale step function is applied to its input.
PIN CONFIGURATION
48-Lead LQFP
(ST-48)
AGND
CNVST
RESET
DGND
AGND
AVDD
BYTESWAP
OB/2C
NC = NO CONNECT
SEP/PAR
D2/DIVSCLK[0]
BUSY
D15
D14
D13
D3/DIVSCLK[1]D12NCNCNCNCIN+NCNCNCIN
REFGNDREF
D4/EXT/
INT
D5/INVSYNCD6/INVSCLK
D7/RDC/SDIN
OGND
DGND
D8/SDOUT
D9/SCLK
D10/SYNC
D11/RDERR
AD7676
–Typical Performance CharacteristicsTPC 1.Integral Nonlinearity vs. Code
TPC 2.Histogram of 16,384 Conversions of a DC Input at
the Code Transition
TPC 3.Typical Positive INL Distribution (199 Units)
TPC 4.Histogram of 16,384 Conversions of a DC Input at
the Code Center
TPC 5.Typical Negative INL Distribution (199 Units)
TPC 6.FFT Plot
TPC 7.SNR, S/(N+D), and ENOB vs. Frequency
TPC 8.SNR and S/(N+D) vs. Input Level
TPC 9.SNR, THD vs. Temperature
TPC 10.Typical Delay vs. Load Capacitance CL
TPC 11.Operating Currents vs. Sample Rate
TPC 12.Power-Down Operating Currents vs. Temperature
AD7676Figure 3.ADC Simplified Schematic
CIRCUIT INFORMATIONThe AD7676 is a fast, low-power, single-supply, precise 16-bit
analog-to-digital converter (ADC). The AD7676 is capable of
converting 500,000 samples per second (500 kSPS) and allows
power saving between conversions. When operating at 100 SPS,
for example, it consumes typically only 15 µW. This feature
makes the AD7676 ideal for battery-powered applications.
The AD7676 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
The AD7676 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP package that combines space savings and allows
flexible configurations as either serial or parallel interface. The
AD7676 is pin-to-pin compatible with the AD7675.
CONVERTER OPERATIONThe AD7676 is a successive approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The capacitive DAC con-
sists of two identical arrays of 16 binary weighted capacitors.
During the acquisition phase, terminals of the array tied to the
comparator’s input is connected to AGND via SW+ and SW–.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire both analog signals.
When the acquisition phase is complete and the CNVST input
goes or is low, a conversion phase is initiated. When the con-
version phase begins, SW+ and SW– are opened first. The two
capacitor arrays are then disconnected from the inputs and
connected to the REFGND input. Therefore, the differential
voltage between the output of IN+ and IN– captured at the
end of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced.
By switching each element of the capacitor array between
REFGND or REF, the comparator input varies by binary
weighted voltage steps (VREF/2, VREF/4...VREF/65536). The
control logic toggles these switches, starting with the MSB first,
in order to bring the comparator back into a balanced condition.
After the completion of this process, the control logic generates
the ADC output code and brings BUSY output low.
Transfer FunctionsUsing the OB/2C digital input, the AD7676 offers two output
codings: straight binary and two’s complement. The ideal trans-
fer characteristic for the AD7676 is shown in Figure 4.
Figure 4.ADC Ideal Transfer Function
