AD7671ACP Fast Delivery |IC PHOENIX CO.,LIMITED

AD7671ACP ,16-Bit 1 MSPS Bipolar PulSAR® ADCSPECIFICATIONS (–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) ..
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AD7671ACP
16-Bit 1 MSPS Bipolar PulSAR® ADC
REV.B
16-Bit, 1 MSPS CMOS ADC
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Throughput
1 MSPS (Warp Mode)
800 kSPS (Normal Mode)
INL: �2.5 LSB Max (�0.0038% of Full Scale)
16-Bit Resolution with No Missing Codes
S/(N+D): 90 dB Typ @ 250 kHz
THD: –100 dB Typ @ 250 kHz
Analog Input Voltage Ranges
Bipolar: �10 V, �5 V, �2.5 V
Unipolar: 0 V to 10 V, 0 V to 5 V, 0 V to 2.5 V
Both AC and DC Specifications
No Pipeline Delay
Parallel (8/16 Bits) and Serial 5 V/3 V Interface
SPI®/QSPI™/MICROWIRE™/DSP Compatible
Single 5 V Supply Operation
Power Dissipation
112 mW Typical
15 �W @ 100 SPS
Power-Down Mode: 7 �W Max
Package: 48-Lead Quad Flatpack (LQFP)
Package: 48-Lead Chip Scale (LFCSP)
Pin-to-Pin Compatible Upgrade of the AD7665/AD7664
APPLICATIONS
Data Acquisition
Communication
Instrumentation
Spectrum Analysis
Medical Instruments
Process Control
GENERAL DESCRIPTION
The AD7671 is a 16-bit, 1 MSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5V power
supply. It contains a high speed 16-bit sampling ADC, a resistor
input scaler that allows various input ranges, an internal
conversion clock, error correction circuits, and both serial
and parallel system interface ports.
The AD7671 is hardware factory-calibrated and is comprehen-
sively tested to ensure such ac parameters as signal-to-noise ratio
(SNR) and total harmonic distortion (THD), in addition to the
more traditional dc parameters of gain, offset, and linearity.
It features a very high sampling rate mode (Warp), a fast mode
(Normal) for asynchronous conversion rate applications, and, for
low power applications, a reduced power mode (Impulse) where
the power is scaled with the throughput.
It is fabricated using Analog Devices’ high performance, 0.6 micron
CMOS process and is available in a 48-lead LQFP and a tiny
48-lead LFCSP, with operation specified from –40∞C to +85∞C.
PRODUCT HIGHLIGHTSFast Throughput
The AD7671 is a very high speed (1 MSPS in Warp Mode
and 800 kSPS in Normal Mode), charge redistribution, 16-bit
SAR ADC.Single-Supply Operation
The AD7671 operates from a single 5 V supply, dissipates
only 112 mW typical, even lower when a reduced throughput
is used with the reduced power mode (Impulse) and a power-
down mode.Superior INL
The AD7671 has a maximum integral nonlinearity of 2.5LSB
with no missing 16-bit code.Serial or Parallel Interface
Versatile parallel (8 bits or 16 bits) or 2-wire serial interface
arrangement compatible with both 3 V or 5 V logic.
*Patent pending
PulSAR Selection
AD7671–SPECIFICATIONS(–40�C to +85�C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
AC ACCURACY
AD7671
NOTESLSB means least significant bit. With the ±5 V input range, one LSB is 152.588 mV.See Definition of Specifications section. These specifications do not include the error contribution from the external reference.All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.The max should be the minimum of 5.25 V and DVDD + 0.3 V.In Warp Mode.Tested in Parallel Reading Mode.Tested with the 0 V to 5 V range and VIN – VINGND = 0 V. See Power Dissipation section.In Impulse Mode.With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively.Contact factory for extended temperature range.
Specifications subject to change without notice.
Table I.Analog Input Configuration
NOTES
1Typical analog input impedance.
2With REF = 3 V, in this range, the input should be limited to –11 V to +12 V.
3For this range the input is high impedance.
TIMING SPECIFICATIONS
(–40�C to +85�C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
AD7671
TIMING SPECIFICATIONS (continued)
Refer to Figures 17 and 18 (Master Serial Interface Modes)
Refer to Figures 19 and 21 (Slave Serial Interface Modes)
NOTESIn Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.In Serial Master Read during Convert Mode. See Table II for Master Read after Convert Mode.
Specifications subject to change without notice.
Table II.Serial Clock Timings in Master Read after Convert
SYNC to SCLK First Edge Delay Minimum
PIN CONFIGURATION
ST-48 and CP-48
ABSOLUTE MAXIMUM RATINGS1
Analog Inputs
IND2, INC2, INB2 . . . . . . . . . . . . . . . . . . . . –11 V to +30 V
INA, REF, INGND, REFGND, AGND
. . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AVDD + 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . .±0.3 V
SupplyVoltages
AVDD,DVDD, OVDD . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . .±7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Digital Inputs . . . . . . . . . . . . . . . .–0.3 V to DVDD + 0.3 V
InternalPowerDissipation3 . . . . . . . . . . . . . . . . . . . .700 mW
InternalPowerDissipation4 . . . . . . . . . . . . . . . . . . . . . .2.5 W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range
(Soldering10sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .300∞C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
2See Analog Inputs section.
3Specification is for device in free air: 48-Lead LQFP: qJA = 91∞C/W, qJC = 30∞C/W.
4Specification is for device in free air: 48-Lead LFCSP: qJA = 26∞C/W.
Figure 1.Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, CL = 10 pF
ORDERING GUIDE
NOTESThis board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
Figure 2.Voltage Reference Levels for Timing
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
AD7671
PIN FUNCTION DESCRIPTION
AD7671
PIN FUNCTION DESCRIPTION (continued)
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
AD7671
DEFINITION OF SPECIFICATIONS
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as negative full scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It is
often specified in terms of resolution for which no missing codes
are guaranteed.
Full-Scale Error
The last transition (from 011...10 to 011...11 in twos
complement coding) should occur for an analog voltage 1 1/2 LSB
below the nominal full scale (2.499886 V for the ±2.5 V range).
The full-scale error is the deviation of the actual level of the last
transition from the ideal level.
Bipolar Zero Error
The difference between the ideal midscale input voltage (0 V) and
the actual voltage producing the midscale output code.
Unipolar Zero Error
In Unipolar Mode, the first transition should occur at a level
1/2 LSB above analog ground. The unipolar zero error is the
deviation of the actual transition from that point.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
A measurement of the resolution with a sine wave input. It is
related to S/(N+D) by the following formula:
ENOB = (S/[N + D]dB – 1.76)/6.02)
and is expressed in bits.
Total Harmonic Distortion (THD)
The rms sum of the first five harmonic components to the rms
value of a full-scale input signal, expressed in decibels.
Signal-to-Noise Ratio (SNR)
The ratio of the rms value of the actual input signal to the rms
sum of all other spectral components below the Nyquist fre-
quency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
The ratio of the rms value of the actual input signal to the rms
sum of all other spectral components below the Nyquist fre-
quency, including harmonics but excluding dc. The value for
S/(N+D) is expressed in decibels.
Aperture Delay
A measure of the acquisition performance measured from the
falling edge of the CNVST input to when the input signal is
held for a conversion.
Transient Response
The time required for the AD7671 to achieve its rated accuracy
after a full-scale step function is applied to its input.
TPC 1.Integral Nonlinearity vs. Code
TPC 2.Differential Nonlinearity vs. Code
TPC 3.Typical Positive INL Distribution (314 Units)
TPC 4.Typical Negative INL Distribution (314 Units)
TPC 5.Histogram of 16,384 Conversions of a DC Input at
the Code Transition
TPC 6.Histogram of 16,384 Conversions of a DC Input at
the Code Center
AD7671
TPC 7.FFT Plot
TPC 8.SNR, S/(N + D), and ENOB vs. Frequency

TPC 9.SNR vs. Input Level
TPC 10.SNR, THD vs. Temperature
TPC 11.THD, Harmonics, and SFDR vs. Frequency
TPC 12.THD, Harmonics vs. Input Level
TPC 13.Typical Delay vs. Load Capacitance CL
TPC 14.Operating Currents vs. Sample Rate
TPC 15.Power-Down Operating Currents vs. Temperature
TPC 16.+FS, Offset, and –FS vs. Temperature
CIRCUIT INFORMATION
The AD7671 is a fast, low power, single-supply, precise 16-bit
analog-to-digital converter (ADC). The AD7671 features different
modes to optimize performances according to the applications.
In Warp Mode, the AD7671 is capable of converting 1,000,000
samples per second (1 MSPS).
The AD7671 provides the user with an on-chip track-and-hold,
successive approximation ADC that does not exhibit any pipeline
or latency, making it ideal for multiple multiplexed channel
applications.
It is specified to operate with both bipolar and unipolar input
ranges by changing the connection of its input resistive scaler.
The AD7671 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP package or a 48-lead LFCSP package that com-
bines space savings and flexible configurations as either serialparallel interface. The AD7671 is a pin-to-pin compatible
upgrade of the AD7665 and AD7664.
AD7671
Modes of Operation
The AD7671 features three modes of operation, Warp, Normal,
and Impulse. Each of these modes is more suitable for specific
applications.
The Warp Mode allows the fastest conversion rate up to 1MSPS.
However, in this mode, and this mode only, the full specified accu-
racy is guaranteed only when the time between conversion does
not exceed 1ms. If the time between two consecutive conversions
is longer than 1 ms, for instance, after power-up, the first conver-
sion result should be ignored. This mode makes the AD7671 ideal
for applications where both high accuracy and fast sample rate
are required.
The Normal Mode is the fastest mode (800 kSPS) without any limi-
tation about the time between conversions. This mode makes the
AD7671 ideal for asynchronous applications such as data acquisi-
tion systems, where both high accuracy and fast sample rate are
required.
The Impulse Mode, the lowest power dissipation mode, allows
power saving between conversions. The maximum throughput in
this mode is 666 kSPS. When operating at 100 SPS, for example,
it typically consumes only 15 mW. This feature makes the AD7671
ideal for battery-powered applications.
Transfer Functions
Using the OB/2C digital input, the AD7671 offers two output
codings: straight binary and twos complement. The ideal transfer
characteristic for the AD7671 is shown in Figure 4 and TableIII.
ADC CODE – Straight Binar
+FS – 1.5 LSB–FS
–FS + 0.5 LSB
CONVERTER OPERATION
The AD7671 is a successive approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The input analog signal is
first scaled down and level shifted by the internal input resistive
scaler, which allows both unipolar ranges (0 V to 2.5 V, 0 V to 5V,
and 0Vto 10 V) and bipolar ranges (±2.5 V, ±5 V, and ±10V).
The output voltage range of the resistive scaler is always 0V to
2.5V. The capacitive DAC consists of an array of 16 binary
weighted capacitors and an additional “LSB” capacitor. The
comparator’s negative input is connected to a “dummy” capacitor
of the same value as the capacitive DAC array.
During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND via
SWA. All independent switches are connected to the output of the
resistive scaler. Thus, the capacitor array is used as a sampling
capacitor and acquires the analog signal. Similarly, the dummy
capacitor acquires the analog signal on INGND input.
When the acquisition phase is complete and the CNVST input goes
or is LOW, a conversion phase is initiated. When the conversion
phase begins, SWA and SWB are opened first. The capacitor array
and the dummy capacitor are then disconnected from the inputs and
connected to the REFGND input. Therefore, the differential
voltage between the output of the resistive scaler and INGND
captured at the end of the acquisition phase is applied to the
comparator inputs, causing the comparator to become unbalanced.
By switching each element of the capacitor array between REFGND
or REF, the comparator input varies by binary weighted voltage
steps (VREF/2, VREF/4...VREF/65,536). The control logic toggles
these switches, starting with the MSB first, in order to bring the
comparator back into a balanced condition. After the completion
of this process, the control logic generates the ADC output code
and brings BUSY output LOW.
Figure 3.ADC Simplified Schematic

Partno	Mfg	Dc	Qty	Available	Descript
AD7671ACP	ADI	N/a	200	avai	16-Bit 1 MSPS Bipolar PulSAR® ADC