AD7665AST Fast Delivery |IC PHOENIX CO.,LIMITED

AD7665AST ,16-Bit, 570 kSPS CMOS ADCSPECIFICATIONSParameter Conditions Min Typ Max UnitRESOLUTION 16 BitsANALOG INPUTVoltage Range V – ..
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AD7665AST
16-Bit, 570 kSPS CMOS ADC
REV.0
16-Bit, 570 kSPS CMOS ADC
FUNCTIONAL BLOCK DIAGRAM
DGNDDVDDAVDDAGNDREFREFGND
CNVSTIMPULSEWARP
OGND
IND(4R)4R
OVDDAD7665
INGND
RESET
BYTESWAP
SER/PAR
DATA[15:0]
BUSY
OB/2C
INA(R)R
INC(4R)4R
INB(2R)2R
FEATURES
Throughput:
570 kSPS (Warp Mode)
500 kSPS (Normal Mode)
INL: �2.5 LSB Max (�0.0038% of Full Scale)
16-Bit Resolution with No Missing Codes
S/(N+D): 90 dB Typ @ 180 kHz
THD: –100 dB Typ @ 180 kHz
Analog Input Voltage Ranges:
Bipolar: �10 V, �5 V, �2.5 V
Unipolar: 0 V to 10 V, 0 V to 5 V, 0 V to 2.5 V
Both AC and DC Specifications
No Pipeline Delay
Parallel (8/16 Bits) and Serial 5 V/3 V Interface
Single 5 V Supply Operation
Power Dissipation
64 mW Typical
15 �W @ 100 SPS
Power-Down Mode: 7 �W Max
Package: 48-Lead Quad Flatpack (LQFP)
Pin-to-Pin Compatible Upgrade of the AD7664/AD7663
APPLICATIONS
Data Acquisition
Communication
Instrumentation
Spectrum Analysis
Medical Instruments
Process Control
GENERAL DESCRIPTION
The AD7665 is a 16-bit, 570 kSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V power
supply. It contains a high-speed 16-bit sampling ADC, a resistor
input scaler which allows various input ranges, an internal con-
version clock, error correction circuits, and both serial and
parallel system interface ports.
The AD7665 is hardware factory-calibrated and is comprehen-
sively tested to ensure such ac parameters as signal-to-noise ratio
(SNR) and total harmonic distortion (THD), in addition to the
more traditional dc parameters of gain, offset, and linearity.
It features a very high sampling rate mode (Warp) and, for
asynchronous conversion rate applications, a fast mode (Nor-
mal) and, for low power applications, a reduced power mode
(Impulse) where the power is scaled with the throughput. It is
fabricated using Analog Devices’ high-performance, 0.6 micron
CMOS process and is available in a 48-lead LQFP with opera-
tion specified from –40°C to +85°C.
*Patent pending.
PRODUCT HIGHLIGHTSFast Throughput
The AD7665 is a very high speed (570 kSPS in Warp mode
and 500 kSPS in Normal mode), charge redistribution,
16-bit SAR ADC.Single Supply Operation
The AD7665 operates from a single 5 V supply, dissipates
only 64 mW typical, even lower when a reduced throughput
is used with the reduced power mode (Impulse) and a power-
down mode.Superior INL
The AD7665 has a maximum integral nonlinearity of 2.5LSB
with no missing 16-bit code.Serial or Parallel Interface
Versatile parallel (8 or 16 bits) or 2-wire serial interface
arrangement compatible with both 3 V or 5 V logic.
AD7665–SPECIFICATIONS
AC ACCURACY
DIGITAL OUTPUTS
POWER SUPPLIES
(–40�C to +85�C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
AD7665
NOTESLSB means Least Significant Bit. With the ±5 V input range, one LSB is 152.588 µV.See Definition of Specifications section. These specifications do not include the error contribution from the external reference.All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified.In warp mode.Tested in parallel reading mode.Tested with the 0 V to 5 V range and VIN – VINGND = 0 V. See Power Dissipation section.In impulse mode.With OVDD below DVDD + 0.3 V and all digital inputs forced to OVDD or OGND respectively.Contact factory for extended temperature range.
Specifications subject to change without notice.
Table I.Analog Input Configuration
±2 REF
±REF
0 V to 4 REF
0 V to 2 REF
NOTES
1Typical analog input impedance.
2For this range the input is high impedance.
TIMING SPECIFICATIONS
Refer to Figures 13, 14, and 15 (Parallel Interface Modes)
Refer to Figures 17 and 18 (Master Serial Interface Modes)
(–40�C to +85�C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
AD7665
TIMING SPECIFICATIONS (Continued)
Refer to Figures 19 and 21 (Slave Serial Interface Modes)
NOTESIn warp mode only, the maximum time between conversions is 1 ms, otherwise, there is no required maximum time.In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.In serial master read during convert mode. See Table II.
Specifications subject to change without notice.
Table II.Serial Clock Timings in Master Read after Convert
SYNC to SCLK First Edge Delay Minimum
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7665 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
Figure 1.Load Circuit for Digital Interface Timing, SDOUT,
SYNC, SCLK Outputs, CL = 10 pF
Figure 2.Voltage Reference Levels for Timing
PIN CONFIGURATION
48-Lead LQFP
(ST-48)
ORDERING GUIDE
NOTESThis board can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
ABSOLUTE MAXIMUM RATINGS1
Analog Inputs
IND2, INC2, INB2 . . . . . . . . . . . . . . . . . . . –11 V to +30 V
INA, REF, INGND, REFGND
. . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to AVDD + 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ±0.3 V
SupplyVoltages
AVDD,DVDD, OVDD . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . ±7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V
Digital Inputs . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
InternalPowerDissipation3 . . . . . . . . . . . . . . . . . . . 700 mW
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range
(Soldering10sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.See Analog Input section.Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W, θJC = 30°C/W.
AD7665
PIN FUNCTION DESCRIPTIONS
NOTES
AI = Analog Input.
DI = Digital Input.
DI/O = Bidirectional Digital.
AD7665
DEFINITION OF SPECIFICATIONS
INTEGRAL NONLINEARITY ERROR (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as “negative full scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined as
a level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each code to the true straight line.
DIFFERENTIAL NONLINEARITY ERROR (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It is
often specified in terms of resolution for which no missing codes
are guaranteed.
FULL-SCALE ERROR
The last transition (from 011...10 to 011...11 in two’s
complement coding) should occur for an analog voltage 1 1/2 LSB
below the nominal full scale (2.499886 V for the ±2.5 V range).
The full-scale error is the deviation of the actual level of the last
transition from the ideal level.
BIPOLAR ZERO ERROR
The difference between the ideal midscale input voltage (0 V) and
the actual voltage producing the midscale output code.
UNIPOLAR ZERO ERROR
In unipolar mode, the first transition should occur at a level
1/2 LSB above analog ground. The unipolar zero error is the
deviation of the actual transition from that point.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
EFFECTIVE NUMBER OF BITS (ENOB)
A measurement of the resolution with a sine wave input. It is
related to S/(N+D) by the following formula:
ENOB = (S/[N+D]dB – 1.76)/6.02)
and is expressed in bits.
TOTAL HARMONIC DISTORTION (THD)
The rms sum of the first five harmonic components to the rms
value of a full-scale input signal and is expressed in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
The ratio of the rms value of the actual input signal to the rms
sum of all other spectral components below the Nyquist fre-
quency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
SIGNAL TO (NOISE + DISTORTION) RATIO (S/[N+D])
The ratio of the rms value of the actual input signal to the rms
sum of all other spectral components below the Nyquist fre-
quency, including harmonics but excluding dc. The value for
S/(N+D) is expressed in decibels.
APERTURE DELAY
A measure of the acquisition performance and is measured from
the falling edge of the CNVST input to when the input signal is
held for a conversion.
TRANSIENT RESPONSE
The time required for the AD7665 to achieve its rated accuracy
after a full-scale step function is applied to its input.
TPC 1.Integral Nonlinearity vs. Code
TPC 2.Differential Nonlinearity vs. Code
TPC 3.Typical Positive INL Distribution (446 Units)
TPC 4.Typical Negative INL Distribution (446 Units)
TPC 5.Histogram of 16,384 Conversions of a DC Input at
the Code Transition
TPC 6.Histogram of 16,384 Conversions of a DC Input at
the Code Center
AD7665
TPC 7.FFT Plot
TPC 8.SNR, S/(N+D), and ENOB vs. Frequency
TPC 9.SNR vs. Input Level
TPC 10.SNR, THD vs. Temperature
TPC 11.THD, Harmonics, and SFDR vs. Frequency
TPC 12.THD, Harmonics vs. Input Level
TPC 13.Typical Delay vs. Load Capacitance CL
TPC 14.Operating Currents vs. Sample Rate
TPC 15.Power-Down Operating Currents vs. Temperature
AD7665
Figure 3.ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7665 is a fast, low-power, single-supply, precise 16-bit
analog-to-digital converter (ADC). The AD7665 features different
modes to optimize performances according to the applications.
In Warp mode, the AD7665 is capable of converting 570,000
samples per second (570 kSPS).
The AD7665 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
It is specified to operate with both bipolar and unipolar input
ranges by changing the connection of its input resistive scaler.
The AD7665 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP package that combines space savings and flexible
configurations as either serial or parallel interface. The AD7665
is a pin-to-pin-compatible upgrade of the AD7663 and AD7664.
CONVERTER OPERATION
The AD7665 is a successive approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The input analog signal is,
first, scaled down and level-shifted by the internal input resistive
scaler which allows both unipolar ranges (0 V to 2.5 V, 0 V toV, and 0 to 10 V) and bipolar ranges (±2.5 V, ±5 V, and ±10V).
The output voltage range of the resistive scaler is always 0 V to
2.5 V. The capacitive DAC consists of an array of 16 binary
weighted capacitors and an additional “LSB” capacitor. The
comparator’s negative input is connected to a “dummy” capaci-
tor of the same value as the capacitive DAC array.
During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND
via SWA. All independent switches are connected to the output
of the resistive scaler. Thus, the capacitor array is used as a
sampling capacitor and acquires the analog signal. Similarly, the
“dummy” capacitor acquires the analog signal on INGND input.
When the acquisition phase is complete, and the CNVST input
goes or is low, a conversion phase is initiated. When the conversion
phase begins, SWA and SWB are opened first. The capacitor array
and the “dummy” capacitor are then disconnected from the inputs
and connected to the REFGND input. Therefore, the differen-
tial voltage between the output of the resistive scaler and INGND
captured at the end of the acquisition phase is applied to the
comparator inputs, causing the comparator to become unbalanced.
control logic toggles these switches, starting with the MSB first,
in order to bring the comparator back into a balanced condition.
After the completion of this process, the control logic generates
the ADC output code and brings BUSY output low.
Modes of Operation
The AD7665 features three modes of operations, Warp, Normal,
and Impulse. Each of these modes is more suitable for specific
applications.
The Warp mode allows the fastest conversion rate up to 570 kSPS.
However, in this mode, and this mode only, the full specified accu-
racy is guaranteed only when the time between conversion does
not exceed 1 ms. If the time between two consecutive conversions
is longer than 1 ms, for instance, after power-up, the first conver-
sion result should be ignored. This mode makes the AD7665
ideal for applications where both high accuracy and fast sample
rate are required.
The normal mode is the fastest mode (500 kSPS) without any
limitation about the time between conversions. This mode makes
the AD7665 ideal for asynchronous applications such as data
acquisition systems, where both high accuracy and fast sample
rate are required.
The impulse mode, the lowest power dissipation mode, allows
power saving between conversions. The maximum throughput
in this mode is 444 kSPS. When operating at 100 SPS, for ex-
ample, it typically consumes only 15 µW. This feature makes the
AD7665 ideal for battery-powered applications.
Transfer Functions
Using the OB/2C digital input, the AD7665 offers two output
codings: straight binary and two’s complement. The ideal transfer
characteristic for the AD7665 is shown in Figure 4 and Table III.
ADC CODE - STRAIGHT BINARY

Partno	Mfg	Dc	Qty	Available	Descript
AD7665AST	AD	N/a	200	avai	16-Bit, 570 kSPS CMOS ADC