AD7655AST Fast Delivery |IC PHOENIX CO.,LIMITED

AD7655AST ,Low Cost 4-Channel 1 MSPS 16-Bit ADCSPECIFICATIONS unless otherwise noted.)Parameter Conditions Min Typ Max UnitRESOLUTION 16 BitsANALO ..
AD7655AST ,Low Cost 4-Channel 1 MSPS 16-Bit ADCfeatures 4-channel inputs with two sample-in 48-lead LQFP or 48-lead LFCSP packages with operation ..
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ADL5370ACPZ-R7 , 300 MHz to 1000 MHz Quadrature Modulator

AD7655AST
Low Cost 4-Channel 1 MSPS 16-Bit ADC
REV.0
Low Cost 4-Channel 1 MSPS 16-Bit ADC
FUNCTIONAL BLOCK DIAGRAM
PulSAR Selection
PRODUCT HIGHLIGHTSMultichannel ADC
The AD7655 features 4-channel inputs with two sample-
and-hold circuits that allow simultaneous sampling.Fast Throughput
The AD7655 is a very high speed (1 MSPS in normal mode
and 888 kSPS in impulse mode), charge redistribution, 16-bit
SAR ADC that avoids pipeline delay.Single-Supply Operation
The AD7655 operates from a single 5 V supply and dissipates
only 120 mW typical, even lower when a reduced throughput
is used with the reduced power mode (Impulse) and a power-
down mode.Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement
compatible with both 3 V or 5V logic.
*Patent pending
FEATURES
4-Channel, 16-Bit Resolution ADC
2 Track-and-Hold Amplifiers Throughput:
1 MSPS (Normal Mode)
888 kSPS (Impulse Mode)
Analog Input Voltage Range: 0 V to 5 V
No Pipeline Delay
Parallel and Serial 5 V/3 V Interface
SPI®/QSPI™/MICROWIRE™/DSP Compatible
Single 5 V Supply Operation
Power Dissipation
120 mW Typical,
2.6 mW @ 10 kSPS
Package: 48-Lead Quad Flat Pack (LQFP) or
48-LeadFrame Chip Scale Pack (LFCSP)
Pin-to-Pin Compatible with the AD7654
Low Cost
APPLICATIONS
4-Channel Data Acquisition
GENERAL DESCRIPTION
The AD7655 is a low cost, 4-channel, 16-bit, charge redistribution
SAR, analog-to-digital converter that operates from a single 5V
power supply. It contains two low noise, wide bandwidth track-and-
hold amplifiers that allow simultaneous sampling, a high speed
1MSPS 16-bit sampling ADC, an internal conversion clock,
error correction circuits, and both serial and parallel system
interface ports. Each track-and-hold has a multiplexer in front
to provide a 4-channel input ADC.
The AD7655 features a very high sampling rate mode (Normal)
and, for low power applications, a reduced power mode (Impulse)
where the power is scaled with the throughput. It is available
in 48-lead LQFP or 48-lead LFCSP packages with operation
specified from –40∞C to +85∞C.
AD7655–SPECIFICATIONS
(–40�C to +85�C, VREF = 2.5 V, AVDD = AVDD = 5 V, OVDD = 2.7 V to 5.25 V,
unless otherwise noted.)
AD7655
NOTESLSB means least significant bit. With the 0 V to 5 V input range, one LSB is 76.294 mV.See Definition of Specifications section. These specifications do not include the error contribution from the external reference.All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.Sample tested during initial release.The maximum should be the minimum of 5.25 V and DVDD + 0.3 V.In Normal Mode.In Impulse Mode.Contact factory for extended temperature range.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Refer to Figures 10, 11, 12, 13, and 14 (Parallel Interface Modes)
(–40�C to +85�C, VREF = 2.5 V, AVDD = AVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
AD7655
*In serial master read during convert mode. See Table I for serial master read after convert mode.
Specifications subject to change without notice.
Table I.Serial Clock Timings in Master Read after Convert
TIMING SPECIFICATIONS (CONTINUED)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7655 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1
Analog Inputs
INAx2, INBx2, REFx, INxN, REFGND
AGND . . . . . . . . . . . . . . . . . . . . . .–0.3 V to AVDD + 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . .±0.3 V
SupplyVoltages
AVDD,DVDD, OVDD . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . .±7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . .-0.3 V to +7 V
Digital Inputs . . . . . . . . . . . . . . . . .–0.3 V to DVDD + 0.3 V
InternalPowerDissipation3 . . . . . . . . . . . . . . . . . . . . .700 mW
InternalPowerDissipation4 . . . . . . . . . . . . . . . . . . . . . . .2.5 W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150∞C
Storage Temperature Range . . . . . . . . . . . . .–65∞C to +150∞C
Lead Temperature Range
(Soldering10sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .300∞C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.See Analog Input section.Specification is for device in free air: 48-Lead LQFP: �JA = 91∞C/W, �JC = 30∞C/W.Specification is for device in free air: 48-Lead LFCSP: �JA = 26∞C/W.
ORDERING GUIDE
Model
AD7655AST
AD7655ASTRL
AD7655ACP
AD7655ACPRL
EVAL-AD7655CB
EVAL-CONTROL BRD2
NOTESThis board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
Figure 1.Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, CL = 10 pF
Figure 2.Voltage Reference Levels for Timing
AD7655
PIN FUNCTION DESCRIPTIONS
3A0DIMultiplexer Select. When LOW, the analog inputs INA1 and INB1 are sampled simultaneously,
5A/B
6, 20
9, 10
11, 12
PIN CONFIGURATION
DVDD
CNVST
RESET
EOC
AGND
AVDD
BYTESWAP
A/B
DGND
IMPULSE
SER/PAR
D2/DIVSCLK[0]
BUSY
D15
D14
D13
D3/DIVSCLK[1]D12
GND
GND
INA1INANINA2REF
REFBINB2INBNINB1REFGNDREF
D4/EXT/
INT
D5/INVSYNCD6/INVSCLK
D7/RDC/SDIN
OGND
DGND
D8/SDOUT
D9/SCLK
D10/SYNC
D11/RDERR
PIN FUNCTION DESCRIPTIONS
19, 36
25–28
AD7655
PIN FUNCTION DESCRIPTIONS (continued)
39, 41
42, 43
40, 45
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
DEFINITION OF SPECIFICATIONS
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code from
a line drawn from negative full scale through positive full scale.
The point used as negative full scale occurs 1/2 LSB before the
first code transition. Positive full scale is defined as a level 1 1/2 LSB
beyond the last code transition. The deviation is measured from the
middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Full-Scale Error
The last transition (from 111...10 to 111...11) should
occur for an analog voltage 1 1/2 LSB below the nominal full
scale (4.999886 V for the 0 V to 5 V range). The full-scale error
is the deviation of the actual level of the last transition from the
ideal level.
Unipolar Zero Error
In unipolar mode, the first transition should occur at a level 1/2
LSB above analog ground. The unipolar zero error is the devia-
tion of the actual transition from that point.
Spurious Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula:
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signals are held for a conversion.
Transient Response
The time required for the AD7655 to achieve its rated accuracy
after a full-scale step function is applied to its input.
TPC 1.Integral Nonlinearity vs. Code
CODE IN HEX
COUNTS
10310410510610710810910A
101
TPC 2.Histogram of 16,384 Conversions of a DC
Input at the Code Transition
FREQUENCY – kHz
AMPLITUDE – dB of Full Scale–140
–60
TPC 3.FFT Plot
TPC 4.Differential Nonlinearity vs. Code
CODE IN HEX
COUNTS4000
10310410510610710810910A
5000
TPC 5.Histogram of 16,384 Conversions of a DC
Input at the Code Center
TEMPERATURE – �C
SNR – dB
THD – dB
TPC 6.SNR, THD vs. Temperature
AD7655
FREQUENCY – kHz
SNR AND S/[N+D] – dB101001000
100ENOB – Bits
15.0
TPC 7.SNR, S/(N+D), and ENOB vs. Frequency
FREQUENCY – kHz
THD, HARMONICS – dB
–85
TPC 8. THD, Harmonics, Crosstalk and SFDR
vs.Frequency
TPC 9.Full Scale and Zero Error vs. Temperature
TPC 10.Operating Currents vs. Sample Rate
CL – pF
DELAY – ns200501001000
150
TPC 11.Typical Delay vs. Load Capacitance CL

Partno	Mfg	Dc	Qty	Available	Descript
AD7655AST	ADI	N/a	70	avai	Low Cost 4-Channel 1 MSPS 16-Bit ADC
AD7655AST	AD	N/a	50	avai	Low Cost 4-Channel 1 MSPS 16-Bit ADC