AD7653ACP ,16-Bit 1 MSPS PulSAR® Unipolar ADC with Refapplications, The AD7653 has an internal reference with a typical and a reduced power mode (Impulse ..
AD7654ASTZ , 16-Bit, 500 kSPS PulSAR® Dual, 2-Channel, Simultaneous Sampling ADC
AD7655AST ,Low Cost 4-Channel 1 MSPS 16-Bit ADCSPECIFICATIONS unless otherwise noted.)Parameter Conditions Min Typ Max UnitRESOLUTION 16 BitsANALO ..
AD7655AST ,Low Cost 4-Channel 1 MSPS 16-Bit ADCfeatures 4-channel inputs with two sample-in 48-lead LQFP or 48-lead LFCSP packages with operation ..
AD7656YSTZ , 250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar 16-/14-/12-Bit ADC
AD7658BSTZ , 250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar 16-/14-/12-Bit ADC
ADL5310ACPZ-REEL7 ,120dB-range (3 nAapplications, including control circuitry for lasers, optical switches, atten-Figure 1. uators, an ..
ADL5321ARKZ-R7 , 2.3 GHz to 4.0 GHz ¼ Watt RF Driver Amplifier
ADL5330ACPZ-WP ,1MHz to 3GHz VGA with 60dB Gain Control RangeAPPLICATIONS VPS2VPS1Output Power Control for Wireless Infrastructure IPBSVREF OPBS COM2 COM2 COM2 ..
ADL5356ACPZ-R7 , 1200 MHz to 2500 MHz, Dual-Balanced Mixer, LO Buffer, IF Amplifier, and RF Balun
ADL5358ACPZ-R7 , 500 MHz to 1700 MHz, Dual-Balanced Mixer, LO Buffer, IF Amplifier, and RF Balun
ADL5370ACPZ-R7 , 300 MHz to 1000 MHz Quadrature Modulator
AD7653ACP
16-Bit 1 MSPS PulSAR® Unipolar ADC with Ref
16-Bit 1 MSPS PulSARTM
Unipolar ADC with Reference
FEATURES
Throughput:
1 MSPS (Warp mode)
800 kSPS (Normal mode)
666 kSPS (Impulse mode)
16-bit resolution
Analog input voltage range: 0 V to 2.5 V
No pipeline delay
Parallel and serial 5 V/3 V interface
SPI®/QSPITM/MICROWIRETM/DSP compatible
Single 5 V supply operation
Power dissipation
92 mW typ @ 666 kSPS, 138 µW @ 1 kSPS without REF
128 mW typ @ 1 MSPS with REF
48-lead LQFP and 48-lead LFCSP packages
Pin-to-pin compatible with PulSAR ADCs
APPLICATIONS
Data acquisition
Instrumentation
Digital signal processing
Spectrum analysis
Medical instruments
Battery-powered systems
Process control
GENERAL DESCRIPTION The AD7653* is a 16-bit, 1 MSPS, charge redistribution SAR
analog-to-digital converter that operates from a single 5 V
power supply. The part contains a high speed 16-bit sampling
ADC, internal conversion clock, internal reference, error
correction circuits, and both serial and parallel system interface
ports. It features a very high sampling rate mode (Warp), a fast
mode (Normal) for asynchronous conversion rate applications,
and a reduced power mode (Impulse) for low power applica-
tions where power is scaled with the throughput. The AD7653 is
fabricated using Analog Devices’ high performance, 0.6 micron
CMOS process, with correspondingly low cost. It is available in
a 48-lead LQFP and a tiny 48-lead LFCSP with operation
specified from –40°C to +85°C. Patent Pending.
FUNCTIONAL BLOCK DIAGRAM DATA[15:0]
BUSY
SER/PAR
OB/2C
OGND
OVDD
DGNDDVDD
AVDD
AGND
REFREFGND
INGND
RESET
CNVSTWARPIMPULSE
REFBUFIN
PDBUF
PDREF
BYTESWAP
Figure 1.
Table 1. PulSAR Selection
PRODUCT HIGHLIGHTS 1. Fast Throughput.
The AD7653 is a 1 MSPS, charge redistribution, 16-bit SAR
ADC with internal error correction circuitry.
2. Internal Reference.
The AD7653 has an internal reference with a typical
temperature drift of 7 ppm/°C.
3. Single-Supply Operation.
The AD7653 operates from a single 5 V supply. In Impulse
mode, its power dissipation decreases with the throughput.
4. Serial or Parallel Interface.
Versatile parallel or 2-wire serial interface arrangement is
compatible with both 3 V and 5 V logic.
Rev. A
TABLE OF CONTENTS Specifications.....................................................................................3
Timing Specifications.......................................................................5
Absolute Maximum Ratings............................................................7
Pin Configuration and Function Descriptions.............................8
Definitions of Specifications.........................................................11
Typical Performance Characteristics...........................................12
Circuit Information........................................................................15
Converter Operation..................................................................15
Typical Connection Diagram....................................................17
Power Dissipation vs. Throughput...........................................19
Conversion Control....................................................................19
Digital Interface..........................................................................20
Parallel Interface.........................................................................20
Serial Interface............................................................................20
Master Serial Interface...............................................................21
Slave Serial Interface..................................................................22
Microprocessor Interfacing.......................................................24
Application Hints............................................................................25
Bipolar and Wider Input Ranges..............................................25
Layout..........................................................................................25
Evaluating the AD7653’s Performance....................................25
Outline Dimensions.......................................................................26
Ordering Guide...........................................................................26
REVISION HISTORY
Location Page
9/03—Data Sheet Changed from Rev. 0 to Rev. A Change to Product Highlights....................................................1
Changes to Specifications............................................................3
Changes to Absolute Maximum Ratings...................................7
Changes to Figure 15..................................................................13
Changes to Figure 22..................................................................16
Changes to Voltage Reference Input section...........................18
Changes to Figure 31..................................................................20
SPECIFICATIONS
Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted
V V µA µA
1See Analog Input section. LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV.
3See Definitions of Specifications section. These specifications do not include the error contribution from the external reference. All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
5Parallel or serial 16-bit. Conversion results are available immediately after completed conversion.
7The max should be the minimum of 5.25 V and DVDD + 0.3 V. In Warp mode. With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH.
10With PDREF, PDBUF LOW and PD HIGH. Impulse Mode. Tested in Parallel Reading mode.
12Consult factory for extended temperature range.
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted ns µs ns µs ns ns µs ns ns
1In Warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
Table 4. Serial Clock Timings in Master Read after Convert ABSOLUTE MAXIMUM RATINGS
Table 5. AD7653 Absolute Maximum Ratings1 Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
2See section. See Voltage Reference Input section.
4Specification is for the device in free air:
48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W
5Specification is for the device in free air:
48-Lead LFCSP; θJA = 26°C/W.
Analog Input
500µA
1.6mA
TO OUTPUT
PIN1.4V
60pF*
*IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.02966-0-006
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs CL = 10 pF
02966-0-007
Figure 3. Voltage Reference Levels for Timing
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGND
CNVST
RESET
DGND
AGND
AVDD
BYTESWAP
OB/2C
WARP
IMPULSE
NC = NO CONNECT
SER/PAR
BUSY
D15
D14
D13
D3/DIVSCLK1D12
/INT
/IN
VSYN
D6/INVSCL
/RDC/S
OGND
OVDDDV
DGND
DOUT
CLK
10/SYN
/RDE
RROR
DBUF
DRE
FBUFIN
TEMPAVAGNDAGNDNCINGNDRE
FGNDD2/DIVSCLK0
Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)
Table 6. Pin Function Descriptions
AI = Analog Input; AI/O = Bidirectional Analog; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power.
DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Full-Scale Error The last transition (from 011…10 to 011…11 in twos
complement coding) should occur for an analog voltage 1½ LSB
below the nominal full scale (2.49994278 V for the 0 V to 2.5 V
range). The full-scale error is the deviation of the actual level of
the last transition from the ideal level.
Unipolar Zero Error The first transition should occur at a level ½ LSB above analog
ground (19.073 µV for the 0 V to 2.5 V range). Unipolar zero
error is the deviation of the actual transition from that point.
Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula:
ENOB = (S/[N+D]dB – 1.76)/6.02
and is expressed in bits.
Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal, and is
expressed in decibels.
Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (S/[N+D]) S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
Aperture Delay Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response Transient response is the time required for the AD7653 to
achieve its rated accuracy after a full-scale step function is
applied to its input.
Overvoltage Recovery Overvoltage recovery is the time required for the ADC to
recover to full accuracy after an analog input signal 150% of the
full-scale value is reduced to 50% of the full-scale value.
Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is the change of
internal reference voltage output voltage V over the operating
temperature range and normalized by the output voltage at
25°C, expressed in ppm/°C. The equation follows: 2210)–()C25((–)()/(××°=°TTVVTVCppmTCV
where:
V(25°C) = V at +25°C
V(T2) = V at Temperature 2 (+85°C)
V(T1) = V at Temperature 1 (–40°C)
TYPICAL PERFORMANCE CHARACTERISTICS
CODE
INL (
SB)–4
1638432768655364915202966-0-023
Figure 5. Integral Nonlinearity vs. Code
CODE IN HEX
COUNTS
7FFB0
800080018003800280047FFC7FFD7FFE7FFF
100000
Figure 6. Histogram of 261,120 Conversions of a
DC Input at the Code Transition
FREQUENCY (kHz)
AMPLITUDE (
B of
Full Scale)–180
200300500400–20
Figure 7. FFT Plot
CODE
DNL (LS–1.0
1638432768655364915202966-0-026
Figure 8. Differential Nonlinearity vs. Code
CODE IN HEX
COUNTS
800080018003800280047FFC7FFD7FFE7FFF
140000
Figure 9. Histogram of 261,120 Conversions of a
DC Input at the Code Center
FREQUENCY (kHz)
NR,
/[N+D] (dB)
100ENOB (
14.0
Figure 10. SNR, S/(N+D), and ENOB vs. Frequency
FREQUENCY (kHz)
THD, HARMONICS
(dB)
100DR (dB)
–110
Figure 11. THD, Harmonics, and SFDR vs. Frequency
INPUT LEVEL (dB)
NR, S
/[N+D] RE
RRE
D TO FULL S
CALE
(dB)
–608202966-A-032
–50–40–30–20–10Figure 12. SNR and S/(N+D) vs. Input Level (Referred to Full Scale)
TEMPERATURE (°C)
NR,
/[N+D] (dB)
–5585ENOB (
Figure 13. SNR, S/(N+D), and ENOB vs. Temperature
TEMPERATURE (°C)
THD, HARMONICS
(dB)
–95585105
Figure 14. THD and Harmonics vs. Temperature
SAMPLE RATE (SPS)RATING CURRE
NT (
10000Figure 15. Operating Current vs. Sample Rate
TEMPERATURE (°C)
RO E
RROR, FULL S
CALE
(LS
–55–1585105
Figure 16. Zero Error, Full Scale with Reference vs. Temperature
TEMPERATURE (°C)
EF (
2.50202.5011
Figure 17. Typical Reference Output Voltage vs. Temperature
REFERENCE DRIFT (ppm/°C)
NUMBE
R OF UNITS
–300–10–6–223026221814106
Figure 18. Reference Voltage Temperature Coefficient Distribution (335 Units)
CL (pF)
DE
LAY
(ns020050100150
Figure 19. Typical Delay vs. Load Capacitance CL
