AD7643 Fast Delivery |IC PHOENIX CO.,LIMITED

AD7643 ,18-Bit, 1.25 MSPS PulSAR庐 A/D ConverterFEATURES FUNCTIONAL BLOCK DIAGRAM TEMP REFBUFIN REF REFGND DVDD DGNDThroughput: 1.25 MSPS INL: ±1.5 ..
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AD7643
18-Bit, 1.25 MSPS PulSAR庐 A/D Converter
18-Bit, 1.25 MSPS PulSAR® ADCFEATURES
Throughput: 1.25 MSPS
INL: ±1.5 LSB typical, ±3 LSB maximum (±11 ppm of full scale)
18-bit resolution with no missing codes
Dynamic range: 95 dB typical
SINAD: 93.5 dB typical @ 20 kHz (VREF = 2.5 V)
THD: −113 dB typical @ 20 kHz (VREF = 2.5 V)
2.048 V internal reference: typical drift 8 ppm/°C; TEMP output
Differential input range: ±VREF (VREF up to 2.5 V)
No pipeline delay (SAR architecture)
Parallel (18-, 16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Single 2.5 V supply operation
Power dissipation
65 mW typical @ 1.25 MSPS with internal REF
2 μW in power-down mode
Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ
Pin compatible with the AD7641 and other PulSAR ADC’s
APPLICATIONS
Medical instruments
High speed data acquisition/high dynamic data acquisition
Digital signal processing
Spectrum analysis
Instrumentation
Communications
ATE
GENERAL DESCRIPTION
The AD7643 is an 18-bit, 1.25 MSPS, charge redistribution
SAR, fully differential, analog-to-digital converter (ADC) that
operates from a single 2.5 V power supply. The part contains a
high speed, 18-bit sampling ADC, an internal conversion clock,
an internal reference (and buffer), error correction circuits, and
both serial and parallel system interface ports. The part has no
latency and can be used in asynchronous rate applications. The
AD7643 is hardware factory calibrated and tested to ensure ac
parameters, such as signal-to-noise ratio (SNR), in addition to
the more traditional dc parameters of gain, offset, and linearity.
The AD7643 is only available in Pb-free packages with
operation specified from −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
DGNDDVDD
AVDD
AGND
REFREFGND
IN+
IN–
RESET
PDBUF
REFBUFIN
PDREF
TEMP
D[17:0]
BUSY
D0/OB/2C
OGND
OVDD
MODE1
MODE0
CNVST
Figure 1.
Table 1. PulSAR 48-Lead Selection
PRODUCT HIGHLIGHTS
1. Fast Throughput.
The AD7643 is a 1.25 MSPS, charge redistribution,
18-bit SAR ADC.
2. Superior Linearity.
The AD7643 has no missing 18-bit code.
3. Internal Reference.
The AD7643 has a 2.048 V internal reference with a typical
drift of ±8 ppm/°C and an on-chip TEMP sensor.
4. Single-Supply Operation.
The AD7643 operates from a 2.5 V single supply.
5. Serial or Parallel Interface.
Versatile parallel (18-, 16-, or 8-bit bus) or 2-wire serial
interface arrangement compatible with 2.5 V, 3.3 V, or
5 V logic.
TABLE OF CONTENTS
Features..............................................................................................1
Applications.......................................................................................1
General Description.........................................................................1
Functional Block Diagram..............................................................1
Product Highlights...........................................................................1
Revision History...............................................................................2
Specifications.....................................................................................3
Timing Specifications.......................................................................5
Absolute Maximum Ratings............................................................7
ESD Caution..................................................................................7
Pin Configuration and Function Descriptions.............................8
Terminology....................................................................................11
Typical Performance Characteristics...........................................12
Applications Information..............................................................15
Circuit Information....................................................................15
Converter Operation..................................................................15
Transfer Functions......................................................................16
Typical Connection Diagram........................................................17
Analog Inputs..............................................................................17
Multiplexed Inputs.....................................................................17
Driver Amplifier Choice...........................................................18
Voltage Reference Input............................................................18
Power Supply...............................................................................20
Conversion Control...................................................................20
Interfaces..........................................................................................21
Digital Interface..........................................................................21
Parallel Interface.........................................................................21
Serial interface............................................................................22
Master Serial Interface...............................................................22
Slave Serial Interface..................................................................24
Microprocessor Interfacing.......................................................26
Application Hints...........................................................................27
Layout..........................................................................................27
Evaluating the AD7643 Performance......................................27
Outline Dimensions.......................................................................28
Ordering Guide..........................................................................28
REVISION HISTORY
4/06—Revision 0: Initial Version
SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
When using an external reference. With the internal reference, the input range is −0.1 V to VREF. 2 See Analog Inputs section. Linearity is tested using endpoints, not best fit.
4 LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 15.63 μV. See Voltage Reference Input section. These specifications do not include the error contribution from the external reference.
6 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. Parallel or serial 18-bit.
8 Conversion results are available immediately after completed conversion. See the Absolute Maximum Ratings section.
10 Tested in parallel reading mode. With internal reference, PDREF and PDBUF are low; with external reference, PDREF and PDBUF are high.
12 With all digital inputs forced to OVDD. Consult sales for extended temperature range.
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. See the Conversion Control section. See the Digital Interface section and the RESET section.
Table 4. Serial Clock Timings in Master Read After Convert Mode
NOTE
IN SERIAL INTERFACE MODES, THE SYNC, SCLK,AND
SDOUT TIMINGARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
500µAIOL
500µAIOH
1.4VTO OUTPUTPINCL
50pF
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, CL = 10 pF
Figure 3. Voltage Reference Levels for Timing
ABSOLUTE MAXIMUM RATINGS
Table 5. See Analog Inputs section.
2 See Voltage Reference Input section. Specification is for the device in free air:
48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W. Specification is for the device in free air:
48-Lead LFCSP; θJA = 26°C/W.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGND
CNVST
RESET
DGND
AGND
AVDD
MODE0
MODE1
D0/OB/2C
NC = NO CONNECT
D1/A0
D2/A1
D4/DIVSCLK[0]
BUSY
D17
D16
D15
D5/DIVSCLK[1]D14
/IN
D7/
INV
/IN
OGN
D10
D12
RDE
RRO
DBUF
DRE
BUFIN
DGND
DGND
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions

AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. Table 7. Data Bus Interface Definition
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Gain Error
The first transition (from 000…00 to 000…01) should occur for
an analog voltage ½ LSB above the nominal negative full scale
(−2.0479922 V for the ±2.048 V range). The last transition
(from 111…10 to 111…11) should occur for an analog voltage
1½ LSB below the nominal full scale (+2.0479766 V for the
±2.048 V range). The gain error is the deviation of the
difference between the actual level of the last transition and the
actual level of the first transition from the difference between
the ideal levels.
Zero Error
The zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the
midscale output code.
Dynamic Range
It is the ratio of the rms value of the full scale to the rms noise
measured with the inputs shorted together. The value for
dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Signal to (Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and is expressed in bits by
ENOB = [(SINADdB − 1.76)/6.02]
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response
The time required for the AD7643 to achieve its rated accuracy
after a full-scale step function is applied to its input.
Reference Voltage Temperature Coefficient
It is derived from the typical shift of output voltage at 25°C on a
sample of parts maximum and minimum reference output
voltage (V) measured at T, T(25°C), and T. It is
expressed in ppm/°C using
REFMINMAX())()10C25Cppm/×−×°=°REF
REFREF
REFTTVVMaxVTCV
where:
VREF (Max) = Maximum VREF at TMIN, T(25°C), or TMAX
VREF (Min) = Minimum VREF at TMIN, T(25°C), or TMAX
VREF (25°C) = VREF at 25°C
TMAX = +85°C
TMIN = –40°C
TYPICAL PERFORMANCE CHARACTERISTICS
CODE
65536131072196608
Figure 5. Integral Nonlinearity vs. Code
FFE
FFB
FFC
FFD
FFF
CODE IN HEX
UNT
5000
Figure 6. Histogram of 131,072 Conversions of a DC Input at
the Code Center (External Reference)
TEMPERATURE (°C)
(V
Figure 7. Typical Reference Voltage Output vs. Temperature (2 Units)
CODE
–0.5
Figure 8. Differential Nonlinearity vs. Code
02B
02C
02D
02F
CODE IN HEX
UNT
5000
Figure 9. Histogram of 131,072 Conversions of a DC Input at
the Code Center (Internal Reference)
TEMPERATURE (°C)
, G
N E
RRO
R (
Figure 10. Zero Error, Gain Error vs. Temperature
FREQUENCY (kHz)
ITU
(d
of
Ful
FREQUENCY (kHz)
ITU
(d
of
Ful
100200300400500
100200300400500
Figure 11. FFT 20 kHz 11000
FREQUENCY (kHz)
NR,
INAD
12.4100
Figure 12. SNR, SINAD, and ENOB vs. Frequency
FREQUENCY (kHz)
HD,
HAR
DR (100
–130
Figure 13. THD, Harmonics, and SFDR vs. Frequency
Figure 14. FFT 100 kHz –551251056545255–15–35
TEMPERATURE (°C)
NR,
INAD (
(B
its
Figure 15. SNR, SINAD, and ENOB vs. Temperature
TEMPERATURE (°C)
HD,
HARM
DR (
Figure 16. THD, Harmonics, and SFDR vs. Temperature
INPUT LEVEL (dB)
NR,
INAD
RRE
D T
CAL
–50–40–30–20–10
Figure 17. SNR and SINAD vs. Input Level (Referred to Full Scale) 125–55
TEMPERATURE(°C)
RAT
ING
CUR
–35–15525456585105
Figure 18. Power-Down Operating Currents vs. Temperature
100k
0.011010M
SAMPLING RATE (SPS)
ING
CURR
1001k10k100k1M
10k
Figure 19. Operating Current vs. Sampling Rate 0
CL (pF)
DE100150200
Figure 20. Typical Delay vs. Load Capacitance CL

Partno	Mfg	Dc	Qty	Available	Descript
AD7643	AD	N/a	2	avai	18-Bit, 1.25 MSPS PulSAR庐 A/D Converter