AD7628 Fast Delivery |IC PHOENIX CO.,LIMITED

AD7628 ,CMOS Dual 8-Bit Buffered Multiplying DACSpecifications subject to change without notice.–2– REV. AAD7628TERMINOLOGYABSOLUTE MAXIMUM RATINGS ..
AD7628KN ,CMOS Dual 8-Bit Buffered Multiplying DACSpecifications subject to change without notice.AC PERFORMANCE
AD7628KP ,CMOS Dual 8-Bit Buffered Multiplying DACSPECIFICATIONSotherwise noted)T = –408CT = –558CA A1 1Parameter T = +258C to +858C to +1258C Units ..
AD7628KP ,CMOS Dual 8-Bit Buffered Multiplying DACcharacteristics are included for Design Guidance only and are notsubject to test. V = +10.8 V to +1 ..
AD7628KP ,CMOS Dual 8-Bit Buffered Multiplying DACCHARACTERISTICSSee Timing DiagramChip Select to Write Set Up Time (t ) 160 160 210 ns minCSChip Sel ..
AD7628KR ,CMOS Dual 8-Bit Buffered Multiplying DACSpecifications subject to change without notice.–2– REV. AAD7628TERMINOLOGYABSOLUTE MAXIMUM RATINGS ..
ADIS16130AMLZ , Digital Output, High-Precision Angular Rate Sensor
ADJ75012 , 1-pole/2-pole 16A polarized power relays Variety of contact arrangements
ADL5310ACPZ-REEL7 ,120dB-range (3 nAapplications, including control circuitry for lasers, optical switches, atten-Figure 1. uators, an ..
ADL5321ARKZ-R7 , 2.3 GHz to 4.0 GHz ¼ Watt RF Driver Amplifier
ADL5330ACPZ-WP ,1MHz to 3GHz VGA with 60dB Gain Control RangeAPPLICATIONS VPS2VPS1Output Power Control for Wireless Infrastructure IPBSVREF OPBS COM2 COM2 COM2 ..
ADL5356ACPZ-R7 , 1200 MHz to 2500 MHz, Dual-Balanced Mixer, LO Buffer, IF Amplifier, and RF Balun

AD7628
CMOS Dual 8-Bit Buffered Multiplying DAC
REV.ACMOS Dual 8-Bit
Buffered Multiplying DAC
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7628 is a monolithic dual 8-bit digital/analog converter
featuring excellent DAC-to-DAC matching. It is available in
small 0.3" wide 20-pin DIPs and in 20-terminal surface mount
packages.
Separate on-chip latches are provided for each DAC to allow
easy microprocessor interface.
Data is transferred into either of the two DAC data latches via a
common 8-bit TTL/CMOS compatible input port. Control in-
put DAC A/DAC B determines which DAC is to be loaded.
The AD7628’s load cycle is similar to the write cycle of a ran-
dom access memory, and the device is bus compatible with most
8-bit microprocessors, including 6502, 6809, 8085, Z80.
The device operates from a +12 V to +15 V power supply and is
TTL-compatible over this range. Power dissipation is a low
20 mW.
Both DACs offer excellent four quadrant multiplication charac-
teristics with a separate reference input and feedback resistor for
each DAC.
PRODUCT HIGHLIGHTSDAC to DAC matching: since both of the AD7628 DACs
are fabricated at the same time on the same chip, precise
matching and tracking between DAC A and DAC B is inher-
ent. The AD7628’s matched CMOS DACs make a whole
new range of applications circuits possible, particularly in the
audio, graphics and process control areas.Small package size: combining the inputs to the on-chip
DAC latches into a common data bus and adding a DAC A/
DAC B select line has allowed the AD7628 to be packaged in
a small 20-pin 0.3" wide DIP, 20-pin SOIC, 20-terminal
PLCC and 20-terminal LCC.TTL-Compatibility: All digital inputs are TTL-compatible
over a +12 V to +15 V power supply range.
FEATURES
On-Chip Latches for Both DACs
+12 V to +15 V Operation
DACs Matched to 1%
Four Quadrant Multiplication
TTL/CMOS Compatible from +12 V to +15 V
Latch Free (Protection Schottkys not Required)
APPLICATIONS
Disk Drives
Programmable Filters
X-Y Graphics
Gain/Attenuation
DIGITAL INPUTS
Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS
CURRENT SETTLING TIME
CHANNEL-TO-CHANNEL ISOLATION
NOTES
AD7628–SPECIFICATIONS
(VDD = +10.8 V to +15.75 V, VREF A = VREF B = +10 V; OUT A = OUT B = 0 V unless
otherwise noted)
These characteristics are included for Design Guidance only and are not
subject to test. VDD = +10.8 V to +15.75 V. (Measured Using Recommended PC Board Layout (Figure 7) and AD644 as Output Amplifiers)
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V, +17 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V, +17 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . .VDD + 0.3 V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . .VDD + 0.3 V
Digital Input Voltage to DGND . . . . . . –0.3 V, VDD + 0.3 V
VPIN2, VPIN20 to AGND . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
VREF A, VREF B to AGND . . . . . . . . . . . . . . . . . . . . . . .±25 V
VRFB A, VRFB B to AGND . . . . . . . . . . . . . . . . . . . . . . .±25 V
Power Dissipation (Any Package) to +75°C . . . . . . . .450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . .6 mW/°C
Operating Temperature Range
Commercial (K) Grades . . . . . . . . . . . . . . .–40°C to +85°C
Industrial (B) Grades . . . . . . . . . . . . . . . . .–40°C to +85°C
Extended (T) Grades . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
ORDERING GUIDE
AD7628KP
AD7628KR
AD7628BQ
AD7628TQ
NOTESTo order MIL-STD-883, Class B process parts, add /883B to part number.
Contact your local sales office for military data sheet.E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = SOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
TERMINOLOGY
Relative Accuracy:
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after ad-
justing for zero and full-scale, and is normally expressed in
LSBs or as a percentage of full-scale reading.
Differential Nonlinearity:
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.
Gain Error:
Gain error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC latches after offset error has been adjusted out. Gain
error of both DACs is adjustable to zero with external resistance.
Output Capacitance:
Capacitance from OUT A or OUT B to AGND.
Digital-to-Analog Glitch Impulse:
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs,
depending upon whether the glitch is measured as a current or
voltage signal. Glitch impulse is measured with VREF A, VREF B
= AGND.
Channel-to-Channel Isolation:
The proportion of input signal from one DAC’s reference input
that appears at the output of the other DAC, expressed as a
ratio in dB.
Digital Crosstalk:
The glitch energy transferred to the output of one converter due
to a change in digital input code to the other converter. Speci-
fied in nV secs.
PIN CONFIGURATIONS
DIP, SOIC
AGND
OUT A
DGND
DAC A/DAC B
(MSB) DB7
RFB A
VREF A
DB6
DB5
DB4
LCCC
VREF A
DGND
DB6
DAC A /DAC B
DB7 (MSB)
OUT ARFB BAGNDOUT B312201391110
RFB A
PLCC
VREF A
DGND
DB6
DAC A/DAC B
DB7 (MSB)
RFB AOUT ARFB BAGNDOUT B
AD7628
INTERFACE LOGIC INFORMATION
DAC Selection
Both DAC latches share a common 8-bit input port. The con-
trol input DAC A/DAC B selects which DAC can accept data
from the input port.
Mode Selection
Inputs CS and WR control the operating mode of the selected
DAC. See Mode Selection Table below.
Write Mode
When CS and WR are both low, the selected DAC is in the write
mode. The input data latches of the selected DAC are transpar-
ent and its analog output responds to activity on DB0–DB7.
Hold Mode
The selected DAC latch retains the data that was present on
DB0–DB7 just prior to CS or WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches.
Mode Selection Table
L = Low State, H = High State, X = Don’t Care
WRITE CYCLE TIMING DIAGRAM
CIRCUIT INFORMATION—D/A SECTION
The AD7628 contains two identical 8-bit multiplying D/A con-
verters, DAC A and DAC B. Each DAC consists of a highly
stable thin film R-2R ladder and eight N-channel current steering
switches. A simplified D/A circuit for DAC A is shown in Figure
1. An inverted R-2R ladder structure is used; that is, binary
weighted currents are switched between the DAC output and
AGND, thus maintaining fixed currents in each ladder leg inde-
pendent of switch state.
EQUIVALENT CIRCUIT ANALYSIS
Figure 2 shows an approximate equivalent circuit for one of
the AD7628’s D/A converters, in this case DAC A. A similar
equivalent circuit can be drawn for DAC B. Note that AGND
(Pin 1) is common for both DAC A and DAC B.
The current source ILEAKAGE is composed of surface and junc-
tion leakages and, as with most semiconductor devices, approxi-
mately doubles every 10°C. The resistor Ro, as shown in Fig-
ure 2, is the equivalent output resistance of the device, which
varies with input code (excluding all 0s code) from 0.8R to 2R.
R is typically 11 kΩ. COUT is the capacitance due to the N-channel
switches and varies from about 50 pF to 120 pF, depending on
the digital input. g(VREF A, N) is the Thevenin equivalent volt-
age generator due to the reference input voltage VREF A and the
transfer function of the R-2R ladder.
For further information on CMOS multiplying D/A converters,
refer to “CMOS DAC Application Guide, 2ND Edition” avail-
able from Analog Devices, Publication Number G872a–15–4/86.
Figure 2.Equivalent Analog Output Circuit of DAC A
CIRCUIT INFORMATION–DIGITAL SECTION
The input buffers are simple CMOS level-shifters designed so
that when the AD7628 is operated with VDD from 10.8 V to
15.75 V, the buffer converts TTL input levels (2.4 V and 0.8 V)
into CMOS logic levels. When VIN is in the region of 1.0 volt to
2.0 volts, the input buffers operate in their linear region and
pass a quiescent current (see Figure 3). To minimize power sup-
ply currents, it is recommended that the digital input voltages be as
close to the supply rails (VDD and DGND) as practicably possible.
The AD7628 may be operated with any supply voltage in the
range 10.8 ≤ VDD ≤ 15.75 volts.
Table I.Unipolar Binary Code Table
NOTE: 1 LSB = (2–8)(VIN) =
256VIN()
Figure 4.Dual DAC Unipolar Binary Operation (2 Quadrant Multiplication). See Table I.
Figure 5.Dual DAC Bipolar Operation (4 Quadrant Multiplication). See Table II.
Table II.Bipolar (Offset Binary) Code Table
NOTE: 1 LSB = (2–7)(VIN) =
128VIN()
Table III. Recommended Trim Resistor Values
AD7628
APPLICATIONS INFORMATION
Application Hints
To ensure system performance consistent with AD7628 specifi-
cations, careful attention must be given to the following points:GENERAL GROUND MANAGEMENT: AC or transient
voltages between the AD7628 AGND and DGND can cause
noise injection into the analog output. The simplest method
of ensuring that voltages at AGND and DGND are equal is
to tie AGND and DGND together at the AD7628. In more
omplex systems where the AGND–DGND intertie is on the
backplane, it is recommended that diodes be connected in
inverse parallel between the AD7628 AGND and DGND
pins (1N914 or equivalent).OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a
code-dependent output resistance which, in turn, causes a
code-dependent amplifier noise gain. The effect is a code-
dependent differential nonlinearity term at the amplifier
output that depends on VOS (VOS is amplifier input offset
voltage). This differential nonlinearity term adds to the R/2R
differential nonlinearity. To maintain monotonic operation, it
is recommended that amplifier VOS be no greater than 10% of
1 LSB over the temperature range of interest.HIGH FREQUENCY CONSIDERATIONS: The output
capacitance of a CMOS DAC works in conjunction with the
amplifier feedback resistance to add a pole to the open loop
response. This can cause ringing or oscillation. Stability can
be restored by adding a phase compensation capacitor in
parallel with the feedback resistor.
DYNAMIC PERFORMANCE
The dynamic performance of the two DACs in the AD7628 will
depend on the gain and phase characteristics of the output am-
plifiers, together with the optimum choice of the PC board lay-
out and decoupling components. Figure 6 shows the relationship
between input frequency and channel-to-channel isolation.
Figure 6.Channel-to-Channel Isolation
Figure 7 shows a printed circuit layout for the AD7628 and the
AD644 dual op amp, which minimizes feedthrough and crosstalk.
SINGLE SUPPLY APPLICATIONS
The AD7628 DAC R-2R ladder termination resistors are con-
nected to AGND within the device. This arrangement is par-
ticularly convenient for single supply operation because AGND
may be biased at any voltage between DGND and VDD. Figure
8 shows a circuit that provides two +5 V to +8 V analog outputs
by biasing AGND +5 V up from DGND. The two DAC refer-
ence inputs are tied together and a reference input voltage is ob-
tained without a buffer amplifier by making use of the constant
and matched impedances of the DAC A and DAC B reference
inputs. Current flows through the two DAC R-2R ladders into
R1, and R1 is adjusted until the VREF A and VREF B inputs are
at +2 V. The two analog output voltages range from +5 V to
+8 V for DAC codes 00000000 to l l l l l l l l .
Figure 8.AD7628 Single Supply Operation
Figure 9 shows DAC A of the AD7628 connected in a positive
reference, voltage switching mode. This configuration is useful
because VOUT is the same polarity as VIN, allowing single supply
operation. However, to retain specified linearity, VIN must be in
the range 0 V to +2.5 V and the output buffered or loaded with
a high impedance (see Figure 10). Note that the input voltage is
connected to the DAC OUT A, and the output voltage is taken
from the DAC VREF A pin.
Figure 9.AD7628 Single Supply, Voltage Switching Mode

Partno	Mfg	Dc	Qty	Available	Descript
AD7628	AD	N/a	130	avai	CMOS Dual 8-Bit Buffered Multiplying DAC