AD7621ACP-AD7621AST Fast Delivery |IC PHOENIX CO.,LIMITED

AD7621ACP ,16-Bit, 1 LSB INL, 3 MSPS PulSAR ADCSPECIFICATIONSParameter Conditions Min Typ Max UnitRESOLUTION 16 BitsANALOG INPUTVoltage Range V – ..
AD7621AST ,16-Bit, 1 LSB INL, 3 MSPS PulSAR ADCFEATURESFUNCTIONAL BLOCK DIAGRAM16 Bits Resolution with No Missing CodesNo Pipeline Delay ( SAR arc ..
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AD7621ACP-AD7621AST
16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC
REV.Pr D
PRELIMINARY TECHNICAL DATA
16-Bit, 1 LSB INL, 3 MSPS PulSARTM ADC
FUNCTIONAL BLOCK DIAGRAM
AD7621
D[15:0]
BUSY
OB/2C
OGND
OVDD
DGNDDVDD
AVDD
AGND
REFREFGND
IN+
IN-
RESET
CNVST
PDBUF
REFBUFIN
WARPIMPULSE
BYTESWAP
PDREF
REF
TEMP
SER/PAR
FEATURES
16 Bits Resolution with No Missing Codes
No Pipeline Delay ( SAR architecture )
Differential Input Range: �VREF (VREF up to 2.5V)
Throughput:
3 MSPS (Wideband Warp and Warp Mode)
2 MSPS (Normal Mode)
1.25 MSPS (Impulse Mode)
INL: �1 LSB Max (�0.0015% of Full-Scale)
S/(N+D): 90 dB Typ @ 100 kHz ( VREF = 2.5V )
THD: –100 dB Typ @ 100 kHz
Parallel (16 or 8bits bus) and Serial 5V/3.3V/2.5V Interface
SPI/QSPI/MICROWIRE/DSP Compatible
On-board Low Drift Reference with Buffer and Temperature
sensor
Single 2.5 V Supply Operation
Power Dissipation: 100 mW Typ @ 3 MSPS
Power-Down Mode
Package: 48-Lead Quad Flat Pack (LQFP)
48-Lead Frame Chip Scale Package (LFCSP)
Speed Upgrade of the AD7677
APPLICATIONS
Medical Instruments
High Speed Data Acquisition
Communications
Instrumentation
Spectrum Analysis
ATE
GENERAL DESCRIPTION
The AD7621 is a 16-bit, 3 MSPS, charge redistribution
SAR, fully differential analog-to-digital converter that
operates from a single 2.5 V power supply. The part
contains a high-speed 16-bit sampling ADC, an internal
conversion clock, an internal reference buffer, error
correction circuits, and both serial and parallel system
interface ports.
It features a very high sampling rate mode (Wideband
Warp) for undersampling applications and, for asyn-
chronous conversion rate applications, a fast mode
(Normal) and, for low power applications, a reduced
power mode (Impulse) where the power is scaled with
the throughput.
It is available in a 48-lead LQFP or a 48-lead LFCSP
with operation specified from –40°C to +85°C.
PRODUCT HIGHLIGHTSHigh resolution and Fast Throughput
The AD7621 is a 3 MSPS, charge redistribution,
16-bit SAR ADC ( no latency ).Excellent accuracy
The AD7621 has a maximum integral nonlinearity of 1
LSB with no missing 16-bit code.Single-Supply Operation
The AD7621 operates from a single 2.5 V supply and
typically dissipates only 100mW. In impulse mode,
its power dissipation decreases with the throughput and
it features a power-down mode.Serial or Parallel Interface
Versatile parallel (16 or 8 bits bus) or 2-wire serial
interface arrangement compatible with either 2.5V,
3.3V or 5 V logic.
PulSAR Selection
PRELIMINARY TECHNICAL DATA
AD7621–SPECIFICATIONS(–40�C to +85�C, VREF = AVDD, AVDD = DVDD = OVDD = 2.5 V, unless otherwise noted.)))))
PRELIMINARY TECHNICAL DATA
NOTESLSB means Least Significant Bit. With the ±2.5 V input range, one LSB is 76.294 µV.See Definition of Specifications section. These specifications do not include the error contribution from the external reference.All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.In warp mode.Tested in parallel reading mode.In impulse mode.With all digital inputs forced to DVDD or DGND respectively.Contact factory for extended temperature range.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
(–40�C to +85�C, AVDD = DVDD = 2.5 V, OVDD = 2.3 V to 3.6 V, unless otherwise noted.)
PRELIMINARY TECHNICAL DATA
Table I.Serial clock timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period minimum
Internal SCLK Period Maximum
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
Busy High Width Maximum (Warp)
Busy High Width Maximum (Normal)
Busy High Width Maximum (Impulse)
NOTESIn warp mode only, the maximum time between conversions is 1ms; otherwise, there is no required maximum time.2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.In serial master read during convert mode. See Table I for serial master read after convert mode.
Specifications subject to change without notice.
TIMING SPECIFICATIONS (continued)
PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS1
Analog Inputs
IN+2, IN-2, REF, REFBUFIN, TEMP, REFGND to
AGND . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . .±0.3 V
Supply Voltages
AVDD,DVDD . . . . . . . . . . . . . . . . . . .-0.3V to +2.7 V
OVDD . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +3.8 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . .–0.3 V to 5.5V
Internal Power Dissipation3 . . . . . . . . . . . . . . . .700 mW
Internal Power Dissipation4 . . . . . . . . . . . . . . . . . . .2.5W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .150°C
Storage Temperature Range . . . . . . . . .–65°C to +150°C
Lead Temperature Range
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . .300°C
NOTESStresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above
those indicated in the operational section of this specification is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.See Analog Input section.Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W, θJC =
30°C/W.Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7621 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of
functionality.
ORDERING GUIDE
NOTESThis board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration
purposes.This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
Figure 1.Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, CL = 10 pF
Figure 2.Voltage Reference Levels for Timing
PRELIMINARY TECHNICAL DATA
PIN CONFIGURATION
48-Lead LQFP and 48-Lead LFCSP
(ST-48 and CP-48)
PRELIMINARY TECHNICAL DATA
PIN FUNCTION DESCRIPTIONS
PRELIMINARY TECHNICAL DATA
PRELIMINARY TECHNICAL DATA
NOTES
AI = Analog Input
AI/O = Bidirectional Analog
AO = Analog Output
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
PRELIMINARY TECHNICAL DATA
DEFINITION OF SPECIFICATIONS
Integral nonlinearity error (INL)
Linearity error refers to the deviation of each individual
code from a line drawn from “negative full scale” through
“positive full scale”. The point used as “negative full
scale” occurs 1/2 LSB before the first code transition.
“Positive full scale” is defined as a level 1 1/2 LSB be-
yond the last code transition. The deviation is measured
from the middle of each code to the true straight line.
Differential nonlinearity error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differ-
ential nonlinearity is the maximum deviation from this
ideal value. It is often specified in terms of resolution for
which no missing codes are guaranteed.
Gain error
The first transition (from 000...00 to 000...01) should
occur for an analog voltage 1/2 LSB above the nominal –
full scale (-2.047962 V for the ±2.048V range). The last
transition (from 111...10 to 111...11) should occur for
an analog voltage 1 1/2 LSB below the nominal full scale
(2.047886 V for the ±2.048V range). The gain error is the
deviation of the difference between the actual level of the
last transition and the actual level of the first transition
from the difference between the ideal levels.
Zero error
The zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the
midscale output code.
Spurious free dynamic range (SFDR)
The difference, in decibels (dB), between the rms ampli-
tude of the input signal and the peak spurious signal.
Effective number of bits (ENOB)
ENOB is a measurement of the resolution with a sine
wave input. It is related to S/(N+D) by the following for-
mula:
ENOB = (S/[N+D]dB – 1.76)/6.02)
and is expressed in bits.
Total harmonic distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal
and is expressed in decibels.
Dynamic range
Dynamic range is the ratio of the rms value of the full
scale to the rms noise measured with the inputs shorted
together. The value for dynamic range is expressed in
decibels.
Signal-to-noise ratio (SNR)
SNR is the ratio of the rms value of the actual input signal
Signal to (noise + distortion) ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input
signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but
excluding dc. The value for S/(N+D) is expressed in
decibels.
Aperture delay
Aperture delay is a measure of the acquisition perfor-
mance and is measured from the falling edge of the
CNVST input to when the input signal is held for a con-
version.
Transient response
The time required for the AD7621 to achieve its rated
accuracy after a full-scale step function is applied to its
input.
Reference Voltage Temperature Coefficient
The change of the internal reference output voltage V
over the operating temperature range and normalized by
the output voltage at 25°C, expressed in ppm/°C. The
equation follows:
TCVppmCVTVTTT(/)()()()°=−−×2110
where
V(25°C) = V at 25°C
V(T2) = V at Temperature 2
V(T1) = V at Temperature 1
Reference Voltage Long-Term Stability
Typical shift of output voltage at 25°C on a sample of
parts subjected to operation life test of 1000 hours at
125°C:ppmVtVt()()()=−×1010
where
V(t0) = V at 25°C at Time 0
V(t1) = V at 25°C after 1,000 hours operation at 125°C
Reference Voltage Thermal Hysteresis
Thermal hysteresis is defined as the change of output
voltage after the device is cycled through temperature
from +25°C to –40°C to +125°C and back to +25°C.
This is a typical value from a sample of parts put through
such a cycleppmVVCHYS()()=−°×25106
where
V(25°C) = V at 25°C
VTC = V at 25°C after temperature cycle at +25°C to
–40°C to +125°C and back to +25°C
PRELIMINARY TECHNICAL DATA
TPC 1.Integral Nonlinearity vs. Code
TPC 2.Histogram of 131,072 Conversions of a DC Input
at the Code Transition
TPC 4.Differential Nonlinearity vs. Code
TPC 5.Histogram of 131,072 Conversions of a DC Input
at the Code Center
PRELIMINARY TECHNICAL DATA
TPC 7.Typical INL and DNL vs Temperature
TPC 8.FFT
TPC 10.Typical INL and DNL vs Sampling rate
TPC 11.SNR, S/(N+D) and ENOB vs. Frequency
PRELIMINARY TECHNICAL DATA
TPC 13. SNR, S/(N+D) and THD vs. Input Level
TPC 14.SNR, S/(N+D) and ENOB vs Temperature
TPC 16.Operating Current vs. Sampling Rate
TPC 17. Power-Down Operating Currents vs. Temperature

Partno	Mfg	Dc	Qty	Available	Descript
AD7621ACP	ADI	N/a	100	avai	16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC
AD7621AST	ADI	N/a	50	avai	16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC