AD760AQ Fast Delivery |IC PHOENIX CO.,LIMITED

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AD760AQ
16/18-Bit Self-Calibrating Serial/Byte DACPORT
FUNCTIONAL BLOCK DIAGRAM
REV.A16/18-Bit Self-Calibrating
Serial/Byte DACPORT
FEATURES
±0.2 LSB (±0.00031%) Typ Peak DNL and INL
±0.5 LSB (±0.00076%) Typ Unipolar Offset, Bipolar Zero
17-Bit Monotonicity Guaranteed
18-Bit Resolution (in Serial Mode)
Complete 16/18-Bit D/A Function
On-Chip Output Amplifier
On-Chip Buried Zener Voltage Reference
Microprocessor Compatible
Serial or Byte Input
Double Buffered Latches
Asynchronous Clear Function
Serial Output Pin Facilitates Daisy Chaining
Pin Strappable Unipolar or Bipolar Output
Low THD+N: 0.005%
MUX Output Control on Power-Up and Supply Glitches
Typical Integral Nonlinearity
DACPORT is a registered trademark of Analog Devices, Inc.
INPUT CODE – Decimal
RELATIVE ACCURACY – LSB
MUX output in a predetermined state by means of a digital and
analog power supply detection circuit. This is particularly use-
ful for robotic and industrial control applications.
The AD760 is available in a 28-pin, 600 mil cerdip package.
The AQ version is specified from –40°C to +85°C.
PRODUCT DESCRIPTION
The AD760 is a complete 16/18-bit self-calibrating monolithic
DAC (DACPORT®) with onboard voltage reference, double
buffered latches and output amplifier. It is manufactured on
Analog Devices’ BiMOS II process. This process allows the fab-
rication of low power CMOS logic functions on the same chip
as high precision bipolar linear circuitry.
Self-calibration is initiated by simply pulsing the CAL pin low.
The CALOK pin indicates when calibration has been success-
fully completed. The output multiplexer (MUXOUT) can be used
to send the output to the bottom of the output range during
calibration.
Data can be loaded into the AD760 as straight binary, serial
data or as two 8-bit bytes. In serial mode, 16-bit or 18-bit data
can be used and the serial mode input format is pin selectable,
to be MSB or LSB first. This is made possible by three digital
input pins which have dual functions (Pins 12, 13, and 14). In
byte mode the user can similarly define whether the high byte or
low byte is loaded first. The serial output (SOUT) pin allows the
user to daisy chain several AD760s by shifting the data through
the input latch into the next DAC thus minimizing the number
of control lines required in a multiple DAC application. The
double buffered latch structure eliminates data skew errors and
provides for simultaneous updating of DACs in a multi-DAC
system.
The asynchronous CLR function can be configured to clear the
output to minus full-scale or midscale depending on the state of
Pin 17 when CLR is strobed. The AD760 also powers up with the
DIGITAL INPUTS (TMIN to TMAX)
AD760–SPECIFICATIONS
(@ TA = +25°C, VCC = +15 V, VEE = –15 V, VLL = + 5 V, unless otherwise noted)
AD760
NOTESFor 18-bit resolution, 1 LSB = 0.00038% of FSR. For 16-bit resolution, 1 LSB = 0.0015% of FSR. For 14-bit resolution, 1 LSB = 0.006% of FSR. FSR stands for
full-scale range and is 10 V in unipolar mode and 20 V in bipolar mode.Characteristics are guaranteed at VOUT Pin (23).TCAL is the calibration temperature.Gain Error is measured with a fixed 50 resistor as shown in Figure 5a and Figure 6a.Gain Error and gain drift are measured with the internal reference. The internal reference is the main contributor to the gain drift. If lower drift is required, the
AD760 can be used with a precision external reference such as the AD587, AD586 or AD688.DAC Gain Error is measured without the on-chip voltage reference. It represents the performance that can be obtained with an external precision reference.External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET on the AD760.Operation on ±12 V supplies is possible using an external reference such as the AD586 and reducing the output range. Refer to the Internal/External Reference
section.
Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS
Specifications are subject to change without notice.
With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise
Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested. (TMIN < TA
< TMAX, VCC = +15 V, VEE = –15 V, VLL = +5 V, tested at VOUT except where noted.)
AD760
(VCC = +15 V, VEE = –15 V, VLL = +5 V, VIH = 2.4 V, VIL = 0.4 V)TIMING CHARACTERISTICS
(Figure 1a)
Specifications subject to change without notice.
DB0–7
HBE OR
LBE
LDAC
Figure 1a.AD760 Byte Load Timing
SIN
LDAC
VALID 1VALID 16/18
SOUTVALID 1
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS*
VCC to AGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +17.0 V
VEE to AGND . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –17.0 V
VLL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±1 V
Digital Inputs (Pins 2, 7–14, and 16–21)
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–1.0 V to +7.0 V
REF IN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .±10.5 V
Span/Bipolar Offset to AGND . . . . . . . . . . . . . . . . . . .±10.5 V
REF OUT, VOUT, MUXOUT, MUXIN . . . . .Indefinite Short to
AGND, DGND, VCC, VEE, and VLL
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 50°C/W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PIN CONFIGURATION
DIP
CLR
UNI/BIP
CLR
Figure 1c.Asynchronous Clear to Bipolar or Unipolar Zero
CAL
CALOK
HBE
Figure 1d.Calibration Timing
AD760
THEORY OF OPERATION
The AD760 uses autocalibration circuitry to produce a true
16-bit DAC with typically 0.2 LSB Integral and Differential
Linearity Error and 0.5 LSB Offset Error. The block diagram
in Figure 2 shows the circuit components needed for calibration.
The MAIN DAC uses an array of bipolar current sources with
MOS current steering switches to develop a current propor-
tional to the applied digital word, ranging from 0 mA to 2 mA.
A segmented architecture is used, where the most significant
four data bits are thermometer decoded to drive 15 equal cur-
rent sources. The lesser bits are scaled using an R-2R ladder,
then applied together with the segmented sources to the sum-
ming node of the output amplifier. An extra LSB is included in
the MAIN DAC, for use during calibration.
The self-calibration architecture of the AD760 attempts to
reduce the linearity errors of its transfer function. The algorithm
first checks for bipolar or unipolar operation, calibrates either
bipolar zero or unipolar offset, and then removes the carry er-
rors (DNL errors) associated with the upper 6 bits (64 codes).
Once calibrated, the top six bits of a code entering the MAIN
DAC simultaneously address the RAM, calling up a correction
code that is then applied to the CALDAC. The output cur-
rents of both the MAIN DAC and CALDAC are combined in
the summing amplifier to produce the corrected output voltage.
Figure 2.Functional Block Diagram
In the first step of DNL calibration the output of the MAIN
DAC is set to the code just below the code to be calibrated.
The extra LSB in the MAIN DAC is turned on to find the ex-
trapolated value for the next code. The comparator is then
nulled using TRANSFER STD DAC. The voltage at VOUT
has in effect been sampled at the code to be calibrated.
Next, the extra LSB is turned off and the MAIN DAC code is
incremented by one LSB. The comparator is once again
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY: Analog Devices defines inte-
gral nonlinearity as the maximum deviation of the actual, ad-
justed DAC output from the ideal analog output (a straight line
drawn from 0 to FS – 1 LSB) for any bit combination. This is
also referred to as relative accuracy.
DIFFERENTIAL NONLINEARITY:Differential nonlinearity
is the measure of the change in the analog output, normalized to
full scale, associated with a 1 LSB change in the digital input
code. Monotonic behavior requires that the differential linearity
error be greater than or equal to –1 LSB over the temperature
range of interest.
MONOTONICITY: A DAC is monotonic if the output either
increases or remains constant for increasing digital inputs with
the result that the output will always be a single-valued function
of the input.
GAIN ERROR:Gain error is a measure of the output error be-
tween an ideal DAC and the actual device output with all 1s
loaded after offset error has been adjusted out.
OFFSET ERROR: Offset error is a combination of the offset
errors of the voltage-mode DAC and the output amplifier and is
measured with all 0s loaded in the DAC.
BIPOLAR ZERO ERROR:When the AD760 is connected for
bipolar output and 10...000 is loaded in the DAC, the devia-
tion of the analog output from the ideal midscale value of 0 V is
called the bipolar zero error.
DRIFT:Drift is the change in a parameter (such as gain, offset
and bipolar zero) over a specified temperature range. The drift
temperature coefficient, specified in ppm/°C, is calculated by
measuring the parameter at TMIN, 25°C and TMAX and dividing
the change in the parameter by the corresponding temperature
change.
TOTAL HARMONIC DISTORTION + NOISE:Total har-
monic distortion + noise (THD+N) is defined as the ratio of the
square root of the sum of the squares of the values of the har-
monics and noise to the value of the fundamental input fre-
quency. It is usually expressed in percent (%). THD+N is a
measure of the magnitude and distribution of linearity error, dif-
ferential linearity error, quantization error and noise. The distri-
bution of these errors may be different, depending upon the
amplitude of the output signal. Therefore, to be the most useful,
THD+N should be specified for both large and small signal am-
plitudes.
SIGNAL-TO-NOISE RATIO:The signal-to-noise ratio is
defined as the ratio of the amplitude of the output when a full-
scale signal is present to the output with no signal present. This
is measured in dB.
DIGITAL-TO-ANALOG GLITCH IMPULSE:This is the
amount of charge injected from the digital inputs to the analog
output when the inputs change state. This is measured at half
scale when the DAC switches around the MSB and as many as
possible switches change state, i.e., from 011.. .111 to
100 . . . 000.
DIGITAL FEEDTHROUGH:When the DAC is not selected

Partno	Mfg	Dc	Qty	Available	Descript
AD760AQ	AD	N/a	4	avai	16/18-Bit Self-Calibrating Serial/Byte DACPORT