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AD7582BQ-AD7582KN-AD7582KP-AD7582TQ
CMOS 12-BIT SUCCESSIVE APPROXIMATION ADC
ANALOG
DEVICES
CMOS 12-Bit
Successive Approximation Mil
FEATURES
12-Bit Successive Approximation ADC
Four High Impedance Input Channels
Analog Input Voltage Range of O to +5V with Positive
Reference of +5V
Conversion Time of 100p.s per Channel
No Missed Codes Over Full Temperature Range
Low Total Unadjusted Error :1LSB max
Autozero Cycle for Low Offset Voltage
Monolithic Construction
GENERAL DESCRIPTION
The AD7582 is a medium speed, I-channel 12-bit CMOS A/D
converter which uses the successive approximation technique to
provide a conversion time of 100ws per channel. An auto-zero
cycle occurs at the start of each conversion resulting in very low
system offset voltages, typically less than 100IW. The device is
designed for easy microprocessor interface using standard control
signals; c7; (decoded device address), It) (READ) and W
(WRITE). The 4-channel input multiplexer is controlled via
address inputs A0 and A1.
Conversion results are available in two bytes, 8LSB's and 4MSB's,
over an 8-bit three state output bus. Either byte can be read
first. Two converter busy flags are available to facilitate polling
of the converter’s status.
The analog input voltage range is 0V to + 5V when using a
reference voltage of + 5V. The four analog inputs are all high
impedance inputs with tight channel-to-channel matching--
typically 0.1LSBs.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
CAI V00 Use; Vcc
1 " 27 s
AINo 2 AD7582
AIN1 3
Am: 5 AUTDZERO
COMPARATOR
Van 6 12-BIT DAC
AGND 7
THREE IO D
STATE I t DATA
23 CLK OUTPUT I our
CLK osc r. --T DRIVERS 17 DB0
CONTROL LOGIC 22 BUSY
" 19 20 21 a
E E w-R BYSL DGND
PRODUCT HIGHLIGHTS
l. The AD7582 is a complete 4 channel 12-bit A/D converter in
either a 28-pin DIP or 28-tcrminal surface mount package
requiring only a few passive components and a voltage
reference.
2. Autozero cycle realizes very low offset voltages, typically
100wV.
3. The four channel input multiplexer (user addressable) features
high input impedance and excellent channel-to-channel
matching.
4. Standard microprocessor control signals to allow easy inter-
facing to most popular 8- and 16-bit microprocessors.
One Technology Way, PO. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
AD7582 -SPEiyFliWl01G (a1ysp=eg'ietl',,bi,,=, tfii,l',l1sgssel'ehes'e=i,iti,iiilv fcut = 14ilkhz external,
Parameter K Versionl B Version' T Version' Units Conditions/Comments
ACCURACY
Resolution 12 12 12 Bits
Total Urradiustcd Error" t 1 t 1 t 1 LSB max Allchannels, AIN6-AIN3
Differential Nunlincarily t 1 t 1 t 1 LSB max No missing codes guaranteed
Full Scalc ErrortGain Error“ t 1/4 t 1/4 t l/4 LSB max All channels, AIN6-AIN3
Full Scale TC is typically 5ppm/oC
Offset Error' t 1/4 t 1/4 t 1/4 LSB max Allchanncls, AIN(y-AIN3
Offset Error TC is typically 5ppm/c'C
Channcl toChanncl Mismatch' t 1/4 t 1/4 tl/4 LSB max
ANALOG INPUTS
Analoglnput Range Oto +5 Oto +5 Oto 4 5 V VREF= +5.0V
CMN, On Channel Input Capacitance g 8 8 pF typ
IAIN, Input Leakage Current AINtVAIN3; 0 to + 5V
+ 25°C 10 10 10 nA max
Tmm ton 100 100 100 nA max
REFERENCE INPUT
VREF(For Specified Performance) + S + 5 + 5 V t 5%
VREF Range + 4to + 6 + 4 to + 6 + 4 to + 6 V Degraded transfer accuracy
VREF Input Reference Current 1.0 1.0 1.0 mA max VREF = + 5.0V
POWER SUPPLY REJECTION
Vooonly t US tl/8 tl/8 LSBtyp VDD= +14.25Vto +15.75V
Vss = - 5V
Vss Only tl/8 tl/8 tl/8 LSBtyp Vss = -4.75Vto - 5.25v
Von = + 15V
LOGIC INPUTS
R-D(Pini8),t-s(Pini9),lR(Pin20)
BYSL (Pin 21), A0 (Pin 24), Al (Pin 25)
Vu. Input Low Voltage + 0.8 + 0.8 + 0.8 V max Vcc = + w 15%
V.” InputHigh Voltage +2.4 +2.4 +2.4 Vmin
Its, Input Current
w-25T tl tl tl wAmax VrN--0toVcc
Tmmton + 10 +10 +10 " max
Cm Input Capacitance' 10 10 10 pF max
CLK (Pin 23)
ViioInputLowVoltage +0.8 + 0.8 +0.8 Vmax Vcc= + 5V :5%
V1”,1nputHigh Voltage + 3.0 + 3.0 + 3.0 V min
111., Input Low Current t 10 t 10 t 10 WA max
hH,InputHighCurrent +1.5 + 1.5 + 1.5 mA max
LOGIC OUTPUTS
DM-DB7(Pinsl(Vl7),BUSY(Pin 22)4
VmJOumuHmeMMg +0.4 +0.4 +0.4 Vmax vcc--+5vt5yo,Isrroa--i.6mA4
Voso Output High Voltage + 4.0 + 4.0 + 4.0 V min Vcc: = + 5V t 5%,130URCE = 200wA
Floating State Leakage Current
(Pins l(y-17) tl tl tl wh max V0m=0VloVCC
Floating State Output Capacitance 15 15 15 pF max
CONVERSION TIMES
With External Clock 100 100 100 us min fcrna = l40kHz
With Internal Clock, TA = + 25°C 50/100 50/100 50/ 100 us min/max Using recommended clock components
as shown in Figure 6.
POWER REQUIREMENTS"
Vor, + 15 + 15 + 15 V NOM t 5% for spccified performance
Vss - 5 - 5 - 5 V NOM t 5% for specified performance
Va: + 5 + S + 5 V NOM t 5% for specified performance
Inn 7.5 7.5 7.5 mA max Typically 4mA with Vim: + 15V
Iss 7.5 7.5 7.5 mA max Typically 3mA with Vss = - 5V
Ia; 100 100 100 wAtyp VrN--VuwrVrr,
1.0 1.0 1.0 mAmax _ - -
Power Dissipation 75 75 75 mW lyp WR = RD = CS = BUSY = Logic HIGH
"rcmpcrature Rang: as follows: K, B Versions; - 40"Cto + 85"C
TVersion; - 55'C to + 125“C
JInciudes Full Scale Error, Offset Error and Relative Accuracy.
'Guaranteed bv Design, not Production tested.
'L,rswior BUSY tpin 22 ; is 1.0 milliamp.
'Conversion Time includes aulozeru cycle time.
“Power supply current is measured when AD7582 is inactive 1.6.,W - R-r, - E - BUSY - Logic HIGH.
Specifications subject ro change without notice.
-2- REV. B
AD7582
TIMING SPECIFICATIONS‘ (h, = +15ll,he= +5ll,hs= -5ll,hsr= +510
Limit at + 25°C Limit at Tm, Tu, Limit at Tu,, Tum
Parameter (All Grades) (K & B Grades) AT Grade) Units Conditions/Comments
t, 0 0 0 ns min a to W Setup Time
te (INT)2 200 240 280 ns min W Pulse Width (Internal Clock Operation)
t2 (EXT)2 IO 10 10 us min Ntrlt Pulse Width (External Clock Operation)
t3 0 0 0 ns min a to W Hold Time
t4 1 30 160 200 ns typ
200 250 300 ns max W to BUSY Propagation Delay
ts 0 o o nsmin A0,AlVa1idtoW Setup Time
tt 20 20 20 nsmin A0,A1vaiidtiRHowrirne
t7 0 0 0 ns min BUSY to CTS' Setup Time
Is 0 0 0 ns min a to E Setup Time
to 200 240 280 nsmin Emlse Width
t", o o 0 nsmin trstoR-D Hold Time
In 50 so 50 nsmin BYSLtoR) Setup Time
tu 0 o 0 nsmin BYSLtoR) Hold Time
t133 150 180 200 ns typ
200 240 280 ns max E to Valid Data (Bus Access Time)
:1: 20 20 20 nsmin R-Du, Three State Output
130 150 150 ns max (Bus Relinquish Time)
'Timing Specifications are guaranteed by Design, not Production tested. All input control signals are
specified with t, = I, = 20ns ( 10% to 90% of + 5V) and timed from a voltage level of + 1.6V. Data is timed from
Vm,Vu.orVoir,Voi.. -
2When using an external clock source the WR pulse width must be extended to provide the minimum
auto-zero cycle time of lows. See "External Clock Operation".
ll , 3 is measured with the load circuits of Figure 3 and defined as the time required for an output to cross 0.8V or 2.4V.
4tl4 is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 4.
S pecifications subject to change without notice.
i BUSY (PIN 22) f
CS (PIN 19)
ts, 3 (PIN 191
W (PIN 20) I ---"-T- ts-a-tir, l. -.- tu,
RT: (PIN Is) r
t. +x...‘ amt [Ht tta)'
bw/tu"' --1 L
BUSY (PIN 22) trs m to '14
ts P 3:11; Ity-tT) HIGN IMPEDANCE BUS LOW BVTE DATA HIGH BYTE DATA F
A0, A1 v... NOTES
(PINS 24.25) THE rwo-BVTE CONVERSQN RE_SULT CAN BE READ IN EITHER ORDER FIGURE Is FOR LOW BYTE. NIGN BYTE ORDER
" IF BYSL CHANGES WHILE CS & RD ARE LOW THE DATA WILL CHANGE TO REFLECT THE BYSL INPUT
Figure I. Start Cycle Timing Figure 2. Read Cycle Timing
DBN DEN DBN DBN
3k () 100pF mop; 3k I 10pF mpF
DGND $oc~n DGND g DGND
a. High-Z to VOH b. High-Z to ' a. VOH to High-Z b. VOL to High-Z
Figure 3. Load Circuits for Access Time Test (trs) Figure 4. Load Circuits for Output Float Delay Test (rm)
REV. B -3-
AD7582
ABSOLUTE MAXIMUM RATINGS'
(TA = f 25°C unless otherwise stated)
Vroro to DGND
Vss to DGND ..................
AGND to DGND ............
Wx: to DGND
VREF to AGND .............
AIN (0-3) to AGND
Digital Input Voltage to DGND
(Pins 18-21, 23-25)
Digital Output Voltage to DGND
(Pins 10-17, 22) ............
Operating Temperature Range
Commercial (K Version)
Industrial (B Version) ...........
....... -0.3V, +17V
+0.3V, -7V
-0.3V, VREF +0.3V
-0.3V, Voo +0.3V
-0.3V, Vor, +0.3V
-0.3V, Vor, +0.3V
-0.3V, Vor, +0.3V
-0.3V, Vroro +0.3V
- 40°C to + 85°C
- 40°C to + 85°C
Extended (T Version) ........... - 55''C to + 125°C
ORDERING GUIDE
Unadjusted
Temperature Error Package
Modell Range Tsus -TMAX Option2
AD7582KN - 40°C to + 85''C t ILSB N-28
AD7582BQ - 40°C to + 85°C t lLSB Q-28
AD7582TQ - 55°C to +125°C t ILSB Q-28
AD7582KP - 40°C to + 85°C t ILSB P-28A
'To order MIL-STD-883, Class B processed parts, add /883B to part
number. Contact your local sales office for military data sheet.
IN = Plastic DIP; Q = Cerdip, P = Plastic Leaded Chip Carrier.
CAUTION
F........... -65T to ' 150°C
Storage Temperature
Junction Temperature ................ + 150°C
DIP Package, Power Dissipation ........... 875mW
01A Thermal Impedance .............. 75°C/W
Lead Temperature, Soldering (lOsec) ........ + 260°C
Cerdip Package, Power Dissipation ......... l000mW
ha Thermal Impedance .............. 51°C/W
Lead Temperature, Soldering (10sec) ........ + 300°C
PLCC Package, Power Dissipation .......... 500mW
61A Thermal Impedance .............. 80°C/W
Lead Temperature, Soldering
Vapor Phase (60sec) ............... + 215°C
Infrared (15sec) .................. + 210°C
'Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V, which readily
accumulate on the human body and on test equipment, can discharge without detection. Although
these devices feature proprietary ESD protection circuitry, permanent damage may still occur on 1
these devices if they are subjected to high energy electrostatic discharges. Therefore, proper
precautions are recommended to avoid any performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
PIN CONFIGURATIONS
CAZ 1 . " V00
AINO 2 27 Vss
Am1 E 26 NC
AINZ [I 25 At
JUN 3 E
AGND E
DGND E
DB6 11
DB6 13
AD7582 " A0
TOP VIEW
(Not to Scale) 23 CLK
17 DB0 (L531
15 DB2
NC = NO CONNECT
A07582
TOP VIEW
(Not to Sula)
NC = NO CONNECT
REV. B
