AD7581BQ ,CMOS uP-COMPATIBLE 8-BIT, 8-CHANNEL DASGENERAL DESCRIPTION
The AD7581 is a microprocessor compatible 8 bit, 8 channel,
memory buffered ..
AD7581JN ,CMOS uP-COMPATIBLE 8-BIT, 8-CHANNEL DASSpecifications subject to change without notice.
REV. AM7581
GENERAL CIRCUIT INFORMATION
B ..
AD7581KN ,CMOS uP-COMPATIBLE 8-BIT, 8-CHANNEL DASGENERAL DESCRIPTION
The AD7581 is a microprocessor compatible 8 bit, 8 channel,
memory buffered ..
AD7581KN ,CMOS uP-COMPATIBLE 8-BIT, 8-CHANNEL DASFEATURES
8-Bit Resolution
On-Chip tt X 8 Dunl-Port Memory
No Missed Codes Over Full Temper ..
AD7581LN ,CMOS uP-COMPATIBLE 8-BIT, 8-CHANNEL DASSpecifications subject to change without notice.
REV. AM7581
GENERAL CIRCUIT INFORMATION
B ..
AD7582BQ ,CMOS 12-BIT SUCCESSIVE APPROXIMATION ADCSpecifications subject to change without notice.
-2- REV. BAD7582
TIMING SPEIIIFlllATIONS1 (a ..
ADG836YCP-REEL ,0.5 Ω CMOS 1.65 V TO 3.6 V Dual SPDT/2:1 MUXSPECIFICATIONS (V = 2.5 V ± 0.2 V, GND = 0 V, unless otherwise noted.)DD ..
ADG836YCP-REEL ,0.5 Ω CMOS 1.65 V TO 3.6 V Dual SPDT/2:1 MUXCHARACTERISTICS t 21 ns typ R = 50 , C = 35 pF ON L L ..
ADG836YRM ,0.5 Ω CMOS 1.65 V TO 3.6 V Dual SPDT/2:1 MUXSPECIFICATIONS (V = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.)DD –40C ..
ADG836YRM-REEL7 ,0.5 Ω CMOS 1.65 V TO 3.6 V Dual SPDT/2:1 MUXGENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe ADG836 is a low voltage CMOS device containing two 1. <0. ..
ADG839YKSZ-500RL7 ,0.35 Ω CMOS 1.65 V to 3.6 V Single SPDT Switch/2:1 MUXGENERAL DESCRIPTION The ADG839 is a low voltage CMOS device containing a single- Table 1. ADG839 Tr ..
ADG839YKSZ-REEL7 ,0.35 Ω CMOS 1.65 V to 3.6 V Single SPDT Switch/2:1 MUXFEATURES FUNCTIONAL BLOCK DIAGRAM 1.65 V to 3.6 V operation ADG839Ultralow on resistance: S20.35 Ω ..
AD7581AQ-AD7581BQ-AD7581JN-AD7581KN-AD7581LN
CMOS uP-COMPATIBLE 8-BIT, 8-CHANNEL DAS
ANALOG
DEVICES
ans' MP-Compatihle
8-Bit,8-thannel0hs
AD7581
FEATURES
8-Bit Resolution
On-Chip tt X 8 Duai.Port Memory
No Missed Codes Our Full Temperature Range
lnurfacu Directly to ZBO/BOBSMOO
CMOS, TTL Compatible Digital inputs
Three-Sme Data Drivers
Ratiometritt Capability
Interleaved DMA Operation
Fast Conversion
AID Process Totally Transparent to ttP
Low Cost
GENERAL DESCRIPTION
The AD7581 is a microprocessor compatible 8 bit, 8 channel,
memory buffered, data-acquisition system on a monolithic
CMOS chip. It consists of an 8 bit successive approximation
A/D converter, an 8 channel multiplexer, 8 X 8 dual-port
RAM, three-state DATA drivers (for interface), address latches
and microprocessor compatible control logic. The device inter-
faces directly to 8080, 8085, Z80, 6800 and other micro-
processor systems.
The successive approximation conversion takes place on a
continuous, channel sequencing, basis using microprocessor
control signals for the clock. Data is automatically transferred
to its proper location in the 8 X 8 dual-port RAM at the end
of each conversion. When under microprocessor control, a
READ DATA operation is allowed at any time for any channel
since on-chip logic provides interleaved DMA. The facility to
latch the address inputs (A0 - A2) with ALE enables the
AD7581 to interface with pp systems which feature either
shared or separate address and data buses.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
Van Van Don
AD7581
"IT DAC
aouiuhuu
DRIVERS MEMORY
DB - DBO
DATA OUT
(10 - 17]
SUCCESSIVE
APPROXIMATION
REGISTER
ADDRESS
LAYCHES
INTERFACE AND
CONTROL LOGDC
ALE A0 A1 A2
One Technology Way, PO. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703 wa: 710/394-6577
Telex: 924491 Cable: ANALOG NORWOODMASS
A0758] -SPEtlFlthT10lG
nc SPECIFICATIONS th, = +5ll, llesr
-m Unipolar Operation, unless otherwise stated.)
Typical at Limit Over
Parameter Version1 +25°C Temperature Units Conditions/Comments
ACCURACY
Resolution All 8 8 Bits
Relative Accuracy IN, AQ tl 7/8 tl 7/8 max LSB
KN, BQ 13/4 13/4 max LSB
LN, CQ 11/2 t1/2 max LSB
Differential Nonlinearity IN, AQ :1 7/8 tl 7/8 max LSB
KN, BQ ue7/8 t7/8 max LSB
LN, CQ t3/4 t3/4 max LSB
Offset ErrorZ IN, AQ 200 200 max mV Adjustable to zero, See Figure 7a.
KN, BQ 80 80 max mV
LN, CO 50 50 max mV
Gain Error
Worst Channel IN, AQ t3 t6 max LSB Adjustable to zero, See Figure 7a.
KN, BQ t2 t4 max LSB Gain Error Is Measured After Offset
LN, CQ fcl t2 max LSB Calibration. Max Full Scale Change
for Any Channel from +25°C to
Tmin or TM Is t2LSB.
Gain Match Between Channels IN, AQ 2 3 max LSB Adjustable to zero, See Figure Ta,
KN, BQ 1 1/2 2 max LSB
LN, CQ 1 1 max LSB
BOFS Gain Error All -2 1/2 - LSB
ANALOG INPUTS
Input Resistance
At VREF (Pin 10) All 10/20/30 10/20/30 kit min/typ/max
At BOFS (Pin 1)3 All 10/20/30 10/20/30 Kil minhyplmax
At Any Analog Input (Pins 2-9) All 10/20/30 10/20/30 kfl min/typlmax
VREF (For Specified Performance) All - 10 - 10 V i5%
Vm Range' All -5 to -15 -5 to -15 V
Nominal Analog Input Range
Unipolar Mode All 0 to +Vup 0 to +VREF V See Figure 7 and 8.
0 to -kur, 0 to -VREF V .
Bipolar Mode All -vBoessvAmslvREFl-VBoFs See Figure 9
DIGITAL INPUTS
a (Pin 13), ALE (Pin 16)A0 - A,
(Pin 17-19), CLK (Pin 15)
an Logic HIGH Input Voltage All +2.2 +2.4 min V
me. Logic LOW Input Voltage All + 1.2 +0.8 max V
Irs Input Current All 0.01 1 max wh Vm = 0V, VDD
Cm Input Capacitance' A11 4 5 max pF
DIGITAL OUTPUTS
STAT (Pin 12), DB, to DB0 (Pins 26-27)
Vor, Output HIGH Voltage All +4.8 +4.5 min V ISOURCE = 40WA
Vos. Output LOW Voltage All +0.4 +0.6 max V ISINK = 1.6mA
ILKG DB, to DB0 Floating State
Leakage All 0.3 10 max WA
Floating State Output Capacitance
(DB7-DBD) All 5 10 max pF VOUT = 0V to Vo,,
Output Code All U.nipolar Binary Figure 7
Complementary Binary Figure 8
Offset Binary Figure 9
POWER REQUIREMENTS
VDD A11 +5 +5 V
u, - Static All 3 typ 5 max mA
loo - Dynamic All 3 typ 8 max mA fcas--1MH2
'Temperature range " follows: IN, KN, LN (0 to +70°C); AQ, BQ, CQ (-2S'C to +85%).
2Typical offset temperature coefficient is t 150wVPC.
3R30F5/RMN (G-F) mismatch causes transfer function rotation about positive full scale. The effect is an offset and a gain term when using the circuits
of Figure Ba and Figure 9a.
'Typical value, not guaranteed or subject to test.
'Guaranteed but not tested.
"Typical change in Bors gain from +25°C to Tmill to Tm, is t2LSBs,
Specifications subject to change without notice.
REV. A
AD7581
GENERAL CIRCUIT INFORMATION
BASIC CIRCUIT DESCRIPTION
The AD7581 accepts eight analog inputs and sequentially con-
verts each input into an eight-bit binary word using the succes-
sive approximation technique. The conversion results are
stored in an 8 X 8 bit dual-port RAM. The device runs either
directly from the microprocessor clock (in 6800 type systems)
or from some suitable signal (e.g. ALE in 8085 type systems).
Most applications require only a -10V reference and a +SV
supply. Start-up logic is included on the device to establish
the correct sequences on power-up. A maximum of 800 clock
pulses are required for this period. Figure 1 shows the AD7581
functional diagram.
Van Van Bars
AIN B-BIT DAC
I X tt T AGND
DRIVERS MEMORY
DB7 - DBO
DATA DUT
(20 - 27)
SUCCESSIVE
APPROXlMA'IION
REGISTER
ADDRESS
INTERFACE AND LATCHES
CONTROL LOGIC
E5 DGND CLK 'TAT
ALE A0 A1 A2
Figure 1. AD7581 Functional Diagram
Conversion of a single channel requires 80 input clock periods
and a complete scan through all channels requires 640 input
clock periods. When a channel conversion is complete, the suc-
cessive approximation register contents are loaded into the
proper channel location of the 8 X 8 RAM. At this time a
status signal output, STAT (pin 12), gives a short IEEEEiVC
going pulse (8 clock periods). This negative going STAT pulse
is extended to 72 clock periods when channel 1 conversion is
complete. An external pulse-width detector connected to the
status pin can be used to derive conversion-related timing sig-
nals for microprocessor interrupts (see Channel Identification
opposite page). Simultaneous with STAT going low, the MUX
address is decremented. Eight clock periods later the next con-
version is started.
Automatic interleaved DMA is provided by on-chip logic to
ensure that memory updates take place at instants when the
microprocessor is not addressing memory. Memory locations
are addressed by A0, A1 and A2. This address may be latched
by ALE for systemsyrhich feature a multiplexed address/data
bus or alternatively, for systems which have separate address
and data buses, the address latches can be made transparent by
tying ALE (pin 16) HIGH. tS (pin 13) activates three-state
buffers to place addressed data on the DB0 - DB7 data out-
put pins.
AID CIRCUIT DETAILS
In the successive approximation technique, successive bits,
starting with the most significant bit (DB7), are applied to the
input of the D/A converter. The DAC output is then compared
to the unknown analog input voltage, Am (n), using a com-
parator. If the DAC output is greater than Am(n), the data
latch for the trial bit is reset to zero, and the next smaller data
bit is tried. If the DAC output is less than A1N(n), the trial
data bit stays in the "I" State, and the next smaller data bit is
tried. Each successive bit is tried, compared to A1N(n), and set
or reset in this manner until the least significant bit (DBo)
decision is made. The successive approximation register now
contains a valid digital representation of Am(n). AlN(n) is
assumed to be stable during conversion.
The current weighting D/A converter is a precision multiplying
DAC. Figure 2 shows the functional diagram of the DAC as
used in the AD7581. It consists of a precision Silicon Chromi-
um thin film R/2R ladder network and 8 N-channel MOSFET
switches operated in single-pole-double-throw.
The currents in each 2R shunt arm are binarily weighted i.e.,
the current in the MSB arm is VREF divided by 2R, in the
second arm is VREF divided by 4R, etc, Depending on the
D/A logic input (A/D output) from the successive approxima-
tion register, the current in the individual shunt arms is steered
either to AGND or to the comparator summing point.
JUN I0) AIN m Boss
SUMMING
COMPARATOR
MSB I I ILSB
DB7 1036 L035 050
SUCCESIVE
APPROXIMATION REGISTER
AGND CONTROL
Figure 2. D/A Converter as Used in AD7581
REV. A
A0758]
M SPECIFICATIONS th, = +5ll, VREF = -m Unipolar Operation. unless otherwise stated.)
Typical at Limit Over
Symbol Specification oiy'c Temperature Units Conditions
tH ALE pulse width 50 80 min ns See "Switching Terminology"
tALS Address valid to latch set-up time 45 70 min ns
tALH Address valid to latch hold time 10 20 min ns
ILCS Address latch to E set-up time 10 20 min ns
tACC eg to output propagation delay 200 250 max ns CL = lOOpF
ttrw 'i5pulse width 250 280 min ns
ttF CS to output float propagation delay 50 80 max ns
tCLZ Etc low impedance bus 100 150 max ns
chK Clock frequency for stated accuracy 1600 1200 max1 kHz
'Guaranteed conversion time of 66.6us/channel with 120okHz clock.
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
V00 to AGND ...................... + 7V am 1 V Eire,
VDD t0 DGND ...................... + 7V JUN 7E " tmo Mit)
AGND t0 DGND ................ -0.3V, Vor, A|NUE E1931
Digital Input Voltage to DGND m 5E E DB2
(Pins 13, 16-19) ........... -0.3V, VDD +0.3V AIME " DB3
Digital Output Voltage to DGND Am “I: AD7581 CEI DM
(Pins 12, 26-27) ........... -0.3V, VDD +0.3V “qu TOP “W 21035
CLK (Pin 15) Input Voltage to DGND . - 0.3V, vDD +0.3V Am 'CE tNOTr0 SCALE) " m
VREF (Pin 10) to AGND ................ t 25V AmuE E931 (msa)
VBOFS (Pin l) to AGND ................ t 17V VREFE EM
AIN (0-7)(Pin 9-2) ................... t 17V AGNDE " AI
OperatingTemperature Range MAT " 11 Att
Commercial (J, K, L Versions) ......... 0 to + 70°C eg Ei " ALE
Industrial (A, B, C Versions) ....... - LPC to + 85°C DGND u " cm
Storage Temperature
Lead Temperature (Soldering, lOsecs)
Power Dissipation (Any Package)
to +75°C .....................
Derate above + 75°C by
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect-
ed; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The pro-
tective foam should be discharged to the destination socket before devices are removed.
............ - 65°C to +150°C
+ 300°C
1 ,OOOmW
. . lOmW/°C
REV. A
ORDERING GUIDE
Temperature Differential Package
Model Range Nonlinearity (LSB) Option'
AD758UN 0 to +70°C tl 7/8 max N-28
AD7581K.N 0 to +70°C t7/8 max N-28
AD7581LN 0 to +70°C t3/4 max N-28
AD7581AQ -2YC to +85°C tl 7/8 max Q-28
AD758lBQ -25''C to +85''C t7/8 max Q-28
AD7581CQ -25''C to +85°C t3/4 max Q-28
*N = Plastic DIP; Q = Cerdip. For outline information see Package
Information section.
AD7581
TIMING AND CONTROL OF THE AD7581
CHANNEL SELECTION
Table I shows the truth table for the address inputs. The input
address is latched when ALE goes LOW. When ALE is HIGH
the address input latch is transparent.
Channel Data
A2 A1 A0 ALE To Be Read
0 0 0 1 Channel o
o o 1 1 Channel 1
0 1 0 1 Channel 2
0 1 1 1 Channel 3
l o 0 1 Channel 4
1 o 1 1 Channel 5
1 l 0 1 Channel 6
1 1 1 1 Channel 7
Table J. Channel Selection Truth Table
TIMING AND CONTROL
A typical timing diagram is shown in Figure 3. When (Fis
HIGH, the three-state data drivers are in the high-impedance
state. When t5ggoes LOW the data drivers switch to the low-
impedance state (i.e., low impedance to DGND or to VDD).
Output data is valid after time t ACC.
--i tH H-
(PIN ttil
ALS l-- tACH
A0, A1, A2 ADDR
(PINSI7.13,19) VALID
--l (Les F-
(PIN13)
--"acc--l
DB7-DBO
@5317; - - - mo VALID “”L‘LWE'G
DATA DATA
- tCLE F-
Figure 3. Timing Diagram for the AD7581
SWITCHING TERMINOLOGY
tH: ALE pulse width requirement.
tALH Address Valid to latch hold time,
t Aur.Address Valid to latch set-up time.
ths: Address latch to Chip Select set-up time.
ttnys Chip Select pulse width requirement.
tACC:Chip Select to valid data propagation delay.
tcpz Chip Select to output data float propagation delay.
tCLz:Chip Select to low impedance data bus.
CHANNEL IDENTIFICATION
In some real-timc applications, it may be necessary to provide
an interrupt signal when a particular channel receives updated
data. To achieve this, it is necessary to identify which channel
is currently under conversion. The STAT output provides an
REV. A
identifying signal by staying low for an additional 64 clock
periods over normal (8 clock periods) when channel 0 is active.
This is illustrated in Figure 4. Memory update takes place on a
rising edge of a clock pulse and is completed in 200ns. This
occurs 6 clock periods before STAT goes low.
l--- BO CLOCK PERIODS ----l
FOR CHANNELS) TO 7 g f
g , AT
s CLOCK a CLOCK
PERIODS PERIODS
rnsvuous CHANNEL START NEXT CURRENT
Esme“ CONVERSION filtr"
MUX ADDRESS #1: MSB UPDATE
DECREM amen L COMPLETE
FOR CHANNEL 0 ' ,
I a CLOCK
64 CLOCK PERIODS --A P--.'. PERIODS
BCLOCK I
a CLOCK
PERIODS PERIODS
CHANNEL 1 START CHANNEL 0
UPDATE TRIAL CHANNEL ll UPDATE
COMPLETE, MUX
ADDRESS RESET TO
CHANNEL 7
Figure 4. STA T Output for Channel Identification
One simple circuit using the STAT output is shown in Figure
5. The time constant RC is chosen such that X2 ignores the
normal STAT low pulse width (8 clock periods wide) but
respond to the much wider STAT low pulse width (72 clock
periods wide) occurring during channel 0 conversion. Typically
for a lps clock period C = 0.022PF, R = 1.8kf2.
1/6 CD4009A
1/6 CD4009A 1/6 CD4009A
GOES HIGH WHEN
CHANNEL 0 IS ACTIVE
Figure 5. Hardware Channel Identification
Another Iyossibir1ty is to use the microprocessor to interrogate
the STAT output and hence determine channel identity. A
simple routine is shown in Figure 6.
Figure 6. Software Channel Identification
