AD7578BQ ,CMOS 12-BIT SUCCESSIVE APPROXIMATION ADCSpecifications subject to change without notice.
-2-
VCC= + 5V t 5%
VIN = 0 to Vcc
Vcc ..
AD7578KN ,CMOS 12-BIT SUCCESSIVE APPROXIMATION ADCSPECIFICATIONS‘ (an = +15ll,hx= +5ll,hs= -5ll,herr-- +510
Limit at Tm, Tmax
(T Grade) Units
0
..
AD7579JN ,LC2MOS 10-BIT SAMPLING A/D CONVERTERSSpecifications subject to change without notice.
REV. AADT579/A0758l]
TIMING spEtyFItyiTois1
..
AD7579JN/+ ,LC2MOS 10-BIT SAMPLING A/D CONVERTERSspecifications (SNR, Harmonic Distortion, IMD).
The AD7S79 and AD7580 are microproctsoeion1eible ..
AD7579JP ,LC2MOS 10-BIT SAMPLING A/D CONVERTERSspecifications are sample tested at + 25°C to ensure compliance. All input control signals are spec ..
AD7579KN ,LC2MOS 10-BIT SAMPLING A/D CONVERTERSFEATURES FUNCTIONAL BLOCK DIAGRAMS
20ps Conversion Time vm,
On-Chip Sample-Hold
50kHz Sampli ..
ADG813YRU ,0.5 CMOS 1.65 V to 3.6 V Quad SPST SwitchesGENERAL DESCRIPTION The ADG811, ADG812, and ADG813 are low voltage CMOS 1. <0.8 Ω o ver full temper ..
ADG819BRM ,0.5 OHM CMOS 1.8 V to 5.5 V 2:1 Mux/SPDT SwitchesGENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe ADG819 and the ADG820 are monolithic, CMOS, SPDT1. Very l ..
ADG819BRT-REEL7 , 0.5 ohm, CMOS, 1.8V to 5.5V, 2:1 Mux/SPDT Switch
ADG819BRT-REEL7 , 0.5 ohm, CMOS, 1.8V to 5.5V, 2:1 Mux/SPDT Switch
ADG822BRM ,CMOS Low Voltage 1 Ω Dual SPST SwitchesSPECIFICATIONS–40C to +125C, unless otherwise noted.) –40C to –40C to2Parameter 25C +85C +125 ..
ADG822BRMZ-REEL7 , 1 ohm CMOS, 1.8V to 5.5V, Dual SPST Switches
AD7578BQ-AD7578KN
CMOS 12-BIT SUCCESSIVE APPROXIMATION ADC
ANALOG
DEVICES
12-Bit Successive Approximation Mt
A07578
FEATURES
12-Bit Successive Approximation ADC
No Missed Codes Over Full Temperature Range
Low Total Unadjusted Error 1-1LSB max
High Impedance Analog Input
Autozero Cycle for Low Offset Voltage
Low Power, 75mW typ
Small Size: 0.3", 24-Pin Package
Conversion Time of 100515
GENERAL DESCRIPTION
The AD7578 is a medium speed, monolithic 12-bit CMOS A/D
converter which uses the successive approximation technique to
provide a conversion time of 100p.s. An auto-zero cycle occurs
at the start of each conversion resulting in very low system
offset voltages, typically less than 100wV. The device is designed
for easy microprocessor interfacing using standard control signals;
E (decoded device address), E (READ) and W (WRITE).
Conversion results are available in two bytes, SLSBS and 4MSBs,
over an 8-bit three state output bus. Either byte can be read
first. Two converter busy flags are available to facilitate polling
of the converter's status.
The analog input voltage range is 0V to + 5V when using a
reference voltage of "- 5V.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
AUTOIERO
COMPARATOR
IZ-BIT DAC
THREE [
STATE I DATA
OUTPUT ' I OUT
--n/ DRIVERS
CLK 0 cm
E E W BYSL DGND
PRODUCT HIGHLIGHTS
I, The AD7578 is a complete 12-bit A/D converter in a 24-pin
package requiring only a few passive components and a voltage
reference.
2. Autozero cycle realizes very low offset voltages, typically
100wV.
3. Standard microprocessor control signals to allow easy inter-
facing to most popular 8- and 16-bit microprocessors.
4. Monolithic construction for increased reliability and small
0.3", 24-pin package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
M7578-SPEClFliyiil0l1 2112;412:115;t:11:5:.:.;;1.¥.::;:m;:1“ = 14tlkhzextemal,
Parameter K Versionl B Versionl T Version' Units Conditions/Comments
ACCURACY
Resolution 12 12 12 Bits
Total Unadiusted Error2 t 1 t l t 1 LSB max
Differential Nonlinearity t l t l : 1 LSB max No missing codes guaranteed
Full Scale Error (Gain Error)3 t 1/4 t 1/4 t 1/4 LSB max Full Scale TC is typically lppm/°C
Offset Error3 t 1/4 t 1/4 t 1/4 LSB max Offset Error TC is typically 1ppm/°C
ANALOG INPUT
Analog Input Range 0to + 5 0to + 5 0to + 5 V VREF -, + 5.0V
Cam, Input Capacitance 8 8 8 pF typ
IAIN, Input Leakage Current AIN;0to + 5V
+ 25''C 10 10 10 nA max
Tmin to Tmax 100 100 100 nA max
REFERENCE INPUT
VREF (For Specified Performance) + 5 + 5 + 5 V t 5%
VREF Range + 4to + 6 + 4 to + 6 + 4 to + 6 V Degraded transfer accuracy
VREFInpuI Reference Current 1.0 1.0 1.0 mA max VREF= + 5.0V
POWER SUPPLY REJECTION
VnoOnly tl/8 tl/8 tl/8 LSB typ Voo-- +14.25Vto +15.75V
Vss = - 5V
VssOnly tl/8 tl/8 tl/8 LSB typ Vss= -4.75Vto -5.25V
Vrso - + 15V
LOGIC INPUTS
E(Pin 16), a(mn 17), Wmin 18)
BYSL (Pin 19)
V11. Input Low Voltage + 0.8 + 0.8 + 0.8 V max Vcc = + 5V t 5%
V.” Input High Voltage + 2.4 +2.4 +2.4 Vmin
im. Input Current
+25°C tl tl tl 11A max VlN-OtoVCC
Tmnton +10 +10 +10 wAmax
Cm Input Capacitance' 10 10 10 pF max
CLK (Pin 21)
Vu., InpuILow Voltage +0.8 +0.8 +0.8 Vmax Vcc-- + 5V t 5%
Viro Input High Voltage + 3.0 + 3.0 + 3.0 V min
lm, Input Low Current t 10 t 10 :10 " max
Im, Input High Current +1.5 +1.5 + 1.5 mA max
LOGIC OUTPUTS
DBO-DB7 (Pins 8-15), BUSY (Pin 20)4
VOL, Output Low Voltage + 0.4 + 0.4 + 0.4 v max Vcc - + 5V t 5%,1SINK =1.6mA‘
Vou, Output High Voltage + 4.0 + 4.0 + 4.0 V min Vcc = + 5V t 5%,IsouRce = 200WA
Floating State Leakage Current
(Pins 8-15) tl tl tl " max Vour=0Vto Vcc
Floating State Output Capacitance 15 15 15 pF max
CONVERSION TIMES
With External Clock 100 100 100 115 min fan; = l40kHz
With Internal Clock, T A = + 25C 50/ 1 00 50/ 100 50/ 100 11.5 min/max Using recommended clock components
as shown in Figure 6.
POWER REQUIREMENTS'
Vor, -k 15 + 15 + 15 V NOM t 5% for specified performance
Vss - 5 - 5 - 5 V NOM t 5% for specified performance
Vcc + 5 + 5 + 5 V NOM t 5% for specified performance
loo 7.5 7.5 7.5 mA max Typically 4mA with Voo= + 15V
Iss 7.5 7.5 7.5 mA max Typically 3mA with Vss = - 5V
ICC 100 100 100 WA typ VIN = Vu, 0r VIH
1.0 1.0 1.0 mA max -
Power Dissipation 75 75 75 mW typ W = km = cs = BUSY = Logic HIGH
'Temperature Range as follows: K, B Versions, - 40°C to + 85°C
T Version, - 55°C to + 125"C
ZIncludes Full Scale Error, Offset Error and Relative Accuracy.
3Guaranteed by design, not production tested.
'Iwo: for BUSY (pin 20) is 1.0 milliamp.
'Conversion Time includes autozero cycle time. - - -
6Power supply current is measured when AD7578 is inactive Le. , WR = RD = cs = BUSY = Logic HIGH.
Specifications subject to change without notice.
Al- REV. B
AD7578
TIMING SPECIFICATIONS1 (h, = +15v,vcc= +50ss--- -5ll,hsrr-- +510
Limit at + 25°C Limit at Tm, Tmax Limit at Tm, Tmax
Parameter (All Grades) (K & B Grades) (T Grade) Units Conditions/Comments
t. 0 0 0 ns min atom Setup Time
t2 (INT)2 200 240 280 ns min W Pulse Width (Internal Clock Operation)
t2 (EXT)2 10 10 10 us min W Pulse Width (External Clock Operation)
ts 0 0 0 ns min $10 W Hold Time
ts 130 160 200 ns typ
200 250 300 ns max W to BUSY Propagation Delay
ts 0 0 0 ns min BUSY 106 Setup Time
tg 0 0 0 ns min c-s to E Setup Time
ty 200 240 280 ns min E Pulse Width
tg 0 0 0 ns min CT; to E Hold Time
to 50 50 50 ns min BYSL to W Setup Time
ho 0 0 0 ns min BYSL to E Hold Time
t1 .3 150 180 200 ns typ
200 240 280 ns max lt-ID to Valid Data (Bus Access Time)
In" 20 20 20 ns min E to Three State Output
130 150 150 ns max (Bus Relinquish Time)
'Timing Specifications are guaranteed by design, not production tested. All input control signals are
specified with t, = tr= 20ns ( 10% to 90% of + 5V)and timed from a voltage level of + 1.6V. Data is timed from
VOH) VOL-
2When using an external clock source the W pulse width must be extended to provide the minimum
auto-zero cycle time of lows. See "External Clock Operation".
3t” is measured with the load circuits of Figure 3 and defined as the time required for an output to cross 0.8V or 2.4V.
'tn is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 4.
Specifications subject to change without notice.
c7; (PIN m
m (PIN 18)
BUSY (PIN 20)
a. High-Z to VOH
Figure I. Start Cycle Timing
b. High-Z to VOL
Figure 3. Load Circuits for Access Time Test ((17)
REV. B
SUSY (PIN 201 r
Q ts H
" (PIN m
RD IPIN 16l
BYTE SELECT
(PIN I9]
(PINS 8 ISI
_ ,q r. -/
mo" IMPEDANCE BUS ' LOW BYTE DATA HIGH BYTE DATA N-
-eture- - toy-- lit,,,
I I , i
In tn tta
THE TWO-BYTE CONVERSION REVSUIT CAN BE READ IN EITHER ORDER FIGURE IS FOR LOW BYTE. HIGH BYTE ORDER
F BYSL CHANGES WHILE CS ' RD ARE LOW THE DATA WILL CHANGE TO REFLECT THE BVSL INPUT
Figure 2. Read Cycle Timing
a. Vote to High-Z
g 10pF
b. VOL to High-Z
Figure 4. Load Circuits for Output Float Delay Test (t1)
AD7578
ABSOLUTE MAXIMUM RATINGS'
Storage Temperature
............ -6!rC to + 150°C
(TA = +25''C unless otherwise stated) Junction Temperature ................. + 150°C
VDD to DGND .M.......w....... _ 0.3V, + 17V DIP Package, Power Dissipation ........... 875mW
Vss to DGND ...W.............. +0.3V, - 7V 61A Thermal Impedance .............. 105°C/W
AGND to DGND ............ -0.3V, VREF +0. 3V Lead Temperature, Soldering (lOsecs) ....... + 260°C
Vcc to DGND ............. -0. 3V, VDD +0.3V Cerdip Package, Power Dissipation .......... 1000mW
VREF to AGND ............. -0.3V, Vor, +0.3V 91A Thermal Impedance .............. 67°C/W
AIN to AGND b............ -0.3V, VDD +0. 3V Lead Temperature, Soldering (lOsecs) ....... + 300°C
Digital Input Voltage to DGND
(Pins 16-19, 21) ............
Digital Output Voltage to DGND
(Pins 8-15, 20) ............ -0.3V, VDD +0.3V
Operating Temperature Range
Commercial (K Version) -40''C to + 85°C
Industrial (B Version) ........... -40oC to + 85°C
Extended (T Version) ........... - 55°C to + 125°C
-0.3V, VDD + th3V
CAUTION
Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V, which readily
accumulate on the human body and on test equipment, can discharge without detection. Although
these devices feature proprietary ESD protection circuitry, permanent
these devices if they are subjected to high energy electrostatic discharges. Therefore, proper
precautions are recommended to avoid any performance degradation or loss of functionality.
damage may still occur on
ESD SENSITIVE DEVICE
ORDERING GUIDE
Unadjusted
Temperature Error Package
Modell Range TMIN -Taeax Option2
AD7578KN - 40°C to + 85°C 1 ILSB N-24
AD7578BQ - 40''C to + 85°C t lLSB Q-24
AD7578TQ - 55''C to +125°C t lLSB Q-24
1To order MIL-STD-883 Class B processed parts, add /883B to part
number. Contact local sales office for military data sheet.
2N = Plastic DIP; Q = Cerdip,
DIP PIN CONFIGURATION
CA2 l '1 o iii) Vor,
AIN l 2 23 Vss
NC I 3 El NC
vREF I 4 21 CLK
AGND I 5 El BUSY
AD7578
DGND l 6 TOP VIEW 19 BYSL
(Not to Scale)
Vcc [E 18 W:
DB7 E 17 E
DB6 I 9 16 E
DBS 10 5 DB0 (L58)
DM 11 14 DBI
DB3 12 13 DB2
NC = NO CONNECT
REV. B
AD7578
PIN FUNCTION DESCRIPTION
\IO\M¥WN—‘
REV. B
MNEMONIC
DESCRIPTION
Autozero Capacitor Input. Connect other side ofcapacitor to AGND.
Analog Input
No Connect pin
Voltage reference input. The AD7578 is specified with VREF = + 5.0V.
Analog Ground
Digital Ground
Logic Supply. For Vcc = + 5V digital inputs and outputs are TTL compatible.
Three state data outputs. They become active when E lk E are brought low. Individual pin function
is dependent upon the Byte Select (BYSL) input.
DATA BUS OUTPUT, E & E = LOW
BYSL = HIGH BYSL = Low
Pin8 BUSY' DB7
Pin9 LOW2 DB6
Pin 10 Low2 DB5
Pin 11 Low2 DB4
Pin 12 DBI 1 (MSB) DB3
Pin 13 DBlO DB2
Pin 14 DB9 DBI
Pin 15 DB8 DB0 (LSB)
'BUSY (Pin 8) is a converter status flag and is HIGH during a conversion.
2Pins 9-11 output: logic LOW when BYSL is HIGH.
DBI 1-DB0 are the 12-bit conversion results, DB 11 is the MSB.
READ input. This active LOW signal, in combination with (i, is used to enable the output data three-
state drivers.
C_HIP SELECT Input. Decoded device address, active LOW. Used in combination with either It-ly or
WR for control.
WRITE Input. This active LOW signal, in combination with E, is used to start a new conversion.
When the AD7578 internal clock is used, the minimum W pulse width is t2 (INT). When an
external clock source is used, the minimum W pulse width must be extended to include the
autozero cycle time. For external clock operation, the minimum W pulse width is t2 (EXT).
BYTE SELECT. This control input determines whet_h_er th_e_high or low byte of data is placed on
the output data bus during a data READ operation (CS & RD LOW). See description of pins 8-
BUSY indicates converter status. §USY is LOW during conversion, otherwise BUSY is held at a
logic HIGH.
CLOCK Input for internal/external clock operation.
Internal : Connect RCLK and CCLK ./CCLK2 timing components. See Figure 6 and Figure 7.
External : Connect external 74HC compatible clock source as shown in Figure 8.
No connect pin.
Negative supply, - 5V.
Positive supply, + 15V.
