AD7576AQ ,LC2MOS 10 us uP-Compatible 8-Bit ADCSpecifications subject to change without notice.TIMING $PEtyFityrroi$1 (hm=+5ll,hsrrrc+1.23ll,NN0=i ..
AD7576BQ ,LC2MOS 10 us uP-Compatible 8-Bit ADCSpecifications are sample tested at + 25°C to ensure compliance. All input control signals are spec ..
AD7576JN ,LC2MOS 10 us uP-Compatible 8-Bit ADCSPECIFICATIONS
(Von = + 5ll; hsr = + 1.23V; ABND = BEND = W; fem = 2htitz external;
All sptxiti ..
AD7576KN ,LC2MOS 10 us uP-Compatible 8-Bit ADCGENERAL DESCRIPTION
The AD7576 is a low cost, low power, microprocessor compatible
8-bit analog ..
AD7578BQ ,CMOS 12-BIT SUCCESSIVE APPROXIMATION ADCSpecifications subject to change without notice.
-2-
VCC= + 5V t 5%
VIN = 0 to Vcc
Vcc ..
AD7578KN ,CMOS 12-BIT SUCCESSIVE APPROXIMATION ADCSPECIFICATIONS‘ (an = +15ll,hx= +5ll,hs= -5ll,herr-- +510
Limit at Tm, Tmax
(T Grade) Units
0
..
ADG794BRQZ-REEL7 ,Low Voltage, 300 MHz Quad 2:1 Mux Analog HDTV Audio/Video Switchspecifications T to T , unless otherwise noted. DD MIN MAXTable 1. 1 B Version Parameter 25°C TMI ..
ADG801BRM specifications –40°C to +125°C unless otherwise noted.)DD SS o o–40 C to –40 C too o oParameter ..
ADG802BRT specifications –40°C to +125°C unless otherwise noted.)DD SS o o–40 C to –40 C too o oParameter ..
ADG813YRU ,0.5 CMOS 1.65 V to 3.6 V Quad SPST SwitchesGENERAL DESCRIPTION The ADG811, ADG812, and ADG813 are low voltage CMOS 1. <0.8 Ω o ver full temper ..
ADG819BRM ,0.5 OHM CMOS 1.8 V to 5.5 V 2:1 Mux/SPDT SwitchesGENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe ADG819 and the ADG820 are monolithic, CMOS, SPDT1. Very l ..
ADG819BRT-REEL7 , 0.5 ohm, CMOS, 1.8V to 5.5V, 2:1 Mux/SPDT Switch
AD7576AQ-AD7576BQ-AD7576JN-AD7576KN
LC2MOS 10 us uP-Compatible 8-Bit ADC
ANALOG
DEVICES
FEATURES
Single +5V Operation with External Positive
Reference
Fast Conversion Time: 10.1.5
No Missed Codes Over Full Temperature Range
Microprocessor Compatible
Low Cost
Low Power (15mW)
100ns Data Access Time
GENERAL DESCRIPTION
The AD7576 is a low cost, low power, microprocessor compatible
8-bit analog-to-digital converter, which uses the successive
approximation technique to achieve a fast conversion time of
lows. The device is designed to operate with an external reference
of +1.23V (standard bandgap reference) and converts input
signals from 0V to ZVREF.
The part is designed for ease of microprocessor interface with
three control inputs (6, E and MODE) controlling all ADC
operations such as starting conversion and reading data. The
interface logic allows the part to be easily configured as a memory
mapped device. All data outputs use latched, three-state output
buffer circuitry to allow direct connection to a microprocessor
data bus or system input port. The output latches serve to make
the conversion process transparent to the microprocessor.
The part is designed for single + SV operation, has on-board
comparator, interface logic, and internal/external clock option.
This makes the AD7576 ideal for most ADC/wp interface
applications.
The AD7576 is fabricated in an advanced, all ion-implanted
high speed Linear Compatible CMOS (LCZMOS) process and is
packaged in a small, 0.3" wide, 18-pin DIP.
PRODUCT HIGHLIGHTS
1. Single Supply Operation
Operation from a single + 5V supply with a +1.23V reference
allows operation of the AD7576 with microprocessor systems
without any additional power supplies.
Information furnished by Analog Devices is believed to be accurate
and reliable. However, no responsibility is assumed by Analog Devices
for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implica-
tion or otherwise under any patent or patent rights of Analog Devices.
LCZIVIDS
s,,,,,,,!,,),,::,, sl,,),,),,):,!,,,',,, ml,,!,,.!,,,,,',,!,,,,,,',, 8- Bit sl,,),!,!!,,
2. Low Power
CMOS fabrication of the AD7576 results in a very low power
dissipation figure of 15mW typical.
3. Versatile Interface Logic
The AD7576 can be configured to perform continuous con-
versions or to convert on command. It can be interfaced as
SLOW-MEMORY or ROM, allowing versatile interfacing to
most microprocessors.
4. Fast Conversion Time
The fabrication of the AD7576 on Analog Devices' Linear
Compatible CMOS (LCZMOS) process enables fast conversion
times of lows, eliminating the need for expensive Sample-and-
Holds in many low frequency applications.
AD7576 F UNCTIONAL DIAGRAM
AGND is
VREF " DAC
cLK 5 OSCILLATOR
E , L LATCH ND 6 DB7
m 2 egg THREE sun‘ t
ouwur DRIVERS "
MODE 3 I DB0
Two Technology Way; Norwood, MA 02062-9106 U.S.A.
Tel:617l329-4700 Twx:710/396-65TT
Telex: 174059 Cables: ANALOG NORWOODMASS
SPECIFICATIONS
(Von = + 51H”: + 1.2311; AGND = BEND =0V; u-- Ihihz Mental;
All specifications u, to u, unless thhtmitse noted.)
AD7S76JNl AD7576KN
Parameter AD7S76AQ AD7576BQ AD7576SQ AD7576TQ Units Conditions/Comments
ACCURACY
Resolution 8 8 8 8 Bits
Total Unadjusted Error t 2 t l t 2 t 1 LSB max
Relative Accuracy t l t V, t 1 t 1/2 LSB max
Minimum Resolution for which
No Missing Codes is Guaranteed 8 8 8 8 Bits max
Full Scale Error -
25°C t l t 1 t 1 LSB max Full Scale TC is typically 5ppm/‘C
Tmton tl tl tl LSBmax
Offset Error2
25°C t v, t Ve t 1/2 t '/2 LSB max Offset TC is typically 5ppm/°C
Tmto Tu, t V2 t V2 t 1/2 t '/z LSB max
ANALOG INPUT
Voltage Range 0 to ZVREF 0 to ZVREF 0 to ZVREF 0 to ZVREF Volts ILSB = ZVREp/256; See F igure 4
DC Input Impedance 10 10 10 10 Mn min
REFERENCE INPUT
VREF (For specified Performance) 1.23 1.23 1.23 1.23 Volts t 5%
Isuw 500 500 500 500 Mmax
LOGIC INPUTS
CE, RE, MODE
VINL, Input Low Voltage 0.8 0.8 0.8 0.8 V max
Vrroo Input High Voltage 2.4 2.4 2 .4 2.4 V min
Irs, Input Current
25°C tl tl tl tl Mmax Vm=00rVDD
Tmton t 10 tio tio t10 Mmax VIN=00rVDD
Cm, Input Capacitance3 10 10 10 10 pF max
Vom, Input Low Voltage 0.8 0.8 0.8 0.8 V max
Vom, Input High Voltage 2.4 . 2.4 2.4 2.4 V min
IINL, Input Low Current 700 700 800 800 wh max VM = 0V
Irtoo Input High Current 700 700 800 800 M max VINE = VDD
LOGIC OUTPUTS
BUSY, DBO to DB7
VOL, Output Low Voltage 0.4 0.4 0.4 0.4 V max Ismx = 1.6mA
Vom Output High Voltage 4.0 . 4.0 4.0 4.0 V min ISOURCE = 40wh
DBO to DB7
Floating State Leakage Current t 1 t l t 10 t 10 WA max Vom- = 0 to 'a,
Floating State Output Capacitance' 10 10 10 10 pF max
CONVERSION TIME'
With External Clock 10 10 10 10 ps fCLx = 2MHz
With Internal Clock, TA = 25°C 10 10 10 10 us min Using recommended clock
20 20 20 20 us max components shown in Figure 3.
POWER REQUIREMENTS' .
Vos, + S + S + 5 + 5 Volts t 5% for Specified Performance
loo 6 6 7 7 mA max Typically 3m with VDD = + 5V
Power Dissipation 15 15 15 l 5 mW typ
Power Supply Rejection t 1/4 t 1/4 t V4 t V4 LSB max 4.75Vsvnos5.25V
'Temperature Ranges Ire as follows:
AD7576JN, KN 0 to + 70°C
AD7576AQ, BQ -25T to +85'C
AD75768Q, TQ - 55°C tty ' 125°C
2Otfset error is measured with respect to an ideal first code transition which occurs at 1/2LSB.
'Sampie tested at 25'C to ensure compliance.
'Accuracy may degrade at conversion times other than those specified. - -
'Power supply current is measured when AD7S76 is inactive Le. when cs = RD--- MODE = BUSY = logic HIGH.
Specifications subject to change without notice.
'gg2tggt F 'r:5i'i,i'iili'lir'ii'
TIMING SP il
Limit at + 25°C Limit at Tm, Tmax Limit at TU,, Tu,
Parameter (All Grades) (J , K, A, B Grades) (S, T Grades) Units Conditions/Comments
t1 0 0 0 ns min c-s tom Setup Time
te 100 100 120 ns max E to BUSY Propagation Delay
ts2 100 100 120 ns max Data Access' Time after)
t4 100 100 120 nsmin Emse Width
ts 0 0 0 nsmin c-StoR-DHoid Time
I62 80 80 100 ns max Data Access Time after BUSY
I73 10 10 10 ns min Data Hold Time
80 80 100 ns max
te 0 0 0 ns min BUSY to a Delay
'Timing Specifications are sample tested at + 25°C to ensure compliance. All input control signals are specified with tr= tf= 20ns (10% to 90% of + 5V)
and timed from a voltage level of 1.6V.
2:3 and ts are measured with the load circuits of Figure l and defined as the time required for an output to cross 0.8V or 2.4V.
3t7 is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
$100pF
b. High-Z to '
DEM DEM
I 100pF
a. High-Z to VOH
Figure 1. Load Circuits for Data Access Time Test
150x12, N.
F''"' 2%
CONTROL
INPUTS
DB7-DBO
DATA OUT
Figure 3. AD7576 Operational Diagram
DEM DEM
3m g 10pF g 101>F
DGND DGND
a. VOH to High-Z b. VOL to High-Z
Figure 2. Load Circuits for Data Hold Time Test
OUTPUT
CODE FULL SCALE
TRANSITION
l I " " = zvg
l f I 1 LSB = 2%
'tttttroot" ------ -F-F-+-_
01LSB 2LSB'S 3LSB'S L "
FS - TLSB
AIN. INPUT VOLTAGE [IN TERMS OF LSBS)
Figure 4. Nominal Transfer Characteristic for
Unipolar Operation
ABSOLUTE MAXIMUM RATINGS' AQ, BQ .................. - 25°C to + 85°C
Vos, TO AGND ................ - 0 3V, + 7V SQ, T_Q .................. - 55°C to + 125°C
Vor, TO DGND ................ -0 3V, + 7V Storage Temperature Range ......... -.. 65°C to + 150°C
AGND TO DGND ............... --0.3V, VDD Lead Temperature (soldering, 10 secs) ......... 300°C
Digital Input Voltage to DGND (Pins 1-3) . . . -0.3V, VDD Power Dissipation (Any Package) to + 75°C ..... 450mW
Digital Output Voltage to DGN D Derates above 75°C by ................ 6mW/°C
(Pins 4, 6-8, 10-14) .............. -0.3V, V131)
CLK Input Voltage (Pin S) to DGND ..... - 0.3V, VDD *Stresses above those listed un.e"A.bsoly.e yaximum Ryings'.'may.
vm to AGND ................. - 0.3V, VDD 5ause.perp"ent .damay.e to tht device. This 1sastress "tm/r Tly and
functional operation of the device at these or any other conditions above
AIN TO AGND .............'... - o. 3V, VDD those indicated in the operational sections of this specification is not
Operating Temperature Range implied. Exposure to absolute maximum rating conditions for extended
IN, KN ..................... 0 to + 70°C periods may affectdevice reliability.
CAUTION
ESD (Electro-Static-Discharge) sensitive device. The digital control inputs are zener protect-
ed; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The pro-
tective foam should be discharged to the destination socket before devices are removed.
WARNING!
PIN CONFIGURATION
:iqCieS..e.,V.s-t2
'ifii"-i'ii'iii'i'i'ii'] 'iiitll!
(£15 m a d3 EWE
ORDERING INFORMATION
Temperature Range and Package
Relative
Accuracy Plastic Cerdip' Cerdipt
(TU, to Tmax) 0 to + 70°C - 25''C to + 85''C - RPC to + 125''C
t ILSB AD7576JN AD7576AQ AD7576SQ
t VzLSB AD7576KN AD7576BQ AD7576TQ
'Analog Devices reserves the right to ship ceramic packages in lieu of cerdip packages.
fig cr q U E van
'rulE Elma
MODE CE Eil AIN
m7 CE $373123, Eil AGND
ch CE (Not to Scale) El nan (LSB)
DBr (M53) TE CCal DB1
nus E E DB2
DBS CE CE DB3
DGND IE " DB4
TERMINOLOGY
LEAST SIGNIFICANT BIT (LSB)
An ADC with 8-bits resolution can resolve 1 part in yr (i.e.,
256) of full scale. For the AD7576 with +2.46V full scale one
LSB is 9.6lmV.
TOTAL UNADJUSTED ERROR
This is a comprehensive specification which includes full scale
error, relative accuracy and offset error.
RELATIVE ACCURACY
Relative Accuracy is the deviation of the ADC's actual code
transition points from a straight line drawn between the devices
measured first LSB transition point and the measured full scale
transition point.
FULL SCALE ERROR (GAIN ERROR)
The gain of a unipolar ADC is defined as the difference between
the analog input levels required to produce the first and the last
digital output code transitions. Gain error is a measure of the
deviation of the actual span from the ideal span of F S - 2LSB's.
ANALOG INPUT RANGE
With VREF= +1.23V the maximum analog input voltage range
is 0 to +2.46V. The output data in LSB's is related to the
analog input voltage by the integer value of the following
expression:
256 AIN
Data (LSB's) =
-e ta 3" I I
, --tcoNv-----o-t
‘susv l ,'
Asa}. --t tg l‘ --', tr Ir-
HIGH IMPED N E NE HIGH IMPED NCE
DATA BUS A C l OLD DATA OAK I BUS A
Figure 5. Slow Memory Interface Timing Diagram
TIMING AND CONTROL OF THE AD7576
The AD7S76 is capable of two basic operating modes which are tur-AO ADDRESS BUS 5
outlined in the timing diagrams below. These two operating
modes are an Asynchronous Conversion Mode and a Synchronous 1 L A"':
Conversion Mode. The selection of the required operating mode ms“ ADDRESS T"
is determined by the status of the MODE pin. When this pin is DEMDE e cs A075“,
ls- HIGH, the devictperforr_ns conversions only when the required so R-tt
control signals (CS and RD) are applied; witlihis pigOW the W
device performs continuous conversions and CS and RD are ALE - A3535
used only to access the output data. I fl 030-037
SYNCHRONOUS CONVERSION MODE
In the Synchronous Conversion mode the AD7576 will perform ADM” DATA BUS 5
a conversion when requested to do so by the microprocessor. READY I
The MODE pin of the AD7576 is tied HIGH to place the device t''ll'rflgi''lirg%ih''sr'" FOR CLARITY
in Synchronous Conversion operation. Two interface options
\4 exist for reading the output data from the AD7576. Figure 6. AD7576 to 8085A-2 Slow Memory Interface
Slow Memory Interface
The first of these interface options is intended for use with AD7576 ensures that the microprocessor is not placed in a WAIT
microprocessors which can be forced into a WAIT STATE for state for an excessive amount of time. The timing diagram for
at least lows (such as the 8085A). The microprocessor starts a this interface is shown in Figure 5.
'r':geg,t,nI1i,2:1tte, tt,i2tg,1s1i1sltiftitat,'dct,1Ig,ig1tii,i' a Faster versions of many processors, including the 8085A-2, test
memo READ to the Iii)' 57 6 address BUSY sjbs uentlg the condition of the READY input very soon after the start of
goes 123w (forcing the microprocessor T(EADY 'IC,',','') L 'lllJ) an instruction te. Therefore, BUSY of the_AD7576 must gt)
placing the processor in a W AIT state When conversion is LOW very early in the cycle for the READY mput to be effective
. in forcing the processor into a WAIT state. When using the
y 'rat'." (BUSY goes HIGH) the p rocessor completes the memory 8085A-2, the processor SO status signal provides the earliest
. possible Indication that a READ 6iieraiion is about to occur.
The major advantage of this interface is that it allows the micro- Hence, SO (which is 0 for a READ cycle) provides the READ
processor to start conversion, WAIT, and then READ data with signal to the AD7576. The AD7576 connection diagram to the
a single READ instruction. The fast conversion time of the 8085A-2 is shown in Figure 6.
a fl fir " f-"-"-
_ P"' *I F“ I
RD -''''rri-o 4; I u i I -
--! t i‘- I : I
I 2 I I l l
- --------4- I - - - l- -
BUSY L, I ff- J Il----} ------- -
"l --ltrh-- f "Clr --ltrl--
I l 1; I
Figure 7. ROM Interface Timing Diagram
