AD7575 Fast Delivery |IC PHOENIX CO.,LIMITED

AD7575 ,CMOS, 5祍 8-Bit Sampling ADCGENERAL DESCRIPTIONBUSY DGNDThe AD7575 is a high speed 8-bit ADC with a built-in track/hold functio ..
AD7575AQ ,LC2MOS 5 us 8-Bit ADC with Track/Holdspecifications T to T unless otherwise noted)MIN MAX1Parameter J, A Versions K, B Versions S Versio ..
AD7575JN ,LC2MOS 5 us 8-Bit ADC with Track/Holdspecifications T to T unless otherwise noted)MIN MAX1Parameter J, A Versions K, B Versions S Versio ..
AD7575JP ,LC2MOS 5 us 8-Bit ADC with Track/HoldGENERAL DESCRIPTIONBUSY DGNDThe AD7575 is a high speed 8-bit ADC with a built-in track/hold functio ..
AD7575JP ,LC2MOS 5 us 8-Bit ADC with Track/HoldFEATURES FUNCTIONAL BLOCK DIAGRAMFast Conversion Time: 5 msVOn-Chip Track/Hold DDLow Total Unadjust ..
AD7575JR ,LC2MOS 5 us 8-Bit ADC with Track/HoldSpecifications subject to change without notice.Test Circuits+5V+5V3kV3kVDBNDBNDBNDBN3kV 10pF3kV 10 ..
ADG788BCP ,2.5ohm, 1.8V to 5.5V, +-2.5 V Triple/Quad SPDT Switches in Chip Scale Packagesapplications. All channels exhibit break-before-make switch-ing action preventing momentary shortin ..
ADG788BCPZ-REEL7 , 2.5ohm, 1.8V to 5.5V, 2.5V, -2.5V Triple/Quad SPDT Switches in Chip Scale Packages
ADG790BCBZ-REEL , Low Voltage, CMOS Multimedia Switch
ADG790BCBZ-REEL , Low Voltage, CMOS Multimedia Switch
ADG791GBCPZ-500RL7 , IC-Compatible, Wide Bandwidth, Quad, 2:1 Multiplexer
ADG794BRQZ ,Low Voltage, 300 MHz Quad 2:1 Mux Analog HDTV Audio/Video SwitchCharacteristics .8 Single Supply 3 Typical Application ........8 Absolute Maximum Ratings...... 5 ..

AD7575
CMOS, 5祍 8-Bit Sampling ADC
REV.BLC2MOS
5 ms 8-Bit ADC with Track/Hold
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7575 is a high speed 8-bit ADC with a built-in track/
hold function. The successive approximation conversion tech-
nique is used to achieve a fast conversion time of 5 ms, while the
built-in track/hold allows full-scale signals up to 50 kHz (386 mV/ms
slew rate) to be digitized. The AD7575 requires only a single +5 V
supply and a low cost, 1.23 V bandgap reference in order to convert
an input signal range of 0 to 2 VREF.
The AD7575 is designed for easy interfacing to all popular 8-bit
microprocessors using standard microprocessor control signals
(CS and RD) to control starting of the conversion and reading of
the data. The interface logic allows the AD7575 to be easily
configured as a memory mapped device, and the part can be
interfaced as SLOW-MEMORY or ROM. All data outputs of
the AD7575 are latched and three-state buffered to allow direct
connection to a microprocessor data bus or I/O port.
The AD7575 is fabricated in an advanced, all ion-implanted high
speed Linear Compatible CMOS (LC2MOS) process and is
available in a small, 0.3" wide, 18-lead DIP, 18-lead SOIC or in
other 20-terminal surface mount packages.
FEATURES
Fast Conversion Time: 5 ms
On-Chip Track/Hold
Low Total Unadjusted Error: 1 LSB
Full Power Signal Bandwidth: 50 kHz
Single +5 V Supply
100 ns Data Access Time
Low Power (15 mW typ)
Low Cost
Standard 18-Lead DlPs or 20-Terminal
Surface Mount Packages
PRODUCT HIGHLIGHTSFast Conversion Time/Low Power
The fast, 5 ms, conversion time of the AD7575 makes it
suitable for digitizing wideband signals at audio and ultra-
sonic frequencies while retaining the advantage of low
CMOS power consumption.On-Chip Track/Hold
The on-chip track/hold function is completely self-contained
and requires no external hold capacitor. Signals with slew
rates up to 386 mV/ms (e.g., 2.46 V peak-to-peak 50 kHz sine
waves) can be digitized with full accuracy.Low Total Unadjusted Error
The zero, full-scale and linearity errors of the AD7575 are so
low that the total unadjusted error at any point on the trans-
fer function is less than 1 LSB, and offset and gain adjust-
ments are not required.Single Supply Operation
Operation from a single +5 V supply with a low cost +1.23 V
bandgap reference allows the AD7575 to be used in 5 V
microprocessor systems without any additional power
supplies.Fast Digital Interface
Fast interface timing allows the AD7575 to interface easily to
the fast versions of most popular microprocessors such as the
Z80H, 8085A-2, 6502B, 68B09 and the DSP processor, the
TMS32010.
AD7575–SPECIFICATIONS
(VDD = +5 V, VREF = +1.23 V, AGND = DGND = 0 V; fCLK = 4 MHz external;
all specifications TMIN to TMAX unless otherwise noted)
NOTESTemperature ranges are as follows:
J, K Versions; 0°C to +70°C
A, B Versions; –25°C to +85°C
S, T Versions; –55°C to +125°COffset error is measured with respect to an ideal first code transition that occurs at 1/2 LSB.Sample tested at +25°C to ensure compliance.Accuracy may degrade at conversion times other than those specified.Power supply current is measured when AD7575 is inactive i.e., when CS = RD = BUSY = logic HIGH.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1
NOTESTiming specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tr = tf = 20 ns (10% to 90% of +5 V)
and timed from a voltage level of 1.6 V.t3 and t6 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.t7 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
(VDD = +5 V, VREF = +1.23 V, AGND = DGND = 0 V)
Test Circuits
ABSOLUTE MAXIMUM RATINGS*
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD
Digital Input Voltage to DGND . . . . . . .–0.3 V, VDD + 0.3 V
Digital Output Voltage to DGND . . . . . .–0.3 V, VDD + 0.3 V
CLK Input Voltage to DGND . . . . . . . . .–0.3 V, VDD + 0.3 V
VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD
AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD
Operating Temperature Range
Commercial (J, K Versions) . . . . . . . . . . . . . .0°C to +70°C
Industrial (A, B Versions) . . . . . . . . . . . . .–25°C to +85°C
Extended (S, T Versions) . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . . .450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . .6 mW/°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7575 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
b High-Z to VOLa. High-Z to VOH
Figure 1.Load Circuits for Data Access Time TestFigure 2.Load Circuits for Data Hold Time Test
a. VOH to High-Zb. VOL to High-Z
DGND
DBN
DGND
3kV
100pF
DBN
+5V
DGND
3kV
10pF
DBN
+5V
AD7575
TERMINOLOGY
LEAST SIGNIFICANT BIT (LSB)
An ADC with 8-bits resolution can resolve 1 part in 28 (i.e.,
256) of full scale. For the AD7575 with +2.46 V full-scale one
LSB is 9.61 mV.
TOTAL UNADJUSTED ERROR
This is a comprehensive specification that includes full-scale
error, relative accuracy and offset error.
RELATIVE ACCURACY
Relative Accuracy is the deviation of the ADC’s actual code
transition points from a straight line drawn between the devices
measured first LSB transition point and the measured full-scale
transition point.
SNR
Signal-to-Noise Ratio (SNR) is the ratio of the desired signal to
the noise produced in the sampled and digitized analog signal.
SNR is dependent on the number of quantization levels used in
the digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical SNR for a sine wave input is given by
SNR = (6.02 N + 1.76) dB
where N is the number of bits in the ADC.
FULL-SCALE ERROR (GAIN ERROR)
The gain of a unipolar ADC is defined as the difference between
the analog input levels required to produce the first and the last
digital output code transitions. Gain error is a measure of the
deviation of the actual span from the ideal span of FS – 2 LSBs.
ANALOG INPUT RANGE
With VREF = +1.23 V, the maximum analog input voltage range
is 0 V to +2.46 V. The output data in LSBs is related to the
analog input voltage by the integer value of the following
expression:
Data (LSBs) =
SLEW RATE
Slew Rate is the maximum allowable rate of change of input
ORDERING GUIDE
NOTESTo order MIL-STD-883, Class B process parts, add /883B to part number.
Contact local sales office for military data sheet. For U.S. Standard Military
Drawing (SMD), see DESC drawing #5962-87762.E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip, R = SOIC.
PIN CONFIGURATIONS
PLCCDIP/SOICLCCC
DGND
DB5
BUSY
DB6
DB7 (MSB)
CLK
DB4
DB3
VDD
VREF
AIN
AGND
DB2
DB1
DB0 (LSB)1912310111213
NC = NO CONNECT
BUSY
CLK
DB7 (MSB)
DB6
DB5
AIN
AGND
DB0 (LSB)
DB1
DB2RDCSV
REF
DGNDNC
DB4DB3
NC = NO CONNECT
BUSY
CLK
DB7 (MSB)
DB6
AIN
AGND
DB0 (LSB)
DB1
DB2CSNCV
REF
DB5
DGND
DB4DB3
TIMING AND CONTROL OF THE AD7575
The two logic inputs on the AD7575, CS and RD, control both
the starting of conversion and the reading of data from the part.
A conversion is initiated by bringing both of these control inputs
LOW. Two interface options then exist for reading the output
data from the AD7575. These are the Slow Memory Interface
and ROM Interface, their operation is outlined below. It should
be noted that the TP pin of the AD7575 must be hard-wired
HIGH to ensure correct operation of the part. This pin is used
in testing the device and should not be used as a feedthrough pin
in double-sided printed circuit boards.
SLOW MEMORY INTERFACE
The first interface option is intended for use with microproces-
sors that can be forced into a WAIT STATE for at least 5 ms.
The microprocessor (such as the 8085A) starts a conversion and
is halted until the result of the conversion is read from the con-
verter. Conversion is initiated by executing a memory READ to
the AD7575 address, bringing CS and RD LOW. BUSY subse-
quently goes LOW (forcing the microprocessor READY input
LOW), placing the processor into a WAIT state. The input
signal, which had been tracked by the analog input, is held on
the third falling clock edge of the input clock after CS and RD
have gone LOW (see Figure 12). The AD7575 then performs a
conversion on this acquired input signal value. When the con-
version is complete (BUSY goes HIGH), the processor com-
pletes the memory READ and acquires the newly converted
data. The timing diagram for this interface is shown in Figure 3.
*LINEAR CIRCUITRY OMITTED FOR CLARITY
SO = 0 FOR READ CYCLES
The major advantage of this interface is that it allows the micro-
processor to start conversion, WAIT, and then READ data with
a single READ instruction. The fast conversion time of the
AD7575 ensures that the microprocessor is not placed in a
WAIT state for an excessive amount of time.
Faster versions of many processors, including the 8085A-2, test
the condition of the READY input very soon after the start of
an instruction cycle. Therefore, BUSY of the AD7575 must go
LOW very early in the cycle for the READY input to be effec-
tive in forcing the processor into a WAIT state. When using the
8085A-2, the processor S0 status signal provides the earliest
possible indication that a READ operation is about to occur.
Hence, S0 (which is LOW for a READ cycle) provides the
READ signal to the AD7575. The connection diagram for the
AD7575 to 8085A-2 Slow Memory interface is shown in
Figure 4.
ROM INTERFACE
The alternative interface option on the AD7575 avoids placing
the microprocessor into a WAIT state. In this interface, a con-
version is started with the first READ instruction, and the sec-
ond READ instruction accesses the data and starts a second
conversion. The timing diagram for this interface is shown in
Figure 5. It is possible to avoid starting another conversion on
the second READ (see below).
Conversion is initiated by executing a memory READ instruc-
tion to the AD7575 address, causing CS and RD to go LOW.
Data is also obtained from the AD7575 during this instruction.
This is old data and may be disregarded if not required. BUSY
goes LOW, indicating that conversion is in progress, and re-
turns HIGH when conversion is complete. Once again, the
input signal is held on the third falling edge of the input clock
after CS and RD have gone LOW.
The BUSY line may be used to generate an interrupt to the
microprocessor or monitored to indicate that conversion is
complete. The processor then reads the newly-converted data.
Alternatively, the delay between the convert start (first READ
instruction) and the data READ (second READ instruction)
must be at least as great as the AD7575 conversion time. For
the AD7575 to operate correctly in the ROM interface mode,
CS and RD should not go LOW before BUSY returns HIGH.
Normally, the second READ instruction starts another conver-
sion as well as accessing the output data. However, if CS and
BUSY
DATA
Figure 3.Slow Memory Interface Timing Diagram
AD7575
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 6.AD7575 to 6502/6809 ROM Interface
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 7.AD7575 to Z-80 ROM Interface
Figures 6 and 7 show connection diagrams for interfacing the
AD7575 in the ROM Interface mode. Figure 6 shows the
AD7575 interface to the 6502/6809 microprocessors while the
connection diagram for interfacing to the Z-80 is shown in
Figure 7.
As a result of its very fast interface timing, the AD7575 can also
be interfaced to the DSP processor, the TMS32010. The
AD7575 will (within specifications) interface to the TMS32010,
running at up to 18 MHz, but will typically work over the full
clock frequency range of the TMS32010. Figure 8 shows the
connection diagram for this interface. The AD7575 is mapped
at a port address. Conversion is initiated using an IN A, PA
instruction where PA is the decoded port address for the
AD7575. The conversion result is obtained from the part using
a second IN A, PA instruction, and the resultant data is placed
in the TMS32010 accumulator.
In many applications it is important that the signal sampling
occurs at exactly equal intervals to minimize errors due to sam-
pling uncertainty or jitter. The interfaces outlined previously
require that for sampling at equidistant intervals, the user must
count clock cycles or match software delays. This is especially
difficult in interrupt-driven systems where uncertainty in inter-
rupt servicing delays would require that the AD7575 have prior-
ity interrupt status and even then redundant software delays
may be necessary to equalize loop delays.
This problem can be overcome by using a real time clock to
control the starting of conversion. This can be derived from the
clock source used to drive the AD7575 CLK pin. Since the
sampling instant occurs three clock cycles after CS and RD go
LOW, the input signal sampling intervals are equidistant. The
resultant data is placed in a FIFO latch that can be accessed by
the microprocessor at its own rate whenever it requires the data.
This ensures that data is not READ from the AD7575 during a
conversion. If a data READ is performed during a conversion,
valid data from the previous conversion will be accessed, but the
conversion in progress may be interfered with and an incorrect
result is likely.
If CS and RD go LOW within 20 ns of a falling clock edge, the
AD7575 may or may not see that falling edge as the first of the
three falling clock edges to the sampling instant. In this case, the
sampling instant could vary by one clock period. If it is impor-
tant to know the exact sampling instant, CS and RD should not
IMPEDANCE BUSDATA
BUSY
Figure 5.ROM Interface Timing Diagram

Partno	Mfg	Dc	Qty	Available	Descript
AD7575	ADI	N/a	2	avai	CMOS, 5祍 8-Bit Sampling ADC