AD7574BQ ,CMOS uP-COMPATIBLE 8-BIT DACANALOG
DEVICES
CMOS
pLP-Compatihle 8-Bit Mt
AD7574
AD7574BQ ,CMOS uP-COMPATIBLE 8-BIT DACGENERAL DESCRIPTION
AD7574 is a low-cost, 8-bit pp compatible ADC which uses
the successive-app ..
AD7574JN ,CMOS uP-COMPATIBLE 8-BIT DACSPECIFICATIONS (h, = +5ll, VREF = --1W, Unipolar Configuration, RCLK = 130m, cm = ltnpF, unless oth ..
AD7574KN ,CMOS uP-COMPATIBLE 8-BIT DACSPECIFICATIONS (h, = +5ll, VREF = --1W, Unipolar Configuration, RCLK = 130m, cm = ltnpF, unless oth ..
AD7574KN .. ,CMOS uP-COMPATIBLE 8-BIT DACSPECIFICATIONS (h, = +5ll, VREF = --1W, Unipolar Configuration, RCLK = 130m, cm = ltnpF, unless oth ..
AD7574TQ ,CMOS uP-COMPATIBLE 8-BIT DACapplications. Small size (18-pin DIP) and monolithic
reliability will find wide use in avionics, i ..
ADG779BKS ,CMOS 1.8 V to 5.5 V, 2.5 ohm SPDT Switch/2:1 Mux In Tiny SC70 PackageGENERAL DESCRIPTIONPRODUCT HIGHLIGHTSThe ADG779 is a monolithic CMOS SPDT (single-pole,1. Tiny 6-Le ..
ADG779BKS-REEL ,CMOS, Low Voltage 2.5 Ohms SPDT Switch / 2:1 MuxGENERAL DESCRIPTIONPRODUCT HIGHLIGHTSThe ADG779 is a monolithic CMOS SPDT (single-pole,1. Tiny 6-Le ..
ADG781 ,CMOS, Low Voltage 2.5 Ohm Quad SPST Switches in Chip Scale PackageGENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe ADG781, ADG782, and ADG783 are monolithic CMOS 1. 20-Lead ..
ADG781BCP ,2.5 ohm Quad SPST Switches in Chip Scale PackageGENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe ADG781, ADG782, and ADG783 are monolithic CMOS 1. 20-Lead ..
ADG788BCP ,2.5ohm, 1.8V to 5.5V, +-2.5 V Triple/Quad SPDT Switches in Chip Scale Packagesapplications. All channels exhibit break-before-make switch-ing action preventing momentary shortin ..
ADG788BCPZ-REEL7 , 2.5ohm, 1.8V to 5.5V, 2.5V, -2.5V Triple/Quad SPDT Switches in Chip Scale Packages
AD7574AQ-AD7574BQ-AD7574JN-AD7574KN-AD7574KN ..-AD7574TQ
CMOS uP-COMPATIBLE 8-BIT DAC
ANALOG
DEVICES
pP-Compatible 8-Bit Mt
AD7574
FEATURES
B-Bit Resolution
No Missed Codes over Full Temperature Range
Fast Conversion Time: Ttips
Interfaces to pp like RAM, ROM or Slow . Memory
Low Power Dissipation: 30mW
Ratiometric Capability
Single HN Supply
Low Cost
lnmmal Comparator and Clock Oscillator
GENERAL DESCRIPTION
AD7574 is a low-cost, 8-bit pp compatible ADC which uses
the successive-approximations technique to provide a con-
version time of 15ps,
Designed to be operated as a memory mapped input device,
the AD75 74 can be interfaced like static RAM, ROM, or slow
memory. lts c-s (decoded device address) and 15
(READ/WRITE control) inputs are available in all pp memory
systems. These two inputs control all ADC operations such as
starting conversion or reading data. The ADC output data bits
use three-state logic, allowing direct connection to the pP data
bus or system input port.
Internal clock, +SV operation, on-board comparator and
interface logic, as well as low power dissipation (30mW) and
fast conversion time make the AD7S74 ideal for most ADC/PP
interface applications. Small size (18-pin IMP) and monolithic
reliability will find wide use in avionics, instrumentation, and
process automation applications.
ORDERING GUIDE
FUNCTIONAL BLOCK DIAGRAM
DB, - Dire
DATA OUT DRIVERS
tr-BIT DAC
SU CCESSIVE
Am Bars
5 AGND
APPROXIMATION
REGISTER
INTERFACE
& CONTROL
AD7S74
CLK Daub
PIN CONFIGURATION
VDD E . " DGND
Vner E 7 CLK
Bors E " c-s
Am cr E ‘E’
Am 7 -
AGND E 5 ' u BUSY
037mm) 7 Eoeouse)
DBs E CCtl DB1
'"s E 21m
DB4 9 10 DB3
TOP VIEW
(NOT TOSCALE)
Differential
Temperature Nonlinearity Package
Model Range (LSB) 0ption*
AD7S74JN 0°C to +70°C t-7/8 max N-24
AD7574KN 0°C to +70°C :3/4 max' N-24
AD7S74AQ -25''C to +85°C t7/8 max Q-24
AD7S74BQ -25°C to +85°C t3/4 max Q-24
AD7S74SQ -55''C to +125°C 1-7/8max Q-24 .
AD7S74TQ -55°C to + 125°C t3/4 max Q-24
*N = Plastic DIP; Q = Cerdip.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assu med by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703 wa: 710/394-6577
Telex: 924491 Cable: ANALOG NORWOODMASS
M7574-SPEClFliyrrl0hlS
M SPECIFICATIONS i% = +5ll, hs, = -m Unipolar Configuration, Rch = 18tm, cm = 1llopF, unless otherwise noted)
Limits
Parameter T, = +25''C TL,,, TU,' Units Conditions/Comments
ACCURACY
Resolution 8 8 Bits
Relative Accuracy Error
J, A, S Versions :3/4 t3/4 LSB max Relative Accuracy and Differential Nonlinearity are measured
K, B, T Versions 1' 1/2 t 1/2 LSB max dynamically using the external clock circuit of Figure 7b.
Differential Nonlinearity Clock frequency is 500kHz (conversion time 15ws).
J, A, S Versions :7/8 t7/8 LSB max
K, B, T Versions :3/4 13/4 LSB max
Full Scale Error (Gain Error) Full Scale Error is measured after calibrating out offset error. See
J, A, S Versions t5 t6.5 LSB max Figure 8a and associated calibration procedure for offset. Max Full
K, B, T Versions :3 14.5 LSB max Scale change from +25°C to Tmin or Tmax is t2LSB.
Offset Error
J, A, S Versions *60 80 mV max Maximum Offset change from +25°C to Tm, or TL, is t20rnV.
K, B, T Versions "-30 +50 mV max
Mismatch Between Boss (Pin 3)
and Am (Pin 4) Resistances' :1.5 tl.5 % max
ANALOG INPUTS
Input Resistance
At Vim: (Pin 2) 5/10/15 5/10/15 k0. min/typ/max
At Bors (Pin 3) 10/20/30 10/20/30 kn min/typ/max
At Am (Pin 4) 10/20/30 10/20/30 kn miMyplmax
'L, (for Specified Performance) - 10 - 10 V 35% for specified transfer accuracy.
VREF Range' -5 to - IS -5 to - 15 V Degraded transfer accuracy.
Nominal Analog Input Range
Unipolar Mode 0 to +|vm1 v
Bipolar Mode -lVREr/ to +[VREFI V
LOQC INPUTS_
RD (Pin 15), CS (Pin 16)
VIN" Logic HIGH Input Voltage +3.0 +3.0 V min
VINL Logic LOW input Voltage +0.8 +0.8 V max
Im Input Current 1 10 " max 1% = 0V, Vor,
Cm Input Capacitance' 5 5 pF max
CLK (Pin 17)
Voo, Logic HIGH Input Voltage +3.0 +3.0 v min
VIN]. Logic LOW Input Voltage +0.4 +0.4 V max
[mu Logic HIGH Input Current +2 +2 mA max During Conversion: VIMCL,<7 2 ancm
Inn. Logic LOW Input Current 1 10 " max During Conversion vlmcuc s VINLLCLK)
(see circuit of Figure 7b if external clock operation is required).
LOGIC OUTPUTS
BUSY (Pin 14), DB, to DBo (Pins S-U)
Vor, Output HIGH Voltage +4.0 +4.0 V min ISOURCE = 4011A
VOL Output LOW Voltage +0.4 +0.8 V max ISINK = 1.6mA
ILKG DB, to DBo Floating Stage Leakage l 10 " max VOUT = 0V or Vor,
Floating State Output Capacitance
(DB, to D130)5 7 7 pF max
Output Code Unipolar Binary, Offset Binary See Figures 8a, 9a, 10a, and 8b, 9b, 10b.
POWER REQUIREMENTS
Vor, +5 +5 V 15% for specified performance.
1m) (STANDBY) 5 5 mA max Arr; = 0V, ADC in RESET condition.
IREF VREF divided by 5kn max Conversion complete, prior to RESET.
'Temperature ranges as follows: J, K, Versions, 0°C to +70°C; A, B.Wrsions, -25''C to --85''C; S, T Versions; -55''C m + 125°C.
'Typical offset temperature coefficient is t150wW'C.
317(30Fs/RA".. mismatch causes transfer function rotation about positive Full Scale. The effect is an offset and a gain term when using the circuit of Figure 9a.
'Typical value, not guaranteed or subject to test.
'Guaranteed but not tested.
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are Zener protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are removed.
ESD SENSITIV DEVIC
REV. A
AD7574
= = = ed)
Limit at Limit at Limit at
Symbol Specification TA = +25''C T, = IL, TA = IL, Conditions
STATIC RAM INTERFACE_MODE (See Figure 1 and Table I)
tes gnlsiWidth Requirement 100ns min 150ns min 150ns min
twscs R_D to CS Setup Time 0 min 0 min 0 min
t CS to BUSY Propagation Delay 90ns typ 70ns typ 150ns typ -
mm 120ns max 120ns max l80ns max BUSY Load = 20PF
120ns type lOOns typ l80ns typ -
- 150ns max 150ns max 200ns max BUSY Load = IOOPF
tBsn BUSY to IE) Setup Time 0 min 0 min 0 min
tBSCS BUSY to CS Setup Time 0 min 0 min 0 min
t Data Access Time 120ns typ lOOns typ lSOns typ
RAD 150ns max lSOns max 220ns max DBo-DB, Load = lOOpF
Mons typ 220ns typ 300ns typ
300ns max 300ns max 400ns max DBs-DB, Load = 100pF
(mm Data Hold Time 80ns typ 40ns typ 120ns typ
50ns min 30ns min 80ns min
- - 120ns max 80ns max l80ns max
(mes CS to RD Hold Time 250ns max 200 ns max 500ns max
tum. Reset Time Requirement 3ws min Bus min Bus min
ttosvrswr Ctmversion Time
Using Internal Clock Oscillator See Typical Data of Figure 7a
tcomn tknversion Time chK = 500kHz
Using External Clock 15ws 15ws 15ws Circuit of Figure 7b
ROM INTERFACE MODE (See Figure 2 and Table II)
tmu, Data Access Time Same as RAM Mode
trum D_ata Hold Time Same as RAM Mode
[warn RD HIGH to BUSY 400ns typ Mons typ lps typ -
110mm; Delay L.5p Lows, Lows BUSY Load = 20 pF
Ins: BUSY to RD LOW Setup Time RD can go LOW prior to BUSY = HIGH, but must not
return HIGH until = BUSY HIGH. See Table II.
tCONVERT Conversion Time See Typical data of Figure N. Add Ass to
Using Internal Clock Oscillator data shown in Figure 7a for ROM Mode
SLOW - MEMORY INTERIACE MODE (See F igure 3 and Table III)
tam, cs to BUSY Propagation Delay Same as RAM Mode
Russ: Reset Time Requirement Same " RAM Mode
tm Data Access Time Same " RAM Mode
tum Data Hold Time Same as RAM Mode
ICOWT Conversion Time Same as RAM Mode
ABSOLUTE MAXIMUM RATINGS“
Vor, to AGND .......................... ov, +7.0V Industrial (A, B Versions) ............... -25''C to +85°C
Vos, to DGND ........................... 0V, +7.ov Extended (S, T Versions) ............... -55''C to + 150°C
AGND to D GND .-.-............... -0.3V, Vor, Storage Temperature Range ............... -65°C to + 150°C
Digital Input Voltage to D GND (Pins 15 and 16) . . . --0. 3V, +15.0V Lead Temperature (soldering, 10 secs) .............. +300°CV
Digital Output Voltage to Dorm (Pins 6-14) ........ -0.3V, Vor, Power Dissipation (Package)
CLK Input Voltage (Pin 17) toDGND ............ -0.3V, VDD Plastic (Suffix N)
VREF (Pin 2) B............................. IZOV to +70°C ............................. 670mW
VBOFS (Pin 3) ._.._.................W.._.t.. t20V Derate above +70°C by ................... 8.3mW/°C
VAIN (Pin 4) .............................. t20V Oerdip (Suffix Q)
Operating Temperature Range to +75°C ..r.....l..l...l..t 450mW
Commercial (J, K Versions) ................ 0°C to +70°C Derate above +75°C by .................... 6mWPC
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
at or above this specification is not implied. Exposure to above maximum rating conditions for extended periods may affect device reliability.
TERMINOLOGY
RESOLUTION: Resolution is a measure of the nominal analog
change required for a l-bit change in the ND converter’s digital
output. While normally expressed in a number of bits, the analog
resolution of an n-bit unipolar A/D converter is (2-") VREF).
Thus, the AD7574, an 8-bit A/D converter, can resolve analog
voltages as small as (1/256) (VREF) when operated in a unipolar
mode. When operated in a bipolar mode, the resolution is (l/ 128)
(V REF). Resolution does not imply accuracy. Usable resolution is
limited by the differential nonlinearity of the A/D converter.
RELATIVE ACCURACY: Relative accuracy is the deviation of
the ADC's actual code transition points from a straight line
REV. A -3-
drawn between the devices' measured zero and measured full
scale transition points. Relative accuracy, therefore, is a measure
of code position.
DIFFERENTIAL NONLINEARITY: Differential nonlinearity
in an ADC is a measure of the size of an anlog voltage range
associated with any digitial output code. As such, differential
nonlinearity specifies code width (usable resolution). An ADC
with a specified differential nonlinearity of in bits will exhibit
codes ranging in width from lLSB -n LSB to lLSB +n LSB.
A specified differential nonlinearity of less than t1LSB guaran-
tees no-missing-codes operation.
AD7574
TIMING & CONTROL OF THE AD7574
STATIC RAM INTERFACE MODE
Table l and Figure 1 show the truth table and timing require-
ments for AD7574 operation as a static RAM.
A convert start is initiated by executing a memory WRITE
instruction to the address location occupied by the AD7574
(once conversion has started, subsequent memory WRITES
have no effect). A data READ is performed by executing a
memory READ instruction to the AD7574 address location.
BUSY must be HIGH before a data READ is attempted, i.e.
the total delay between a convert start and a data READ must
be at least as great as the AD7574 conversion time. The delay
can be generated by inserting NOP instructions (or other
program instructions) between the WRITE (start convert) and
READ (read data) operations. Once BUSY is HIGH (conver-
sion complete), a data READ is performed by executing a
memory READ instruction to the address location occupied
by the AD7574. The data readout is destructive, i.e. when RD
returns HIGH, the converter is internally reset.
The RAM interface mode uses distinctly different commands
to start conversion (memory WRITE) or read the data (memory
READ). This is in contrast to the ROM mode where a memory
READ causes a data READ and a conversion restart.
Table J. Truth Table, Static RAM Mode
" MEMORY want now on OTHER MEMORY READ IEMOHV mm:
''"'Tpasrif,' I TO Anmt l msrnue‘nous I TO AD7574 I 10 A0151.
Amuse £1". sum IS umu mates Awnsss
Emu 16) -i,'tC)-t,,,,,TC-",,Cj, l
m’l - t-.md)- l
RD IPIN l5) -u/, L -1 I , .l
NI: _-'co''vE't' Inn"
SUSY Inn T6) J,,,,,,, L- ef,,,,,, "um I
Jttt/ /i',ii,,iiii,:,i,,,,Cses,i-,,,',ii, ///W-m”/
Figure 1. Static RAM Mode Timing Diagram
AD7 7574 INPUTS AD7574 OUTPUTS ,
CG R-D iiWN DB7-DBD AD7574 OPERATION
L II " HIGH T WRITE CYCLE (START CONVERT)
L '1. " HIGH 2 *DATA READ CYCLE (DATA READ)
L .r H DATA _ HIGH E RESET CONVERTER
H xl x HIGH T NOT SELECTED
L H L HIGH E NO EFFECT. CONVERTER BUSY
L = L HIGH 2 NO EFFECT, CONVERTER BUSY
i. .1" L HIGH T NOT ALLOWED. CAUSES
INCORRECT CONVERSION
Note 1: If rrogoes LOW Lt2. HIGH when CS Is LO_W, the ADC' Is
internally reset. RD has no effect while CS Is HIGH.
Sea application hint No.1.
ROM INTERFACE MODE
Table II and Figure 2 show the truth table and timing require-
ments for interfacing the AD7574 like Read Only Memory.
Cg is held LOW and converter operation is controlled by the
1V) input. The AD75 74 E input is derived from the decoded
device address. MEMRD should be used to enable the address
decoder in 8080 systems. VMA should be used to enable the
address decoder in 6800 systems. A data READ is initiated by
executing a memory READ instruction to the AD7574 address
location. The converter is automatically restarted when R-D-
I EMORY R EAD MEMORY R EAD
MlCMPRtNIE8aNt m mm: moron omen Iusrnucnous mum)-
oemmou ADORCSS
RDIrmISI l El )m
-1--y m _t"'vs'te 1m
m (rm u) , I j ""T
_ mo'. u te limo“ munr'
1-090 Tr.
Inns Hal ,'"G" I DATA HIGH I It men z"
Figure 2. ROM Mode Timing Diagram (trs Held LOW)
returns HIGH. As in the RAM mode, attempting a data READ
before BUSY is HIGH will result in incorrect data being read.
The advantage of the ROM mode is its simplicity. The major
disadvantage is that the data obtained is relatively poorly
defined in time inasmuch as executing a data READ auto-
matically starts a new conversion. This problem can be over-
come by executing two READS separated by NO -OPS (or
other program instructions) and using only the data obtained
from the second READ.
Table II. Truth Table, ROM Mode
AD7574 INPUTS AD7574 OUTPUTS AD7 74 OPER TION
c-s R-r, BUSY DB7 - D30 5 A
L = H HIGH 2 - DATA DATA READ
L .u- 1 DATA - HIGH T RESET AND
- 7 _ _ _ _ _ _ START NEW CONVERSION
L 1 L HIGH Z NO EFFECT, CONVERTER BUSY
L I L HIGH Z NOT ALLOWED, CAUSES
INCORRECT CONVERSION
SLOW-MEMORY INTERFACE MODE
Table III and Figure 3 show the truth table and timing require-
ments for interfacing the AD7574 as a slow-memory. This
mode is intended for use with processors which can be forced
into a WAIT state for at least 12ps (such as the 8080, 8085
and SC/MP). The major advantage of this mode is that it
allows the pp to start conversion, WAIT, and then READ data
with a single READ instruction.
In the slow-memory mode, tTg and KO are tied together. It is
suggested that the system ALE signal (8085 system) or SYNC
signal (8080 system) be used to latch the address. The decoded
device address is subsequently used to drive the AD7574 CTS
and W) inputs. BUSY is connected to the microprocessor
READY input.
When the AD7574 is NOT addressed, the c-s and TTO inputs
are HIGH. Conversion is initiated by executing a memory
READ to the AD7574 address. BUSY subsequently goes LOW
(forcing the pP READY input LOW) placing the pp in a WAIT
state, When conversion is complete (BUSY is HIGH) the pp
completes the memory READ.
Do not attempt to perform a memory WRITE in this mode,
since three - state bus conflicts will arise.
REV. A
AD7574
" I DEVICE
COMPLETE NOT
MEM READ I SELECTED
_r5'i'"
DEVICE MEMORY READ w
MK9RtN'RtNWSS0R i AD7574 ADDRESS PINWAIT _
1WERATI0N SELECTED) STATE quLE IS Low)
B's " 1
(PINS 15AND 16l
A tcttrtt l-tct''"'""- i
uN Inn f‘bi tum: b;
DBr-DBo /
(nus “3) , men 2 % mu mom E;
Figure 3 Slow Memory Mode Timing Diagram
ttRf and AD Tied Together)
HUS (FIN 14)
Table III. Truth Table, Slow Memory Mode
Am 74 INPUTS AD7574 ourpurs
"CT,' & .1) BUSY DBrDBo AD7574 OPERATION
H H HIGH T. NOT SELECTED
= H a L HIGH 7. START CONVERSION
l L HIGH 1 CONVERSION IN PROGRESS,
"r' IN WAIT STATE
l .J- “Kill Z _ DATA CONVERSION COMPLETE,
pp READS DATA
A" " DATA - HIGH z CONVERTER RliShT
AND DESiiLliCTED
H H HIGH Z NOT SELizCThD
GENERAL CIRCUIT INFORMATION
BASIC CIRCUIT DESCRIPTION
The AD75 74 uses the successive approximations technique to
provide an 8 - bit parallel digital output. The control logic was
designed to provide easy interface to most microprocessors.
Most applications require only passive clock components (R &
C), a -10V reference, and +5V power.
vm, Vnsr Am Bars
l-BIY DAC
us, - ma.
DATA our Dimgs 5 Nsru,
SUCCESSNE
APPROXIMATION
REGISTER
AD757I
INTERFACE
& CONTROL BUSY
6th Damn
Figure 4. AD7574 Functional Diagram
Figure 4 shows the AD7574 functional diagram. Upon receipt
of a start command either via the CS or IV) pins, BUSY goes
low indicating conversion is in progress. Successive bits,
starting with the most significant bit (MSB) are applied to
the input of a DAC. The comparator determines whether the
addition of each successive bit causes the DAC output to be
greater than or less than the analog input, Am. If the sum of
the DAC bits is less than Am, the trial bit is left ON, and the
next smaller bit is tried. If the sum is greater than Am, the
trial bit is turned OFF and the next smaller bit is tried.
REV. A
Each successively smaller bit is tried and compared to AIN in
this manner until the least significant bit (LSB) decision has
been made. At this time ITOTA-r goes HIGH (conversion is com-
plete) indicating the successive approximation register contains
a valid representation of the analog input. The TV) control (see
the previous page for details) can then be exercised to activate
the three-state buffers, placing data on the DBo - DB7 data
output pins. Er, returning HIGH causes the clock oscillator to
run for 1 cycle, providing an internal ADC reset (i.e. the SAR
is loaded with code 10000000).
DAC CIRCUIT DETAILS
The current weighting D/A converter is a precision multiplying
DAC. Figure 5 shows the functional diagram of the DAC as
used in the AD7574. It consists of a precision Silicon Chrom-
ium thin film R/2R ladder network and 8 N -channel MOS-
FET switches operated in single - pole - double - throw.
The currents in each 2R shunt arm are binarily weighted, i.e.
the current in the MSB arm is VREF divided by 2R, in the
second arm is VREF divided by 4R, etc. Depending on the
DAC logic input (A/D output) from the successive approx-
imation register, the current in the individual shunt arms is
steered either to AGND or to the comparator summing point.
Am Bars
" R " 2n
' , ' f
ruse , l use SUMMING mp a T
'(057) '(085) how .'totw Pomr A A Ott
successws - APPROXIMAYIDNS REGISTER
ouasa,
Figure 5. D/A Converter As Used In AD7574
