AD7572AQ05 ,LC2MOS COMPLETE, HIGH SPEED 12-BIT ADCFEATURES
12-!!! Resolution and Accuracy
Fm Convection Time
A0757ZXX05: 5m
A07572XX12: ".Sps
Co ..
AD7572BQ05 ,LC2MOS COMPLETE, HIGH SPEED 12-BIT ADCANALOG
DEVICES
chmos
Complete, High Speed 12-Bit Mt
M757fl
AD7572BQ05 ,LC2MOS COMPLETE, HIGH SPEED 12-BIT ADCFEATURES
12-!!! Resolution and Accuracy
Fm Convection Time
A0757ZXX05: 5m
A07572XX12: ".Sps
Co ..
AD7572JN05 ,LC2MOS COMPLETE, HIGH SPEED 12-BIT ADCGENERAL DESCRIPTION
The AD7S72 is a complete, 12-bit ADC that offers high speed
performance com ..
AD7572JN12 ,LC2MOS COMPLETE, HIGH SPEED 12-BIT ADCFEATURES
12-!!! Resolution and Accuracy
Fm Convection Time
A0757ZXX05: 5m
A07572XX12: ".Sps
Co ..
AD7572JN-12 ,LC2MOS COMPLETE, HIGH SPEED 12-BIT ADCANALOG
DEVICES
chmos
Complete, High Speed 12-Bit Mt
M757fl
ADG759BCP ,3 ohm, 4-/8-Channel Multiplexers in Chip Scale PackageGENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe ADG758 and ADG759 are low voltage, CMOS analog 1. Small 2 ..
ADG774ABRQ ,Low Voltage 400 MHz Quad 2:1 Mux with 3 ns Switching Timespecifications T to T unless otherwise noted.)DD MIN MAX B VersionT toMINParameter 25CT Uni ..
ADG774ABRQZ-REEL , Low Voltage, 400 MHz, Quad 2:1 Mux with 3 ns Switching Time
ADG774BR ,CMOS 3 V/5 V, Wide Bandwidth Quad 2:1 Muxspecifications T to T unless otherwise noted.)DD MIN MAX B Version toTMINParameter +258CT Un ..
ADG774BR. ,CMOS 3 V/5 V, Wide Bandwidth Quad 2:1 Muxspecifications T to T unless otherwise noted.)DD MIN MAX B Version toTMINParameter +258CT Un ..
ADG774BRQ ,CMOS 3 V/5 V, Wide Bandwidth Quad 2:1 MuxFEATURESFUNCTIONAL BLOCK DIAGRAMLow Insertion Loss and On Resistance: 4 V TypicalOn-Resistance Flat ..
AD7572AQ05-AD7572BQ05-AD7572JN05-AD7572JN12-AD7572JN-12-AD7572KN05-AD7572KN12-AD7572LN05-AD7572LN12
LC2MOS COMPLETE, HIGH SPEED 12-BIT ADC
ANALOG
DEVICES
Complete, High Speed 12-Bit Mt
M757fl
FEATURES
12-811 Resolution and Accuracy
Fm Conversion Time
A07572XX05: Spa
A07572XX12: "SPS
Compm- with On-Chlp Romance
PM But Access Time: 90m
Low Power: 13timW
Smell. 0.3". M-Pin Package
and 28-Termiml Surface Mount Package:
GENERAL DESCRIPTION
The AD7S72 is a complete, 12-bit ADC that offers high speed
performance combined with low, CMOS power levels. The
AD7572 uses " accurate, high speed DAC and comparator in a
succusivc-npproximation loop to achieve a fast conversion time.
An on-chip, buried Ttner diode; provides a stable reference
voltage to give low drift performance over the full temperature
range and the specified accuracy is achieved without any user
trims. An on-chip clock circuit is provided, which may be used
with a crystal for smd-alonc operation, or the clock input may
be driven from an external clock source such " I divided-dom:
microprocessor clock. The only other external components re-
quired for basic operation of the AD7572 are decoupling capacitors
for the supply voltages and reference output.
The AD7572 has a high speed digital interface with threevmte
dm outputs and an operate under the control of sundard
microprocessor Read (tith md decoded address (CS) signals.
lnterfxtx timing is sumcieruly fast to allow the AD7572 to operate
with most popular microprocessors, with three-sutc enable
times of only 90nt and bus relinquish times of 75ns.
The AD7572 is fabricated in Analog Devices Linear Compatible
CMOS process (LC’MOS), an advanced, all ion-implanted
process that combines fast CMOS logic and linear, bipolar circuits
on a single chip, thus achieving excellent linear performance
while still retaining low CMOS power levels.
The AD7572 is available in both 0.3" wide , M-pin DlPs and in
a 28-tennitul plastic leaded chip carrier (PLCC) and leadless
cenmic chip carrier (LCCC).
REV. A
Information furnished by Analog Devices is believed to be acourate and
reliable. However. no responsibility is assumed by Analog Devices for its
use. nor for any infringements of patents or other rights of third parties
whichmay result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
Wm" ll Cl! II"
. eri-drbtbd-e
ou' on m 9. mm mm on
" CLIN
PRODUCT HIGHLIGHTS
l. Fast, Sits Ind 12.5ws conversion times make the AD7S72
ideal for a wide range of applications in telewnununications,
sonar and radar signal processing or any wideband data
acquisition system.
2. On-chip buried-chcr reference has temperature coeificient
as low as 25ppmf'C, giving low full-scale drift over the operating
temperature range.
3. Stable DAC and comparator give excellent linearity and low
zero error over the full temperature range.
4. Fast, casy-to-use digital interface has three-sme bus access
time: of 90ns and bus relinquish times of 75ns, allowing the
AD7S72 to interface to most popular microprocessors.
s. LCZMOS circuitry gives low power drain (l35mW) from
+ S, -15 volt supplies.
6. 24-pin 0.3" package offers space saving over parts in 28-pin
0.6" DIP.
On. Technology Way. PO. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tut: 017/329-4700 Fax: 617/326-8703 wa: 710/334-6577
"tew. szust Cable: ANALOG NOHWOODMASS
M757b-$PiitlFltyiiltlhl
ih, = $ll 1 Mt, hs = -w , 5%, G.. t.5tlllg for Mmmll5, 1ttlitfttt
ADTS'IZXXIZ. Ill Stmifitatitmt Uttt u, untess otherwise noted. Specification:
apply to Slow Memory 'lotta.)
LA. s K, B, T C, U
Pm Vcniou' Verdun 1.an Vcabu Units Test Wants
ACCURACY
Resolution II II 12 12 Bits
Itttegml Natlinearity tiy' t 25% , I s. I t 1/2 ' ll LSB mu
Tpor,,., tt tl ' [/2 3m LSBw
DiftetentialNoalittearity xt xl :1 xl LSBmu
Minimum Resohttiat for which no
MissiagCbdes m Guaranteed 12 12 It l2 Bil!
otteetEmreEii+2S'C t4 e3 :3 =3 LSBmu
1-. tor.. ..t 6 a S , 4 2 4 LSB mu Typical Change aver Temp ls , ILSB
FastatetFsyErrrPtd, 4251; :15 tlt) , l0 , I0 LSBM Vnrewivse - ISV;FS-5V
Full Scale Tty" 45 " " " ptrmrC mu Ida} Last Cate Transition "
FS - 312L531
ANALOG INPUT
1rtputvolageRange 0to +5 ho ' ' 0to " Ono 4 S Volts For BipouroperjtoaSee
lnpuxCul-mu " " 3.5 3.5 MM Figuraloar lt
INTERNAL REFERENCE VOLTAGE
Iuroutmitg +25'c -s.2/-s.3 -s.2/-s.3 411-5.; -5.21-5.3 VminNmu -s.2sv , w.
V.” OutputTC 40 20 N 10 ppm/‘CIyp
OutpulCuml Sink Capability 550 $50 Bo $50 " max Emml Load Should Not Change
DuringConvcnion
POWER SUPPLY REJECTION
VDDOnly , III ' 1/2 3 ll) 11/2 LSB lyp “Change. vss " - lsv
V90 6 + MISV to + 5.25V
V“Only ' Ill , IQ :112 21/2 LSB WP FSCtuttge,Voo-- SV
Vss I -14.2$V ttt -15.75V
LOGIC INPUTS
' EB. HBEN.CLK m
Vumdnwl Loonlugc +0.8 ' 0.8 ' 0.8 + (ht V max Von " SV , 5%
vtrm,rnttutHighVtsttage +2.4 02.4 +3.4 +21 Vmin
Cm,'iuputapsciuace no lo 10 10 meu
, HBEN
tm,tttputCtuteat t I0 no t10 :10 wArnax Vm - OloVnn
CLK IN
too Input Curran s. to , 20 ' 20 t 10 M mu Vm . 0 to Vnn
LOGIC OUTPUTS
011-com, m.c1.x our
Vm., Output Low voltage . 04 . 0.4 ' 0.4 ' 0.. V mu lynx " LOMA
Vou,thttput High Voltage ' " ' 4.0 + 4.0 + 4.0 V min Isotmcs " ttlowh
DI I-DOI8
FhtmirtgSateLmugeCttrrettt , l0 , l0 , lo ' l0 “A mu
Flouin; Sm: thnputcsimcitante' 15 IS IS 15 pF mu
CONVERSION TIME
AD7S7ZXXO§
Synchmom Clock ' ' ' S p: mu ko: " 2.5MHz. See Under
Asynchmmus Clock 4.8/5.2 4.8/5.2 0.8/5.2 4,8/5.2 v.5 min/mu Control Inputs Symhmniation
AD7S72XXIZ
$rttrtttmttmstltock l2.5 13.5 I2.3 12.5 .umu {cut " IMH,
AsyttchmtttttisC1ock 12/13 12/13 12/13 12/13 mmin/mmu
POWER REQUIREMENT S
Vno ' S + S - ' " V NOM s. 5% for Spedfted Performance
vs, - " ~13 - IS - IS VNOM rH%forSrerifiedNrftmmnre
1m; 7 7 , 7 MM t2-lit..Vvoo,hm-sv.
Us' II n I2 12 Mint: cs " RD: Vup,AlN-SV
PtmerDim'smirm 135 us us 135 thyp
215 115 IIS IIS . mWI'nu
msrtete--srertstrmt LLLVMWMQ APC.
A, l,CVmiou-; - MT Io ' 'st
3.1,UVcniau'. - ”turf RS'C.
’tmmwmum.
’run-hk‘n: " arsar-rSimgt6otesh-mamTa _ . 19c m_wn...
't-imes--ettsxdrgt.
's-art-tarea-re.
'ttsou-re-ti-G-tte-rain-tvest.,:"'" I © . BUSY I HIGH.
Wain: Mum m"ttttttgt tttttke.
REV. A
AD7572
nmms tagtgtmitttgTitt1 m, = Mrs, -m
Limitat +25% Limit at lies, TU, Limit at Tu,, T.,.,
Pamela: (All Grades) (J,K,L, A, B,CGndes) (S,T, UGrades) Units CmtditiottslCotrunetta
t. 0 0 0 nsmin eg toiiT5setupTime
tg I90 230 270 ns max 1U5to1mWPropagttion Delay
u' 90 110 no ns mu Data Access Tinie after Im, th. = 20PF
125 150 170 ns max Data Access Time after FECL: 100pF
u tt ts ts nsmin Et5PuiseWidth
ts o o o nsmin "atoMHokiTirne
l" 70 90 100 mm Data Setup Time dtch
t,' 20 20 20 ns min Bus Relinquish Time
75 M 90 ns max -
t. 0 0 0 nsmin HBEN tog Setup Time
u 0 0 0 nsmin HBEN to RD Hold Time
tio 200 200 200 nsmin Delay Between Successive
Read Operations
'Timin; 'peeitkations an ample tested " + 2VC to ensure compliance. All input control signals are specifted with
tr = If " $ttsti0%to90hof en0andtitnedfrr-ltagrkvelofl.6v.
'tsutdtoremeasuredwith thelood citruitsofFigute I anddermedttthetinte mquind form
mttputrocrttssthtvor2.4V.
h, is dermed a the time required forthe data line, lochm: t).W when loaded with the circuits ofFigure 2.
Simirtcatiotts whim ID change without ttutice.
ABSOLUTE MAXIMUM RATINGS'
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect-
ed; however, permanent damage may occur on unconnected devices subject ttt high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
DIN MN
"it tk tk
ocuo I $00,413
b. High-Zto VOL (t3)
and VUH to VOL thr)
a. High-Z to Van (ts)
and VOL to Von (ts)
Figure 1. Load Circuits for Access Time
DIN DEN
3m "PF ttltr'
oano I $06»
a. V0,, to High-Z b, VOL to High-Z
Figure 2. Load Circuits for Output Float Delay
(T, = ' 25'C unless otherwise noted)
Hoo to DGND ................ -0.3V to + 7V
Vssto DGND ................. +0.3V to - 17V
AGND to DGND ............ -0.3V, vm, + 0.3V
MN 10 AGND ................ - 15V to +15V
Digital Input Voltage to DGN D
(CLK IN, HBEN, "kT5, CE) .....
Digital Output Voltage to DGN D
(Dll-DO/B, CLK OUT, BUSY) . . .
-th3V, Von +0.3V
-0.3V, 'a, +0.3V
Operating Temperature Range
Commercial (J, K, I. Versions) ......... 0 to f 7tPC
Industrial (A, B, C Versions) ....... -25"C to +85°C
Extended (S, T, U Versions) ....... - 55°C to +125°C
Storage Temperature ............ - 65'C to + 150°C
Lead Temperature (Soldering, lOsecs) ........ + 300''C
Power Dissipation (Any Package) to + 75°C . 1,000mW
Derates above +75°C by .............. lOmWPC
'Slru: above those listed under "Absolute Muimum Ruinp" my cum pumancnl
damage to the device, This it a stress ming only and functional openxion of the device
" these or my other condition above tltuse indicated in the upcmional muons ofthis
specification is not implied. Erposure ttt absolute maximum mung conditions for ex-
tended periods may titem device reliability.
WAR N l il G ('
REV. A
A07572
ORDERING GUIDE'
Convenion Temperature Full-Scde Aeturaey Package
Model’ Time Range TC Grade Option“
AD75721N05 $ws 0 to +7it'C 45pimfC 211.88 N-24
AD7572KN05 $ps 0 to +70°C 25ppm/‘C 211.88 N-24
AD7572LN05 $ps 0 to +70'C 25»me 2 IIZLSB N-24
AD7572JP05 'sas 0 to +70'C 45ppm/T :ILSB P-28A
AD7572KP05 Sp: 0 to +7tt'C 25ppmPC :ILSB P-28A
AD7572LP05 $ws il to +70'C ZSppme 21121.53 P-28A
AD7572AQ05 $ps ~25“C to +85°C 4Sppml'C :ILSB Q44
AD757ZBQ05 Sp: -25‘C to +85'C 25pptMC :ILSB Q-24
AD757ZCQ05 5p: -25'C to +85'C 25ppm/T tl/2LSB Q-24
AD7572$Q05 5ws --55'C to +125°C 45ppm/T :ILSB Qc24
AD757rrQ05 5ws -55°C to +125°C 25ppm/“C 311.513 0.24
AD7572UQOS bs -WC to +125°C 25ppm/‘C :1/2LSB Q-24
AD75728E05 5ps -55°C to +125'C 45pptnt'C I ILSB E-28A
AD7572TE05 Sws -55'C to +125'C 25ppttfC =1LSB E-ZSA
AD7S72UEOS 5m -55‘C to +125°C 25»me , IIZLSB E-28A
AD75721N12 123ws t) to t70T, 45ppnfC YILSB N.24
AD7S72KNIZ 12.5ws 0 to +70'C 25ppml°C :ILSB N-24
AD7S72LN12 12.5ps 0 to +70'C 25ppm/‘C :IIZLSB N-24
AD757211’12 12.Sps 0 to +70'C 45ppm/‘C :ILSB P-28A
AD7572KP12 12.511: " to +70°C 25ppm/'C t ILSB Path
AD7572LP12 123ws 0 to +70'C ZSppme xl/ZLSB P-28A
AD7572AQIZ 123ws -25'C, to +85'C 45ppmfC 111.58 Q-24
AD7572BQ12 12.5ps -2rc to +85°C 25»me :ILSB Q-24
AD7572CQIZ 12.Sps -2rc to +85°C 25ppru/T t1/2LSB Q-24
AD7572SQ12 12.5»: -M'C to +125% 45pprnfC t ILSB Q-24
AD757ZTQ12 123ws -55t' to +125'C ZSppme , ILSB Q-24
AD7572UQI 123ws -55''C to +125°C 2Spprnf'C :IIZLSB Q-24
AD7572$E12 12.5sss -55''C lo +125°C 45ppmfc :ILSB E-ZBA
AD7572TEIZ 12.5ps -M''C ttt +125‘C 25ppml°C :ILSB E-28A
AD7S72UE12 12ass -55°C to +125'C 25pprnPC :1/ZLSB E-ZSA
'Analog Devices Reserves the right to ship cctunic irN34A) in lieu cerdip (Q24) hermetic package.
'To order MIL-STD-RBS, Class B pmd puns. add [8833 to pan numbcr. Count: your ma sales office
for military data sheet. For US. Standard Military Drawing (SMD) tee DESC Drawing #5962-87591.
'D - Cami: DIP; E - iasdlesttkamicChipthrrier(uXX0; N = leichP; P " Hudclndcd
Chip Carrier (PLCC); Q * Cadip.
PIN CONFIGURATIONS
DIP LCCC
"'"-i"""
AM t . E Vac
thte t E Va
A670 1 n m
cm . 11 a
on E E E
m a #07571 El min
" , - w.) E tMOUt mono Sun)
trr ' n cum
u ' " om
m " E om
pa u E cam; " u " u u n u
mu umm azssggg
m-wmzcv 8 '' q
M- REV. A
AD7572
"I'oortv “11.5108". Chi! I 'nxnud pm. 064 Mt" to w
nub. Oman yam Inn) n19 ame- - military am than
'oayq0ertr-rsttterehttosettteittterarditorrmatkitetmtticrmcuers,
Tut MIR "Mat Cttlp Cather.
'MTC. Indus Gum Chip Carin.
REV. A
PIN FUNCTION DESCRIPTION
DIP Pin No. Mnemonic Description
1 MN Amiogrrtput.
2 V”; Voltage Reference Output. The AD7S72 has itsown internal - 5.25V reference.
3 AGND Analqrthound.
4. . . ll D11 . . D4 'rhteestatedtuotmmts.TheytsecrmtesctivewhencmndABarebtrmghtiow.
13 . . . 16 D3I11 . . . 130/8 Indieid1nlpinfitnctioru%tepettdetttupottHighByteEmb1e(HBENMnput,
mrnusomwr "i5suri'b" " LOW
Hal I135 Plat ’81 lb! Ha! Ham Hall 13 III“ III Pb“
HBEN-HIGH 0311 D810 DB9 DN LOW LOW LOW 11 DBIO DB9 DBt
'Dll . . . DtmrrtheADCdtaoutptstpim.
0811 . . . DB0uetheibbitemtversioeumula,DBitistheMsB.
12 DGN D Digital Ground.
17 CLK 1N Clock Input pin. An external TTL compatible clock may be applied to this pin. Altcmatively
a crystal or ceramic monator my be connected between CLK IN
(Pin 17) and CLK OUT (Pin 18).
18 CLK OUT Clock Output Pin. An inserted CLK 1N signal appears at CLK OUT when an external clock
is used. See CLK 1N (Pin l) description for crystal (manner).
19 HBEN High Byte Enable input. Its primary function is to multiplex the 12-bits of conversion data onto
the lower D7 . . . DOIS outputs (4MSBs or ' LSBs). See Pin description 4 . . . 11 and 13 . . _ 16
It also disables convcrsion start when HBEN is high. _
20 kTi READ input. This active LOW signal, in coniuncu'on with CS_is used to enable
the output data three state drivers and initiate a conversion if cs and HBEN are low.
21 cg CHIP SELECT' Input. This active LOW signal, in coniunction with 135 is used to enable
the output data three state drivers and initiate a conversion if F5 and HBEN are low.
22 BUSY BU§Y output indicates converter status. BU§Y is LOW during convenient.
23 Vss Negative Supply, - 15V.
24 1loo Positive Supply, + 5V.
OPERATIONAL DIAGRAM
ORDERING INFORMATION " An operational diagram for the AD7572 is shown in
CONVERSION TIME = 5ps Figure 3. The AD7572 is a 12-bit successive approximation
mem‘ Run: M rm... 096“: ND converter. The addition of just a crystal/ceramic resonator
F n s , Arm.” and a few capacitors enables the device to perform the analog-
TC Olo mrc -tPCu, arc -65'Cut +i2rC to-digital function.
PUgtieDtP Hennetie'Dtr Hmmlic’ DIP o w . "
15M t usn Amsnmm Annmoos amsnsoos ANALOG
25mm , 11.88 AD7S72KNOS Amsnwos AU7S7II‘QUS BINT
zswurc t 1121.53 AD7S72LNN AD7572CQOS AD7S72UQO$ la, aw,
MC’ LCCty
65M ' ILSB AD75721N5 Amsnsw
zsmnc :ILSB Ammxms AD1$7ZTE05
15mm: , mun mnmm: Amsnuw
CONVERSION TIME = 12.5ps
Tommumnuowm
Fa8aeak Acmuy
Tc Grade ttta um: -trcto us-r. ~ss-c-o -ttf'C.
mum itemettPDt Hcmuk’Dlr
csppmrc ttt.SB 11015121an Aomonnz AD1S7ZSQI2
"tmmrr. , ILSB AD7S72KNIZ ADISTZBQII Ar37872TQU
25mm: , ustn AD7S71LNI2 ammmn mmzuun
PLCC' LCCC*
6er t thu Amsmmz amsnsw
zsmrc , ILSB Ammxm nomz'mz i,
25mm , IIZLSB AD7512LPIZ Amsnum
NOTES , I
" DAYA GUS
LDHHXXM- 25M": GVSYWMIC umron.
"ttt322t1ttr. , .MHICIVSTW “SONIA" OI
Ct and co WWW VALUES DCRNO Oil CRYSYAUCIMMIC nuowuoa
WWIACTURER. m VALU!‘ ARE FROM mu Mpr.
Figure 3. AD7572 Operational Diagram
A07572
CONVERTER DETAILS
Conversion start is controlled by the m. it end HBEN
inputs. At the sun of conversion the successive apprrtximatinn
register (SAR) is reset and the three-mte data outputs ue
enabled. Once a conversion cycle has begun it cannot be re-
started.
During eonvetxion, the internal lbbit voltage mode DAC
output is sequenced by the SAR hmn the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 4, the AIN input connects to the comparator input
via 2.51:0. The DAC which has a similar 2.5m output
impedance connects to the same comparator input. Bit decisions
are nude by the commuter (zero crossing detector) which
checks the addition of each successive weighted bit from the
DAC output. The MSB decision is made 80ns (typically)
after the second falling edge of CLK IN following 1 convenion
start. Similarly, the tsucceeding bit decisions are nude ap-
proximately 80tts after I CLK IN edge until conversion is
finished. At the end of conversion, the DAC output current
balances the MN input current. The SAR contents (12-bit
date word) which represent the MN input time! is loaded
into a 12-bit latch.
Car, - - "l cowmm
I fir-e, I
Figure 4, AD7572 AIN Input
cur-it-rl, l f Cr" I I
t... Cl Fi ramp“ m Cl
"soc-ur-Ch-ur-v-ur-ur-
0.11 DIIO ttot tmit
(W1 Ilsl)
Figure 5. Operating Waveforms Using an External Clock
Source for CLK IN
CONTROL INPUTS SYNCHRONIZATION
In applications where the m control input is not synchronized
with the ADC clock then conversion time can vary from 12
to 13 CLK 1N periods. This is because the ADC waits for
the first falling CLK IN edge after conversion start before
the conversion procedure begins. Without synchronization,
thisdehyeanvery frornzemtoiutentireclockperiod.1fa
constant conversion time is required, then the following
approach ensures a fired 5ws conversion time for the
AD7572XX05 and Rigs for the AD7572XX12: when in.
itiating a convenion, RD must go low on either the rising
edge of CLK IN or the falling edge of CLK OUT.
DRIVING THE ANALOG INPUT
During conversion, the AIN input current is modulated by
the DAC output current " a me equal to the CLK 1N frequency
(i.e., 2.5MH2 when CLK IN = 2.5MHZ). The analog input
voltage must remain fixed during this period and as a result
must be driven from an op amp or sample hold with a low
output impedance, The output impedance of an op amp is
equal to the open loop output impedance divided by the loop
gain at the frequency of interest.
Suitable devices capable of driving the AD7572 im input
are the AD OP-27 and AD7ll op amps or the AD585 sample
INTERNAL CLOCK OSCILLATOR
Figure 6 shows the AD7572 internal clock circuit. A crystal or
cenmic resonator may be connected between CLK IN (Pin t7)
and CLK OUT (Pin 18) to provide a clock oscillator for the
ADC timing. Alternatively the eryxtzllresomtor may be omitted
and an external clock source may be connected to CLK IN. For
an external clock the mark/space ratio must be 50/50. An inverted
CLK IN signal will appear at the CLK OUT pin as shown in
the operating waveform, of Figure 5.
CI I AD1572
CI r-a - moat
wnmxu - 33M"! CRYSTAL'CW RESONATOR.
MTSTZXX ll - mm CtttStetAMlCtteS0NAttht.
C100“: uvmmesuwunm 0N ClVSTAUC‘m “$0M“
MINU‘ACWIII. “ml. VALUES I"! "COME ttt T90p6.
Figure 6. A07572 Internal Clock Circuit
INTERNAL REFERENCE
The AD7S72 has an on-chip, buffered, tempentture-compensated,
buried Zener reference, which is factory trimmed to - 5.25V
1 1%. It is internally connected to the DAC and is also available
at Pin 2 to provide up to 550M current to an external load.
For minimum code transition noise the reference output should
be decoupled with a capacitor to filter out wideband noise from
the reference diode (lOuF of tantalum in parallel with 100nF
ceramic). However, large values of decoupling capacitor can
affect the dynamic response and stability of the reference stmplifier,
A 100 resistor in series with the decoupling capacitors will
eliminate this problem without edvueely affecting the filtering
effect of the capacitors. A simplified schematic of the reference
with its recommended decoupling components is shown in
Figure 7.
A0757:
comma to
- 1w IGND v...
01.; to
Figure 7. A07572 Internal - 5.25V Reference
REV. A
