AD7669JN ,LC2MOS Complete, 8-Bit Analog I/0 SystemsSpecifications apply to Mode 1 interface.MIN MAXAD75693J, A Versions AD7569AD7669 K, B AD7569 AD756 ..
AD7669JN ,LC2MOS Complete, 8-Bit Analog I/0 SystemsSpecifications apply to both DACs in the AD7669. V applies to both V A and V B of the AD7669.OUT OU ..
AD7669JP ,LC2MOS Complete, 8-Bit Analog I/0 Systemsspecifications apply for all output ranges including bipolar ranges with dual supply operation.3Tem ..
AD7669JR ,LC2MOS Complete, 8-Bit Analog I/0 SystemsFEATURES2 ms ADC with Track/Hold1 ms DAC with Output AmplifierAD7569, Single DAC OutputAD7669, Dual ..
AD766AN ,16-Bit DSP DACPORTSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*ORDERING GUIDEV to DGND . ..
AD766ANZ ,16-Bit Current-Steering DAC with Voltage ReferenceSPECIFICATIONS MSB trimming is used.)AD766J AD766AParameter Min Typ Max Min Typ Max UnitsRESOLUTION ..
ADL5370ACPZ-R7 , 300 MHz to 1000 MHz Quadrature Modulator
ADL5375-05ACPZ-R7 , 400 MHz to 6 GHz Broadband Quadrature Modulator
ADL5375-05ACPZ-R7 , 400 MHz to 6 GHz Broadband Quadrature Modulator
ADL5390ACPZ-REEL7 ,10MHz to 2.7GHz RF Vector MultiplierGENERAL DESCRIPTION ferential full-scale range centered about a 500 mV common The ADL5390 vector mu ..
ADL5500ACBZ-P2 , 100 MHz to 6 GHz TruPwr Detector
ADL5500ACBZ-P2 , 100 MHz to 6 GHz TruPwr Detector
AD7569AQ-AD7569BR-AD7569JN-AD7569JP-AD7569JR-AD7569KN-AD7569KP-AD7569SQ-AD7669AR-AD7669JN-AD7669JP-AD7669JR
LC2MOS Complete, 8-Bit Analog I/0 Systems
REV.B
LC2MOS
Complete, 8-Bit Analog I/0 Systems
FEATURES
2 ms ADC with Track/Hold
1 ms DAC with Output Amplifier
AD7569, Single DAC Output
AD7669, Dual DAC Output
On-Chip Bandgap Reference
Fast Bus Interface
Single or Dual 5 V Supplies
GENERAL DESCRIPTIONThe AD7569/AD7669 is a complete, 8-bit, analog I/O system
on a single monolithic chip. The AD7569 contains a high speed
successive approximation ADC with 2 μs conversion time, a track/
hold with 200 kHz bandwidth, a DAC and an output buffer ampli-
fier with 1 μs settling time. A temperature-compensated 1.25 V
bandgap reference provides a precision reference voltage for the
ADC and the DAC. The AD7669 is similar, but contains two
DACs with output buffer amplifiers.
A choice of analog input/output ranges is available. Using a sup-
ply voltage of +5 V, input and output ranges of zero to 1.25 V
and zero to 2.5 volts may be programmed using the RANGE in-
put pin. Using a ±5 V supply, bipolar ranges of ±1.25 V or
±2.5 V may be programmed.
Digital interfacing is via an 8-bit I/O port and standard micro-
processor control lines. Bus interface timing is extremely fast, al-
lowing easy connection to all popular 8-bit microprocessors. A
separate start convert line controls the track/hold and ADC to
give precise control of the sampling period.
The AD7569/AD7669 is fabricated in Linear-Compatible
CMOS (LC2MOS), an advanced, mixed technology process
combining precision bipolar circuits with low power CMOS
logic. The AD7569 is packaged in a 24-pin, 0.3" wide “skinny”
DIP, a 24-terminal SOIC and 28-terminal PLCC and LCCC
packages. The AD7669 is available in a 28-pin, 0.6" plastic
DIP, 28-terminal SOIC and 28-terminal PLCC package.
AD7569 FUNCTIONAL BLOCK DIAGRAM
AD7669 FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTSComplete Analog I/O on a Single Chip.
The AD7569/AD7669 provides everything necessary to
interface a microprocessor to the analog world. No external
components or user trims are required and the overall accu-
racy of the system is tightly specified, eliminating the need
to calculate error budgets from individual component
specifications.Dynamic Specifications for DSP Users.
In addition to the traditional ADC and DAC specifications,
the AD7569/AD7669 is specified for ac parameters, includ-
ing signal-to-noise ratio, distortion and input bandwidth.Fast Microprocessor Interface.
The AD7569/AD7669 has bus interface timing compatible
with all modern microprocessors, with bus access and relin-
quish times less than 75 ns and write pulse width less than
80 ns.
DAC SPECIFICATIONS1NOTESSpecifications apply to both DACs in the AD7669. VOUT applies to both VOUTA and VOUTB of the AD7669.Except where noted, specifications apply for all output ranges including bipolar ranges with dual supply operation.Temperature ranges as follows:J, K versions; 0°C to +70°C
A, B versions; –40°C to +85°C
S, T versions; –55°C to +125°C1 LSB = 4.88 mV for 0 V to +1.25 V output range, 9.76 mV for 0 V to +2.5 V and ±1.25 V ranges and 19.5 mV for ±2.5 V range.See Terminology.
AD7569/AD7669–SPECIFICATIONS
(VDD = +5 V 6 5%; VSS2 = RANGE = AGNDDAC = AGNDADC = DGND = 0 V; RL = 2 kV, CL = 100 pF to AGNDDAC
unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
ADC SPECIFICATIONSDYNAMIC PERFORMANCE
ANALOG INPUT
LOGIC INPUTS
CONVERSION TIME
NOTESExcept where noted, specifications apply for all ranges including bipolar ranges with dual supply operation.
2Temperature ranges are as follows:J, K versions; 0°C to +70°C
A, B versions; –40°C to +85°C
S, T versions; –55°C to +125°C
31 LSB = 4.88 mV for 0 V to +1.25 V range, 9.76 mV for 0 V to +2.5 V and ±1.25 V ranges and 19.5 mV for +2.5 V range.
4See Terminology.
5Includes internal voltage reference error and is calculated after offset error has been adjusted out. Ideal unipolar last code transition occurs at (FS – 3/2 LSB). Ideal bipolar last code transition occurs at
(FS/2 – 3/2 LSB).
6Exact frequencies are 101 kHz and 384 kHz to avoid harmonics coinciding with sampling frequency.
7Rising edge of BUSY to falling edge of ST. The time given refers to the acquisition time, which gives a 3 dB degradation in SNR from the tested figure.
8Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
(VDD = +5 V 6 5%; VSS1 = RANGE = AGNDDAC = AGNDDAC = DGND = 0 V; fCLK = 5 MHz external unless other-
wise noted. All specifications TMIN to TMAX unless otherwise noted.) Specifications apply to Mode 1 interface.
AD7569/AD7669
NOTE:
The term DAC (Digital-to-Analog Converter) throughout the
data sheet applies equally to the dual DACs in the AD7669 as
well as to the single DAC of the AD7569 unless otherwise
stated. It follows that the term VOUT applies to both VOUTA and
VOUTB of the AD7669 also.
TERMINOLOGY
Total Unadjusted ErrorTotal unadjusted error is a comprehensive specification that in-
cludes internal voltage reference error, relative accuracy, gain
and offset errors.
Relative Accuracy (DAC)Relative Accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after al-
lowing for offset and gain errors. For the bipolar output ranges,
the endpoints of the DAC transfer function are defined as those
voltages that correspond to negative full-scale and positive full-
scale codes. For the unipolar output ranges, the endpoints are
code 1 and code 255. Code 1 is chosen because the amplifier is
now working in single supply and, in cases where the true offset
of the amplifier is negative, it cannot be seen at code 0. If the
relative accuracy were calculated between code 0 and code 255,
the “negative offset” would appear as a linearity error. If the off-
set is negative and less than 1 LSB, it will appear at code 1, and
hence the true linearity of the converter is seen between code 1
and code 255.
Relative Accuracy (ADC)Relative Accuracy is the deviation of the ADC’s actual code
transition points from a straight line drawn between the end-
points of the ADC transfer function. For the bipolar input
ranges, these points are the measured, negative, full-scale transi-
tion point and the measured, positive, full-scale transition point.
For the unipolar ranges, the straight line is drawn between the
measured first LSB transition point and the measured full-scale
transition point.
Differential NonlinearityDifferential Nonlinearity is the difference between the measured
change and an ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max en-
sures monotonicity (DAC) or no missed codes (ADC). A differ-
ential nonlinearity of ±3/4 LSB max ensures that the minimum
step size (DAC) or code width (ADC) is 1/4 LSB, and the maxi-
mum step size or code width is 3/4 LSB.
Digital-to-Analog Glitch ImpulseDigital-to-Analog Glitch Impulse is the impulse injected into the
analog output when the digital inputs change state with the
DAC selected. It is normally specified as the area of the glitch in
nV secs and is measured when the digital input code is changed
by 1 LSB at the major carry transition.
Digital FeedthroughDigital Feedthrough is also a measure of the impulse injected to
the analog output from the digital inputs, but is measured when
the DAC is not selected. It is essentially feedthrough across the
die and package. It is also a measure of the glitch impulse trans-
ferred to the analog output when data is read from the internal
ADC. It is specified in nV secs and is measured with WR high
and a digital code change from all 0s to all 1s.
DAC-to-DAC Crosstalk (AD7669 Only)The glitch energy transferred to the output of one DAC due to
an update at the output of the second DAC. The figure given is
the worst case and is expressed in nV secs. It is measured with
an update voltage of full scale.
DAC-to-DAC Isolation (AD7669 Only)DAC-to-DAC Isolation is the proportion of a digitized sine
wave from the output of one DAC, which appears at the output
of the second DAC (loaded with all 1s). The figure given is the
worst case for the second DAC output and is expressed as a ra-
tio in dBs. It is measured with a digitized sine wave (fSAMPLING =
100 kHz) of 20 kHz at 2.5 V pk-pk.
Signal-to-Noise RatioSignal-to-Noise Ratio (SNR) is the measured signal to noise at
the output of the converter. The signal is the rms magnitude of
the fundamental. Noise is the rms sum of all the nonfundamen-
tal signals (excluding dc) up to half the sampling frequency.
SNR is dependent on the number of quantization levels used in
the digitization process; the more levels, the smaller the quanti-
zation noise. The theoretical SNR for a sine wave is given by
SNR = (6.02N + 1.76) dB
where N is the number of bits. Thus for an ideal 8-bit converter,
SNR = 50 dB.
Harmonic DistortionHarmonic Distortion is the ratio of the rms sum of harmonics to
the fundamental. For the AD7569/AD7669, Total Harmonic
Distortion (THD) is defined as log
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the individual
harmonics.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products, of order (m + n), at sum and difference frequencies of
mfa ± nfb where m, n = 0, l, 2, 3,… . Intermodulation terms
are those for which m or n is not equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb) and the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
AD7569/AD7669
ORDERING GUIDENOTESE = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = Small Outline SOIC.To order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact your local sales office for military data sheet.
AD7569 PIN CONFIGURATIONS
DIP, SOICPLCCLCCC
AD7669 PIN CONFIGURATIONS
DIP, SOIC
PLCC
PIN FUNCTION DESCRIPTION(Applies to the AD7569 and AD7669 unless otherwise stated.)
VOUT
VSS
RANGE
Table I.Input/Output Ranges
Noise Spectral Density vs. Frequency
Positive-Going Settling Time (±2.5 V Range)
DAC/ADC Full-Scale Temperature Coefficient
AD7569/AD7669—Typical Performance GraphsPower Supply Rejection Ratio vs. Frequency
Negative-Going Settling Time (±2.5 V Range)
IMD Plot for ADC
CIRCUIT DESCRIPTION
D/A SECTIONThe AD7569 contains an 8-bit, voltage-mode, D/A converter
that uses eight equally weighted current sources switched into
an R-2R ladder network to give a direct but unbuffered 0 V to
+1.25 V output range. The AD7669 is similar, but contains two
D/A converters. The current sources are fabricated using PNP
transistors. These transistors allow current sources that are
driven from positive voltage logic and give a zero-based output
range. The output voltage from the voltage switching R-2R lad-
der network has the same positive polarity as the reference;
therefore, the D/A converter can be operated from a single
power supply rail.
The PNP current sources are generated using the on-chip
bandgap reference and a control amplifier. The current sources
are switched to either the ladder or AGNDDAC by high speed
p-channel switches. These high-speed switches ensure a fast set-
tling time for the output voltage of the DAC. The R-2R ladder
network of the DAC consists of highly stable, thin-film resistors.
A simplified circuit diagram for the D/A converter section is
shown in Figure 3. An identical D/A converter is used as part of
the A/D converter, which is discussed later.
Figure 3.DAC Simplified Circuit Diagram
OP AMP SECTIONThe output from the D/A converter is buffered by a high speed,
noninverting op amp. This op amp is capable of developing2.5 V across a 2 kΩ and 100 pF load to AGNDDAC. The am-
plifier can be operated from a single +5 V supply to give two
unipolar output ranges, or from dual supplies (±5 V) to allow
two bipolar output ranges.
The feedback path of the amplifier contains a gain/offset net-
work that provides four voltage ranges at the output of the op
amp. The output voltage range is determined by the RANGE
and VSS inputs. (See Table I in the Pin Function Description
section.) The four possible output ranges are: 0 V to +1.25 V,
0 V to +2.5 V, ±1.25 V and ±2.5 V. It should be noted that
whichever range is selected for the output amplifier also applies
to the input voltage range of the A/D converter.
The output amplifier settles to within 1/2 LSB of its final value
in typically less than 500 ns. Operating the part from single or
dual supplies has no effect on the positive-going settling time.
However, the negative-going output settling time to voltages
supply, a transistor on the output acts as a passive pull-down
with output voltages near 0 V with VSS = 0 V. This means that
the sink capability of the amplifier is reduced as the output volt-
age nears 0 V in single supply. In dual supply operation the full
sink capability of 1.25 mA is maintained over the entire output
voltage range.
For all other parameters, the single and dual supply perfor-
mances of the amplifier are essentially identical. The output
noise from the amplifier, with full scale on the DAC, is 200 μV
peak-to-peak. The spot noise at 1 kHz is 35 nV/√Hz with all 0s
on the DAC. A noise spectral density versus frequency plot for
the amplifier is shown in the typical performance graphs.
VOLTAGE REFERENCEThe AD7569/AD7669 contains an on-chip bandgap reference
that provides a low noise, temperature compensated reference
voltage for both the DAC and the ADC. The reference is
trimmed for absolute accuracy and temperature coefficient. The
bandgap reference is generated with respect to VDD. It is buff-
ered by a separate control amplifier for both the DAC and the
ADC reference. This can be seen in the DAC ladder network
configuration in Figure 3.
DIGITAL SECTIONThe data pins on the AD7569/AD7669 provide a connection
between the external bus and DAC data inputs and ADC data
outputs. The threshold levels of all digital inputs and outputs
are compatible with either TTL or 5 V CMOS levels. Internal
input protection of all digital pins is achieved by on-chip distrib-
uted diodes.
The data format is straight binary when the part is used in single
supply (VSS = 0 V). However, when a VSS of –5 V is applied, the
data format becomes twos complement. This data format ap-
plies to the digital inputs of the DAC and the digital outputs of
the ADC.
ADC SECTIONThe analog-to-digital converter on the AD7569/AD7669 uses
the successive approximation technique to achieve a fast conver-
sion time of 2 μs and provides an 8-bit parallel digital output.
The reference for the ADC is provided by the on-chip bandgap
reference.
Conversion start is controlled by ST or by CS and RD. Once a
conversion has been started, another conversion start should not
be attempted until the conversion in progress is completed.
Exercising the RESET input does not affect conversion; the
RESET input resets the INT line high, which is useful in inter-
rupt driven systems where a READ has not been performed at
the end of the previous conversion. The INT line does not have
to be cleared at the end of conversion. The ADC will continue
to convert correctly, but the function of the INT line will be
affected.
Figure 4 shows the operating waveforms for a conversion cycle.
The analog input voltage, VIN, is held 50 ns typical after the fall-
ing edge of ST or (CS & RD). The MSB decision is made ap-
proximately 50 ns after the second falling edge of the input
CLK following a conversion start. If t1 in Figure 4 is greater
than 50 ns, then the falling edge of the input CLK will be seen
AD7569/AD7669
INTERNAL CLOCKClock pulses are generated by the action of an internal current
source charging the external capacitor (CCLK) and this external
capacitor discharging through the external resistor (RCLK).
When a conversion is complete, this internal clock stops operat-
ing and the CLK pin goes to the DGND potential. Connections
for RCLK and CCLK are shown in the operating diagram of Fig-
ure 21. The nominal conversion time versus temperature for the
recommended RCLK and CCLK combination is shown in Figure
6. The internal clock provides a convenient clock source for the
AD7569/AD7669. Due to process variations, the actual operat-
ing frequency for this RCLK/CCLK combination can vary from
device to device by up to ±25%.
Figure 6.Conversion Time vs. Temperature for Internal
Clock Operation
DIGITAL INTERFACE
DAC Timing and Control—AD7569Table II shows the truth table for DAC operation for the
AD7569. The part contains an 8-bit DAC register, which is
loaded from the data bus under control of CS and WR. The
data contained in the DAC register determines the analog out-
put from the DAC. The WR input is an edge-triggered input,
and data is transferred into the DAC register on the rising edge
of WR. Holding CS and WR low does not make the DAC regis-
ter transparent.
Table II. AD7569 DAC Truth TableL = Low State, H = High State, X = Don’t Care
The contents of the DAC register are reset to all 0s by an active
low pulse on the RESET line, and for the unipolar output ranges,
the output remains at 0 V after RESET returns high. For the bi-
polar output ranges, a low pulse on RESET causes the output to
At the end of conversion, the SAR contents are transferred to
the output latch, and the SAR is reset in readiness for a new
conversion. A single conversion lasts for 8 input clock cycles.
Figure 4.Operating Waveforms Using External Clock
ANALOG INPUTThe analog input of the AD7569/AD7669 feeds into an on-chip
track-and-hold amplifier. To accommodate different full-scale
ranges, the analog input signal is conditioned by a gain/offset
network that conditions all input ranges so the internal ADC al-
ways works with a 0 V to +1.25 V signal. As a result, the input
current on the VIN input varies with the input range selected as
shown in Figure 5.
Figure 5.Equivalent VIN Circuit
TRACK-AND-HOLDThe track-and-hold (T/H) amplifier on the analog input of the
AD7569/AD7669 allows the ADC to accurately convert an in-
put sine wave of 2.5 V peak-to-peak amplitude up to a fre-
quency of 200 kHz, the Nyquist frequency of the ADC when
operated at its maximum throughput rate of 400 kHz. This
maximum rate of conversion includes conversion time and time
between conversions. Because the input bandwidth of the T/H
amplifier is much larger than 200 kHz, the input signal should
be band-limited to avoid converting high-frequency noise
components.
The operation of this T/H amplifier is essentially transparent to
the user. The T/H amplifier goes from its tracking mode to its
hold mode at the start of conversion. This occurs when the
ADC receives a conversion start command from either ST or
CS & RD. At the end of conversion (BUSY going high), the
T/H reverts back to tracking the input signal.
EXTERNAL CLOCKThe AD7569/AD7669 ADC can be used with its on-chip clock
or with an externally applied clock. When using an external
clock, the CLK input of the AD7569/AD7669 may be driven
directly from 74HC, 4000B series buffers (such as 4049) or
from TTL buffers. When conversion is complete, the internal
