AD7568BP-AD7568BS Fast Delivery |IC PHOENIX CO.,LIMITED

AD7569AQ ,LC2MOS Complete, 8-Bit Analog I/0 Systemsspecifications,the AD7569/AD7669 is specified for ac parameters, includ-ing signal-to-noise ratio, ..
AD7569BR ,LC2MOS Complete, 8-Bit Analog I/0 SystemsSpecifications subject to change without notice.–2–REV. BAD7569/AD76691(V = +5 V 6 5%; V = RANGE = ..
AD7569JN ,LC2MOS Complete, 8-Bit Analog I/0 Systemsspecifications T to T unless otherwise noted.)MIN MAXAD75693J, A Versions AD7569AD7669 K, B AD7569 ..
AD7569JP ,LC2MOS Complete, 8-Bit Analog I/0 Systemsspecifications T to T unless otherwise noted.)MIN MAXAD75693J, A Versions AD7569AD7669 K, B AD7569 ..
AD7569JR ,LC2MOS Complete, 8-Bit Analog I/0 SystemsSpecifications apply to both DACs in the AD7669. V applies to both V A and V B of the AD7669.OUT OU ..
AD7569KN ,LC2MOS Complete, 8-Bit Analog I/0 SystemsSpecifications apply to Mode 1 interface.MIN MAXAD75693J, A Versions AD7569AD7669 K, B AD7569 AD756 ..
ADG732 ,32-Channel, Serially Controlled 3.5 Ohm 1.8 V to 5.5 V, ?.5 V, Analog MultiplexerCHARACTERISTICSt 34 ns typ R = 300 Ω , C = 35 pF; Test Circuit 5TRANSITION L L52 62 ns max V = 2 V/ ..
ADG732BSU ,16-/32- Channel, 3.5 з 1.8 V to 5.5 V, ?.5 V, Analog MultiplexersGENERAL DESCRIPTIONand have an input signal range which extends to the sup-The ADG726/ADG732 are mo ..
ADG732BSUZ , 16-/32-Channel, 4 1.8 V to 5.5 V, 2.5 V Analog Multiplexers
ADG732BSUZ , 16-/32-Channel, 4 1.8 V to 5.5 V, 2.5 V Analog Multiplexers
ADG733BRQ ,CMOS, 2.5 ohm Low Voltage, Triple/Quad SPDT SwitchesCHARACTERISTICSt 19 ns typ R = 300 Ω , C = 35 pF;ON L L34 ns max V = 3 V, Test Circuit 4St 7 ns typ ..
ADG733BRU ,CMOS, 2.5 ohm Low Voltage, Triple/Quad SPDT SwitchesSPECIFICATIONS B Version–40CParameter 25C to +85C Unit Test Conditions/Comments ANALOG SWITCH ..

AD7568BP-AD7568BS
LC2MOS Octal 12-Bit DAC
FUNCTIONAL BLOCK DIAGRAMLC2MOS
Octal 12-Bit DAC
FEATURES
Eight 12-Bit DACs in One Package
4-Quadrant Multiplication
Separate References
Single +5 V Supply
Low Power: 1 mW
Versatile Serial Interface
Simultaneous Update Capability
Reset Function
44-Pin PQFP and PLCC
APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation
PIN CONFIGURATIONS
Plastic Quad Flatpack
GENERAL DESCRIPTION
The AD7568 contains eight 12-bit DACs in one monolithic de-
vice. The DACs are standard current output with separate VREF,
IOUT1, IOUT2 and RFB terminals.
The AD7568 is a serial input device. Data is loaded using
FSIN, CLKIN and SDIN. One address pin, A0, sets up a de-
vice address, and this feature may be used to simplify device
loading in a multi-DAC environment.
All DACs can be simultaneously updated using the asynchro-
nous LDAC input and they can be cleared by asserting the
asynchronous CLR input.
The AD7568 is housed in a space-saving 44-pin plastic quad
flatpack and 44-lead PLCC.
REV.B
AD7568–SPECIFICATIONS1
ACCURACY
DIGITAL INPUTS
POWER REQUIREMENTS
AC PERFORMANCE CHARACTERISTICS
DYNAMIC PERFORMANCE
NOTESTemperature range as follows: B Version: –40°C to +85°C.
(VDD = +4.75 V to +5.25 V; IOUT1 = IOUT2 = O V; VREF = +5 V; TA = TMIN to TMAX,
unless otherwise noted)
(These characteristics are included for Design Guidance and are not subject
to test. DAC output op amp is AD843.)
TIMING SPECIFICATIONS
NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.t8 is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Figure 1.Timing Diagram
(VDD = +5 V 6 5%; IOUT1 = IOUT2 = 0 V; TA = TMIN to TMAX, unless otherwise noted)
1.6mAIOL
+2.1V
IOH200mA
50pF
TO OUTPUT
PIN
Figure 2.Load Circuit for Digital Output
Timing Specifications
ORDERING GUIDE
*S = Plastic Quad Flatpack (PQFP), P = Plastic Leaded Chip Carrier (PLCC).
AD7568
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
IOUT1 to DGND . . . . . . . . . . . . . . . . . . .–0.3 V to VDD +0.3 V
IOUT2 to DGND . . . . . . . . . . . . . . . . . . .–0.3 V to VDD +0.3 V
Digital Input Voltage to DGND . . . . . .–0.3 V to VDD +0.3 V
VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .±15 V
Input Current to Any Pin Except Supplies2 . . . . . . . .±10 mA
Operating Temperature Range
Commercial Plastic (B Versions) . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . . . .250 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . .10 mW/°C
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7568 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN DESCRIPTION
TERMINOLOGY
Relative Accuracy
Relative Accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error and is normally ex-
pressed in Least Significant Bits or as a percentage or full-scale
reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Gain Error
Gain Error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC after offset error has been adjusted out and is
expressed in Least Significant Bits. Gain error is adjustable to
zero with an external potentiometer.
Output Leakage Current
Output leakage current is current which flows in the DAC lad-
der switches when these are turned off. For the IOUT1 terminal,
it can be measured by loading all 0s to the DAC and measuring
the IOUT1 current. Minimum current will flow in the IOUT2 line
when the DAC is loaded with all 1s. This is a combination of
the switch leakage current and the ladder termination resistor
current. The IOUT2 leakage current is typically equal to that in
IOUT1.
Output Capacitance
This is the capacitance from the IOUT1 pin to AGND.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For the AD7568, it
is specified with the AD843 as the output op amp.
Digital to Analog Glitch Impulse
This is the amount of charge injected into the analog output
when the inputs change state. It is normally specified as the area
of the glitch in either pA-secs or nV-secs, depending upon
whether the glitch is measured as a current or voltage signal. It
is measured with the reference input connected to AGND and
the digital inputs toggled between all 1s and all 0s.
AC Feedthrough Error
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT terminal, when all 0s are
loaded in the DAC.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input which appears at the
output of any other DAC in the device and is expressed in dBs.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the Digital Crosstalk and is specified in nV-secs.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the de-
vice to show up as noise on the IOUT pin and subsequently on
the op amp output. This noise is digital feedthrough.
Table I.AD7568 Loading Sequence
Table II.DAC Selection
AD7568
Figure 3.Supply Current vs. Logic
Input Voltage
Figure 6.Integral Nonlinearity Error
vs. VREF
Figure 9.Digital-to-Analog Glitch
Impulse
–Typical Performance Curves
Figure 4.Supply Current vs.
Temperature
Figure 7.Typical DAC to DAC
Linearity Matching
Figure 10.Channel-to-Channel
Isolation (1 DAC to 1 DAC)

Partno	Mfg	Dc	Qty	Available	Descript
AD7568BP	AD	N/a	125	avai	LC2MOS Octal 12-Bit DAC
AD7568BS	AD	N/a	210	avai	LC2MOS Octal 12-Bit DAC