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ADG731BCP-REEL7 , 16-/32-Channel, Serially Controlled 4, 1.8 V to 5.5 V, 2.5 V, Analog Multiplexers
ADG731BSUZ , 16-/32-Channel, Serially Controlled 4, 1.8 V to 5.5 V, 2.5 V, Analog Multiplexers
ADG732 ,32-Channel, Serially Controlled 3.5 Ohm 1.8 V to 5.5 V, ?.5 V, Analog MultiplexerCHARACTERISTICSt 34 ns typ R = 300 Ω , C = 35 pF; Test Circuit 5TRANSITION L L52 62 ns max V = 2 V/ ..
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AD7564AR-B-AD7564ARS-B-AD7564BN-AD7564BR-AD7564BRS
LC2MOS +3.3 V/+5 V, Low Power, Quad 12-Bit DAC
a
FEATURES
Four 12-Bit DACs in One Package
4-Quadrant Multiplication
Separate References
Single Supply Operation
Guaranteed Specifications with +3.3 V/+5 V Supply
Low Power
Versatile Serial Interface
Simultaneous Update Capability
Reset Function
28-Pin SOIC, SSOP and DIP Packages
APPLICATIONS
Process Control
Portable Instrumentation
General Purpose Test Equipment
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS1. The AD7564 contains four 12-bit current output DACs with
separate VREF inputs.
2. The AD7564 can be operated from a single +3.3 V to +5 V
supply.
3. Simultaneous update capability and reset function are
available.
4. The AD7564 features a fast, versatile serial interface com-
patiblewithmodern 3 V and 5 V microprocessors and
microcomputers.Low power, 50 μW at 5 V and 33 μW at 3.3 V.
MOS
+3.3 V/+5 V, Low Power, Quad 12-Bit DACREV.A
GENERAL DESCRIPTIONThe AD7564 contains four 12-bit DACs in one monolithic
device. The DACs are standard current output with separate
VREF, IOUT1, IOUT2 and RFB terminals. These DACs operate from
a single +3.3 V to +5 V supply.
The AD7564 is a serial input device. Data is loaded using
FSIN, CLKIN and SDIN. Two address pins A0 and A1 set up
a device address, and this feature may be used to simplify device
loading in a multi-DAC environment. Alternatively, A0 and A1
can be ignored and the serial out capability used to configure a
daisy-chained system.
All DACs can be simultaneously updated using the asynchro-
nous LDAC input, and they can be cleared by asserting the
asynchronous CLR input.
The device is packaged in 28-pin SOIC, SSOP and DIP
packages.
NOTESTemperature range is as follows: B Version: –40°C to +85°C.Not production tested. Guaranteed by characterization at initial product release.
Specifications subject to change without notice.
Normal Mode
AD7564–SPECIFICATIONS
(VDD = +4.75 V to +5.25 V; IOUT1A to IOUT1D = IOUT2A = IOUT2D = AGND = 0 V; VREF = +10 V; TA = TMIN to TMAX,
unless otherwise noted)
NOTESThese specifications apply with the devices biased up at 1.23 V for single supply applications. The model numbering reflects this by means of a "-B" suffix
(for example: AD7564AR-B). Figure 19 is an example of Biased Mode Operation.Temperature ranges is as follows: A Version: –40°C to +85°C.Not production tested. Guaranteed by characterization at initial product release.
Specifications subject to change without notice.
Biased Mode1(VDD = +3 V to +5.5 V; VIOUT1 = VIOUT2 = 1.23 V; AGND = 0 V; VREF = 0 V to 2.45 V; TA = TMIN to
TMAX, unless otherwise noted)
AD7564
AD7564
(VDD = +3 V to +5.5 V; VIOUT1 = VIOUT2 = 1.23 V; AGND = 0 V. VREF = 1 kHz, 2.45 V p-p, sine wave biased at 1.23 V; DAC
output op amp is AD820; TA = TMIN to TMAX, unless otherwise noted. These characteristics are included for Design
Guidance and are not subject to test.)Biased Mode
AC Performance Characteristics
Normal Mode
(VDD = +4.75 V to +5.25 V; VIOUT1 = VIOUT2 = AGND = 0 V. VREF = 6 V rms, 1 kHz sine wave; DAC output op amp is
AD843; TA = TMIN to TMAX, unless otherwise noted. These characteristics are included for Design Guidance and are
not subject to test.)
AC Performance Characteristics
Timing Specifications1(TA = TMIN to TMAX unless otherwise noted)NOTESNot production tested. Guaranteed by characterization at initial product release. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed
from a voltage level of 1.6 V for a VDD of 5 V and from a voltage level 1.35 V for a VDD of 3.3 V.t8 is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with a VDD of 5 V and 0.6 V or 2.1 V for a VDD
of 3.3 V.
t 9
FSIN(I)
CLKIN(I)
SDIN(I)
SDOUT(O)
LDAC, CLRFigure 1.Timing Diagram
1.6mA
+1.6V
200µA
50pF
TO OUTPUT
PIN
IOL
IOHFigure 2.Load Circuit for Digital Output Timing Specifications
AD7564
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
IOUT1 to DGND . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
IOUT2 to DGND . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND . . . . . .–0.3 V to VDD + 0.3 V
VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . .±15 V
Input Current to Any Pin Except Supplies2 . . . . . . . .±10 mA
Operating Temperature Range
Commercial Plastic (A, B Versions). . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
DIP Package, Power Dissipation . . . . . . . . . . . . . . . . .875 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . .260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . .875 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . .260°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . .+220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . .900 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . .100°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
PIN CONFIGURATION
DIP, SOIC and SSOP Packages
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7564 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE*N = DIP; R = SOIC; RS = SSOP.
PIN DESCRIPTIONS
AD7564
Table II. DAC Selection
Output Voltage Settling TimeThis is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For the AD7564, it
is specified with the AD843 as the output op amp.
Digital to Analog Glitch ImpulseThis is the amount of charge injected into the analog output
when the inputs change state. It is normally specified as the
area of the glitch in either pA-secs or nV-secs, depending upon
whether the glitch is measured as a current or voltage signal. It
is measured with the reference input connected to AGND and
the digital inputs toggled between all 1s and all 0s.
AC Feedthrough ErrorThis is the error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT terminal, when all 0s are
loaded in the DAC.
Channel-to-Channel IsolationChannel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input which appears at the
output of any other DAC in the device and is expressed in dBs.
Digital CrosstalkThe glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the Digital Crosstalk and is specified in nV-secs.
Digital FeedthroughWhen the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the de-
vice to show up at on the IOUT pin and subsequently on the op
amp output. This noise is digital feedthrough.
TERMINOLOGY
Relative AccuracyRelativeaccuracy or endpoint linearity is a measure of the
maximum deviation froma straight line passing through the
endpoints oftheDACtransferfunction.Itismeasuredafter ad-
justing for zero error and full-scale error and is normally ex-
pressed in Least Significant Bits or as a percentage of full-scale
reading.
Differential NonlinearityDifferential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Gain ErrorGain error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s
in the DAC after offset error has been adjusted out and is ex-
pressed in Least Significant Bits. Gain error is adjustable to
zero with an external potentiometer.
Output Leakage CurrentOutputleakagecurrentiscurrentwhichflowsin the DAC
ladder switcheswhentheseareturned off. FortheIOUT1
terminal,it can be measured by loading all 0s to the DAC andmeasuredbyloadingall0stotheDACandmeasuringtheIOUT1
current. Minimum current will flow in the IOUT2 line when the
DAC is loaded with all 1s. This is a combination of the switch
leakage current and the ladder termination resistor current.
The IOUT2 leakage current is typically equal to that in IOUT1.
Output CapacitanceThis is the capacitance from the IOUT1 pin to AGND.
Table I.AD7564 Loading Sequence
DB15DB0
