AD7549JN ,LC2MOS DUAL 12-BIT uP-COMPATIBLE DACCHARACTERISTICS‘ (%=+15ll,hm=hm= HM: hm: mun =lhl,uttkrssgthtmrisastatmi)
Limit at
TA = - 55°C
..
AD7549JP ,LC2MOS DUAL 12-BIT uP-COMPATIBLE DACGENERAL DESCRIPTION
The AD7549 is a monolithic dual, 12-bit, current output D/A
converter. It i ..
AD7549KN ,LC2MOS DUAL 12-BIT uP-COMPATIBLE DACSPECIFICATIONS'
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
..
AD7549KN ,LC2MOS DUAL 12-BIT uP-COMPATIBLE DACCHARACTERISTICS
(v.., = +158 =5%2,vm = hm, = IW; Imm = lam = AGND = IN.
All sptmificatiorts T,, ..
AD7549KP ,LC2MOS DUAL 12-BIT uP-COMPATIBLE DACAPPLICATIONS _, l I
-
Programmable Filters
Vnn
AutomatieTestEquipment
-
Microcomputer ..
AD7564AR-B ,LC2MOS +3.3 V/+5 V, Low Power, Quad 12-Bit DACSpecifications with +3.3 V/+5 V Supply 1212 DAC ALATCH A LATCHI AOUT2Low PowerR BFBVersat ..
ADG719BRTZ-REEL , CMOS 1.8 V to 5.5 V, 2.5 Ω 2:1 Mux/SPDT Switch in SOT-23
ADG721BRM ,CMOS Low Voltage 4 ohm Dual SPST Switchesspecifications –408C to +858C, unless otherwise noted.)DD B Version–408C toParameter +258C ..
ADG721BRM-REEL7 , CMOS, Low Voltage, 4 Ω Dual SPST Switches in 3 mm × 2 mm LFCSP
ADG721BRMZ-REEL , CMOS, Low Voltage, 4 Ω Dual SPST Switches in 3 mm × 2 mm LFCSP
ADG722ACPZ-REEL , CMOS, Low Voltage, 4 Ω Dual SPST Switches in 3 mm × 2 mm LFCSP
ADG722BRM ,CMOS Low Voltage 4 ohm Dual SPST SwitchesGENERAL DESCRIPTION1. +1.8 V to +5.5 V Single Supply Operation. The ADG721,The ADG721, ADG722 and A ..
AD7549AQ-AD7549BQ-AD7549JN-AD7549JP-AD7549KN-AD7549KP
LC2MOS DUAL 12-BIT uP-COMPATIBLE DAC
ANALOG
DEVICES
Dual 12-Bit ptP-Compatihle Mil
FEATURES
Two Doubled Buffered 12-Bit DACs
4-Ouadrant Multiplication
Low Gain Error (3LSBs max)
DAC Ladder Resistance Matching: 1%
Space Saving Skinny DIP and Surface Mount Packages
Latch-Up Proof
Extended Temperature Range Operation
APPLICATIONS
Programmable Filters
Automatic Test Equipment
Microcomputer Based Process Control
Audio Systems
Programmable Power Supplies
Synchro Applications
GENERAL DESCRIPTION
The AD7549 is a monolithic dual, 12-bit, current output D/A
converter. It is packaged in both 0.3" wide 20-pin DIPs and in
20-terminal surface mount packages. Both DACs provide four
quadrant multiplication capabilities with a separate reference
input and feedback resistor for each DAC. The monolithic
construction ensures excellent thermal tracking and gain error
tracking between the two DACs.
The DACs in the AD7549 are each loaded in three 4-bit
nibbles. The control logic is designed for easy processor interfacing.
Input and DAC register loading is accomplished using address
lines A0, A1, A2 and cg, W lines. A logic high level on the
CLR input clears all registers. Both DACs may be simultaneously
updated using the UPD input.
The AD7S49 is manufactured using the Linear Compatible
CMOS(LCZMOS) process. It is speed compatible with most
microprocessors and accepts TTL, 74HC or 5V CMOS logic
level inputs.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
DAtt A REGISTER
CONTROL
DAC B REGIS ER
DB3-DB0 DGND
PRODUCT HIGHLIGHTS
1. Small package size: the loading structure adopted for the
AD7549 enables two 12-Bit DACs to be packaged in either a
small 20-pin 0.3" DIP or in 20-terminal surface mount
packages.
2. DAC to DAC matching: since both DACs are fabricated on
the same chip, precise matching and tracking is inherent.
This opens up applications which otherwise would not be
considered, i.e., Programmable Filters, Audio Systems, etc.
One Technology Way, PO. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703 wa: 710/394-6577
Telex: 924491 Cable: ANALOG NORWOODMASS
M754il-rSPEtyFlt
1 (Von = +15Y 15962,an = hm = "N: lam = loum = ASH” = IN.
All sptseifieatitms Tmtn u, unless thherttise specifkd.)
ATIONS
I , A K,
Parameter Versions Versions S Version T Version Units Test Conditions/Commcnts
ACCURACY
Resolution 12 12 12 12 Bits
Relative Accuracy 1 t 1/2 t 1 t 1/2 LSB max
Differential Nuniinearity - 1 z 1 t 1 t I LSB max All grades guaranteed monotonic over
temperature.
Full Scale Error I 6 t 3 + 6 t 3 LSB max Measured using internal Itro and includes
effects of leakage current and gain TC.
Gain Temperature Ctmfricieat3;
AGain/hTemperature - S 1 S - 5 t S ppm/'C max Typical value is lppmPC
Output Leakage Current
Iom'A (Pin l7)
' 25°C 20 20 20 20 nA max DAC A Register loaded withall 0's
TUnto Tn,“ 150 150 250 250 Mm
Iovm (Pin 1 5)
+ 25°C 20 20 20 20 nA max DAC B Register loaded with all 0's
Tm to Tmax 150 150 250 250 nA max
REFERENCE INPUT
Input Resistance (Pin 19, Pin 13) 7 7 7 7 k0 min Typical Input Resistance = 1 1kfl
18 18 18 18 kn max
anFA/VIu-zrn
Input Resistance Match ue 3 + 2 t 3 - 2 % mu Typically , 1%
DIGITAL INPUTS
Vm (Input High voltage) 2.4 2.4 2 4 2.4 V min
Vndinput Low Voltage) 0.8 0.8 0 g 0.8 V max
1m (Input Current)
+25°C l tl tl 1 Mmax VIN:VDD
Tuxon + 10 , 10 t 10 ' 10 wArnax
Cm (Input Cupaciunceys 7 7 7 pF mu
POWER SUPPLY
loo 5 5 5 5 mA max
ht PERFORMANCE CHARACTERISTICS
These Charatdstits an included for Design Guidance only and are not subject to test
(Vm = +1511; hm = hm, = +IW, lam = G = A8111] = w, Output llmplifiersamlilB44 except where stated.)
Parameter TA " + 25NI TA = Tm, Tm Unit: Test CqrtditioetB/Ctmtmetit8
outpstCurzmstlieatiagTime 1.5 - puma: T00.01% offuliesnge.1ovTload= 100.0;Cm = 13pF.DACoutputmeasusedmrm
filling edge ofWR. Typical valucofScnling Time is ihhss.
DigiuI-to-AmlogGlixch Measured with Wsar, = Vars = (N. Iorrra, 10011 load = 1000, Can- = 13pF.
Impulse 10 - nV-sec typ DAC registers alternately loaded with all 0's and Ell Ps.
AC Feedthrough'
VIE“ to Iou-n - 70 - 65 dBmu Furs, Vsuum = 20V p-p lOkHz sine wm.
'urs to loan - 70 - 65 dB mu DAC registers loaded with all Os.
PmSupply Rejection
AGIin/AVDD :0.01 10.02 %per%rnax Avon = :5%
Output Capacitance
Comm " 80 pF max DAC A, DAC B loaded with all "
com 80 80 pF max
COUTA 160 160 pFmax DACA,DACBloodedwithail1'g.
Com 160 160 mex
t2unneGtsAhartnel Isolation
VIEFA to 10m - 62 - dB typ Frasra = 20V iFP 100kHz sine wave, bum, = 0V
ng lo loun _ 62 - dB typ Vnm ' 20V p-p 100kHi sinewave, ber, = 0V
Digital Crosstalk 10 - nV-sec typ Measured for It Cod: Transition ofall 0's tttall 1's
Output Noise Voltage Density
(ttMr-Mmm) 15 - rtVNHztyp MeasurmibexseemtRmAantHourA or Rngandlom
HanntmicDistortian -90 - dBlyp 1%--6Vrms lkHz
'T-tttree-Mimi-u: “In ORS‘C
A,B.Vuuo¢u: -40'Cttt +IS'C
S,T,Va'liuu: -55'Csrt +125‘C
xAIV "5v,tttee_hWhmrtimtal%thtireiexit-fm-.
a2'fliih'/r"r'i2%"i'i%2 .
'Fsttttm-ntretuettterr-xdtsrc-timtt-uititaos-ticr-etuDGND,
'peeitarit-1tsiex:tu"h-ithoutmxim.
REV. A
AD7549
TIMING CHARACTERISTICS‘ am am”. = hm= “M. = latm= mun .---ml,uttkrssthhettdstrstated)
Limit at Limit at
Limit at TA = - 40''C TA = - 55°C
Parameter = 25NI to + 85''C to + 125°C Units Test Conditions/Comments
tt 50 80 110 ns min Address Valid to Write Setup Time
t2 0 0 0 ns min Address Valid to Write Hold Time
ts 180 200 240 ns min Data Setup Time
t4 0 0 0 ns min Data Hold Time
ts 20 20 20 ns min Chip Select or Update to Write Setup Time
tg 0 0 0 ns min Chip Select or Update to Write Hold Time
ty 170 200 250 ns min Write Pulse Width
Is 170 200 250 nsmin Clear Pulse Width
Specirtattions subject to change without notice.
F u _ SV
cut ' ov
1. " INPUT SIGNAL ms: AND FALL TIMES MEASURED FROM 10% TO
30% or +5v. n=n=20ns.
2. TIMING MEASUREMENT REFERENCE LEVEL IS -''gt-'-k
ABSOLUTE MAXIMUM RATINGS'
(TA = + 25°C unless otherwise noted) Operating Temperature Range
Vor, (Pin 20) to DGND ............. -0.3V, + 17V . .
vam, vm (Pins 19, 13) to AGND ......... t25V Industrial (A, B Versions)
VRFBA) VRFBB (Pins 18, 14) t0 AGND ......... t25V
Digital Input Voltage (Pins l-l I)
to DGND ...............
VPINIS: men, to DGND ........
AGND to DGND ............
Power Dissipation (Any Package)
To + 75°C
Derates above + 75°C .........
CAUTION
....... 6mW/°C
-0.3V, Vor, +0.3V
-0.3V, Voo +0.3V
-0.3V, VDD +0.3V
- 40°C to + 85°C
- 40°C to + 85°C
Extended (S, T Versions) ......... - 55°C to +125°C
............ - 65°C to + 150°C
+ 300°C
*Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied, Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Commercial (J, K Versions)
Storage Temperature
Lead Temperature (Soldering, 10secs)
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect-
ed; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be 'stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
el!siiili!ii'iiiiii--il-illi!ll
REV. A
AD7549
ORDERIN G GUIDE
Temperature Relative Full Scale Package
Model1 Range Accuracy Error Option2
AD7549JN - 40°C to + 85°C t lLSB t 6LSB N-20
AD7549KN - 40°C to + 85°C t l/2LSB t BLSB N-20
AD7549IP - 40°C to + 85°C I lLSB t 6LSB P-20A
AD7549KP - 40°C to + 85°C , 1/2LSB t 3LSB P-20A
AD7549AQ - 40°C to + 85°C t lLSB t 6LSB Q-20
AD7549BQ - 40°C to + 85''C t 1/2LSB t 3LSB Q-20
AD7549SQ - 55°C to + 125°C : ILSB i 6LSB Q-20
AD7549TQ - 55°C to + 125°C t 1/2LSB t SLSB Q-20
AD7549SE - 55°C to + 125°C : lLSB t 6LSB E-NA
AD7549TE - 55°C to + 125°C t 1/2LSB A SLSB E-ZOA
m, order MIL-STD-883, Class B process parts, add /883B to part number. Contact your
local sales office for military data sheet.
2E = Ludless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier;
Q = Cerdip.
TERMINOLOGY
RELATIVE ACCURACY
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full scale error and is normally
expressed in Least Significant Bits or as a percentage of full
scale reading.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the difference between the measured
change and the ideal lLSB change between any two adjacent
codes. A specir1ed differential nonlinearity of lLSB max over
the operating temperature range ensures montonicity.
FULL-SCALE ERROR
Full scale error or gain error is a measure of the output error
between an ideal DAC and the actual device output. Full scale
error is adjustable to zero.
OUTPUT CAPACITANCE
This is the capacitance from IOUTA or loam, to AGND.
DIGITAL-TO-ANALOG GLITCH IMPULSE
The amount of charge injected into the analog output when the
inputs change state is called Digital-to-Analog Glitch Impulse.
This is normally specified as the area of the glitch in either pA-
secs or nV-secs depending upon whether the glitch is measured
as a current or voltage signal. Digital charge injection is measured
with VREFA and VREFB equal to AGND.
OUTPUT LEAKAGE CURRENT
Output Leakage Current is current which appears at 1001A or
Iowa with the DAC registers loaded to all zeros.
MULTIPLYING FEEDTHROUGH ERROR
This is the error due to capacitive feedthrough from VREFA to
IOUTA or bum, to 10m with the DAC registers loaded to all
zeros.
CHANNEL-TO-CHANNEL ISOLATION
Channel-to-Channel Isolation refers to the proportion of input
signal from one DAC's reference input which appears at the
output of the other DAC, expressed as a ratio in dB.
DIGITAL CROSSTALK
The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as Digital Crosstalk and is specified in nV-secs.
PIN CONFIGURATIONS
DIP LCCC PLCC
V a N E a
v: E n S I
(usaiossio Els r,,,,,'-,,,,,,,, Dno>>
WE Ev”. 'liititii1,' aanam
3 2 1 20 "
DBI E E am u m
DBlt “nu
DBtt E E kmra , Dan 4 " Rm um F k,
uio E AD7549 E AGND W 5 " um. AD7549 ”"
TOP VIEW AD7549 A2 TOP mew " AGND
" E iNotto ScMerl E Gum A2 6 TOPVIEW " AGND (Mono scam
-tv, 7 (NottoSule) 15 ksu At E IOIHI
A1 , " Km n An m am
" E E Veer. An tt " Ros
63 E E DGND
- 9 10 " " "
wt 10 11 cut
E 1't'a'l''r'ta,i,l,:5 lass“
a ' a >
-4- REV.A
AD7549
\DWNO‘M-hWNr—I
REV. A
FUNCTION DESCRIPTION
DB3 Data Bit 3, Data Bit 7 or Data Bit 11 (MSB)
DB2 Data Bit 2, Data Bit 6 or Data Bit 10.
DBI Data Bit 1, Data Bit 5 or Data Bit 9.
DB0 Data Bit 0, Data Bit 4 or Data Bit 8.
W Updates DAC Registers from 4-bit input registers. DAC A and DAC B both updated simultaneously.
A2 Address line 2 .
AI Address line 1 .
A0 Address line 0.
a Chip Select Input. Active low.
W Write Input. Active low.
CLR Clear Input. Active High. Clears all registers.
DGND Digital Ground.
VREFB Voltage reference input to DAC B.
Rpm; F eedback resistor of DAC B.
[om Current output terminal of DAC B.
AGND Analog ground.
Ioum Current output terminal of DAC A.
Rpm Feedback resistor of DAC A.
V33“ Voltage reference input to DAC A.
Vor, + 15V supply input.
CLR U155 CS RE A2 A1 A0 FUNCTION
0 X X l X x X No data transfer.
0 l 1 X x X x No data transfer.
1 X X X x x X All registers cleared.
0 I 0 Tr 0 0 0 DAC A LOW NIBBLE REGISTER
loaded from Data Bus.
0 l 0 Tr 0 0 l DAC A MID N IBBLE REGI STER
loaded from Data Bus.
0 l 0 Tr 0 l 0 DAC A HIGH NIBBLE REGISTER
loaded from Data Bus. _
0 1 0 U 0 l l DAC A Register loaded from
Input Registers.
0 l 0 U l 0 0 DAC B LOW NIBBLE REGISTER loaded
from Data Bus.
0 l o Tr l 0 l DAC B MID NIBBLE REGISTER loaded
from Data Bus.
0 l 0 Tr 1 l 0 DAC B HIGH NIBBLE REGISTER loaded
from Data Bus.
0 l 0 Tr 1 1 1 DAC B Register loaded from
Input Registers.
0 0 1 -u- X X x DAC A, DAC B Registers updated
simultaneously from Input Registers.
NOTE: X = Don'tCare
Table L AD7549 Truth Table
