AD7548KP ,LC2MOS 8-BIT uP COMPATIBLE 12-BIT DACFEATURES
Mi! Bus Compatible 12-Bit DAG
" Grade: 12-Blt Monotonie Over Full
Temperetuto Range ..
AD7548TQ ,LC2MOS 8-BIT uP COMPATIBLE 12-BIT DACSpecifications gmmmnd om this range
u, 3 All digital input: " or vu,
1 All digial inputs 0V or Vo ..
AD7549AQ ,LC2MOS DUAL 12-BIT uP-COMPATIBLE DACCHARACTERISTICS
(v.., = +158 =5%2,vm = hm, = IW; Imm = lam = AGND = IN.
All sptmificatiorts T,, ..
AD7549AQ ,LC2MOS DUAL 12-BIT uP-COMPATIBLE DACFEATURES F UNCTIONAL BLOCK DIAGRAM
Two Doubled Buffered 12-Bit DACs
4-Ouadrant Multiplication
..
AD7549BQ ,LC2MOS DUAL 12-BIT uP-COMPATIBLE DACGENERAL DESCRIPTION
The AD7549 is a monolithic dual, 12-bit, current output D/A
converter. It i ..
AD7549JN ,LC2MOS DUAL 12-BIT uP-COMPATIBLE DACCHARACTERISTICS‘ (%=+15ll,hm=hm= HM: hm: mun =lhl,uttkrssgthtmrisastatmi)
Limit at
TA = - 55°C
..
ADG719BRT ,CMOS Low Voltage 4 ohm SPDT SwitchCHARACTERISTICSt 14 ns typ R = 300 W , C = 35 pFON L L20 ns max V = 3 V, Test Circuit 4St 3 ns typ ..
ADG719BRT-500RL7 , CMOS 1.8 V to 5.5 V, 2.5 Ω 2:1 Mux/SPDT Switch in SOT-23
ADG719BRT-REEL , CMOS 1.8 V to 5.5 V, 2.5 Ω 2:1 Mux/SPDT Switch in SOT-23
ADG719BRTZ-500RL7 , CMOS 1.8 V to 5.5 V, 2.5 Ω 2:1 Mux/SPDT Switch in SOT-23
ADG719BRTZ-REEL , CMOS 1.8 V to 5.5 V, 2.5 Ω 2:1 Mux/SPDT Switch in SOT-23
ADG721BRM ,CMOS Low Voltage 4 ohm Dual SPST Switchesspecifications –408C to +858C, unless otherwise noted.)DD B Version–408C toParameter +258C ..
AD7548AQ-AD7548BQ-AD7548JN-AD7548JR-AD7548KN-AD7548KP-AD7548TQ
LC2MOS 8-BIT uP COMPATIBLE 12-BIT DAC
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ANALOG
DEVICES
L02 M08
8-Bit " Compatible 12-Bit DAB
AD7548
FEATURES
B-Blt Bus Compatible 1bBit DAC
All Grade: 12-Blt Monotonlc Over Full
Temperature Range:
Operation Speeifierd at +5v. +12v
at + tW Power Suppty
Low Gain Dtift of SppmPC Maximum
Full 4 Ouldnnt MuttipWation
Skinny DIP and Surface Mount Packages
APPuCATNm8
a-an Microproceum Based Control Systems
Programmable Ampt'dkrrs
Function Generation
Servo Control
GENERAL DESCRIPTION
The AD7S48 it a 12-bit monolithic CMOS D/A converter for
use with S-bit bus microprocessors. Data is loaded in two bytes
to input holding registers " shown in the block diagram opposite.
The AD7548 can be configured to accept either left- or right-ius-
tified data, least significant byte or most significant byte first,
using standard TTI. compatible control inputs.
A separate load DAC control input allows the user the choice of
updating the analog output coincident with loading new data to
the DAC input register or at any time after the data loading
event. This feature is especially important in multi-DAC systems
where simultaneous update of all DACs is required.
The new Linear Compatible CMOS (LC’MOS) process used in
the manufacture of the AD7S48 allows precision thitMilm linear
circuitry and high-speed low-power CMOS logic to be integrated
on the same small chip. The high-speed logic allows direct
interfacing to most of the popular Sobit microprocessors.
REV, A
Information furniehad by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents Or other rights of third parties
which may resun from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
AD7548
BIRLIDDER
t)AYA ovum»:
MC “GIST“
NWT ”CB!“
,'ith -
"7-930
PRODUCT HIGHLIGHTS
1. Microprocessor Compatibility
High speed input control (TTL/SV CMOS compatible)
allow direct interfacing to mod of the popular S-hit
microprocessors.
2. Guaranteed Monotonicity
The AD7S48 is guaranteed monotonic to 12-bits over the full
temperature range for all grades and " all specified supply
voltages.
3. Selectable Data Input Format
Left- or right-justified data, least significant or most significant
byte first, This allows the AD7548 to be interfaced with
microprocessors using either Motorola or Intcl-typc data
formatting.
4. Monolithic Construction
For increased reliability and reduced package size - 0.3"
20-pin DIP and 20-terminal surface mount packages.
5. Single Supply Operation - See Figure 8,
6. Low Gain Error and Gain Error T.C.
One Technology Way, PD. Box 9106, Norwood, MA 02062-9105. USA.
Tel: 517/3294700 Fax: 617/326-8703 wa: 710/3365”
Telex: 924431 Cable: ANALOG NORWOODMASS
nl‘nIJI-"J HDV IUD“ I' "" UII UIJI'II'IIIIJ IILllI-l ll!”
M7M8--SPEtlFlMrMG
I (ya = +till, her = +10V; G, = u, = tl1l.hllsImifitatitms ts,, tn u,
unless otherwise specified)
LA R,B
Pt-trr Vmiou Vcniou SVuaiot TWtsion U159 Ten Wanna
AGIURACY
ngsduu'on 12 12 12 12 Bits
Rdnivckcum 21 :1/2 :1 .2112 LSBrnax
DitktentisiNottiinearitr t 1 g 1/2 tl 2 1/2 1.83 mu All graksguarstteed monomnic 1012-b1u
m tmpcmurc.
Ftdiscaleihttr =.6 :3 a6 .x3 1.881111: mmmmmknmmm‘n
drectsof1e9ctazesondgaittTC.
F1111 Sale Ewan be tanned mum.
Fain Tmpaanm m9;
AGdn/ATcmpcnmn " :5 :5 :5 Wm Tyrirai"hseu2ptmt'c
0utprtutMgeCttrretst
1ouriPin "
+25"C es as , ' Man AlldWtalittpta-0V
T-tttT.., :25 :25 .150 150 Mm
REFERENCE INPUT
taptt Munoz, Pin19 7 7 7 7 m min Typical 1nput Raimnce " 11m
20 20 20 20 m an:
D1Gn'AL1NPUTS
1t0atnrtHigttvttltsge) 2,4 14 2.4 2.4 Vmin
vmttrsputLm1loltme) 0.11 " " " Van:
im "tiptttCitrrerst)
+251: xt xl xl 1 11AM VmeorVnp
Tum“ tio :10 - 10 :10 Mm
tattsqnstcstmeittrteer' 7 7 7 pF mu
POVERSUPPLY
Von Range £755.25 £755.15 1.75/51: {7515.15 VminN max $pei6otiorts guumlced over this nus:
[pp l 1 2 2 Man: Atidigitalinptrts VIL oth
300 300 300 300 Mm Alldiginl iaputttNorvrx,
SPECIFICATIONS‘ wmmmmm
J, A K, tt
Inmate: Vcniou Verdun: SVmion TVcnion Uniu TestCooditiostsmo-ts
MIIURACY
Million 12 12 12 12 Ms
Rduichccuncy tl :1/2 sl :1/2 LSBmu
Differential Nemlittearity x l , m 2 1 r. 1/2 LSB max Allmde: gummeed monotonic to 11-bit:
ova: 1cmpcmu1-c.
FttilstaleEgrw :6 t3 t..6 :3 LSBmu MeatttredttsingintmulRnstttditttNdes
etrectsofkakagecurrent and gain TC
Fu0taietihertxnbeuitnrrtedtomto.
GainTatqsemttue ctsemcieaF,
AGIin/ATcmxxI-um : , L5 s. ' x5 pprnt'C ma: Typical "hte is prmf’C
Output mm:
iourtPin "
1 ZS'C as :5 f. :5 nAmu Altdigittlinpute0V
T-tor.., t25 .025 use 2150 MM
REFERENCE INPUT
1ttputReei-rPirt 19 7 7 7 7 mm TrpioHrtputResisance=11ut
20 20 20 20 ktt mu
DIGITALINPUTS
Vm (Input High Voltage) 2.4 2.4 2.4 2.4 Vrnin
Ilrc (Input Laonluu) " " 0.8, 0.8 V mu
tm (lnpulCIn’mi)
+251: ti tl al tl Mm Vm=0voann
Tulon tit) :10 ,..10 - 10 Man:
Cm (1an Clpdunce)’ t , 7 pF mu
POWER SUPPLY
Vpglunn 11.015.75 111115.75 11.614515 11.01175 Vmin/me Spedtiotitmsemnrestrwer 'ttisrange
Itrrs 3 3 3 3 nth um All digital input: " or vu,
1 l 1 t MM Alldigialinpua0vrorvur,
'Te-tttrem-rio-ers-r. -arr.m HST:
AJVerir-uz -‘0’CM+IS'C
S,TVertinttr. OSYCID ' IN'C
quwmzmmmm.
hxx'6osisms mbicuochnxnhhnx coda.
REV. A
AD'IS4B
mama cummmsncs' ihr= +51%: +tthlAm,-=%t=tmmtsssehtmitttstatM)
Limit’u unit’m
Limita: Tara -41rc TA- - SS'C
Parameter TA: 25'C to + 851: to + 125'C Unite Teat Conditions/Comments
Ins 240 240 290 ns min Darn Valid Setup Tim;
hm 50 50 70 ns min Data Valid Hold Time,
tdws 30 40 so nsmin CSM§B orCSLSB xoW_RSerup Time
tam 15 20 25 ns min CSMSB aggLSB to WR Hold Time
tt.ws 30 40 so ns min LDAE to Le. Setup Time
um, 15 20 25 nsmin 1CtfMtoWiHoyi Time
In 250 280 320 ns min Write Pulse Width
TIMING tagtttmtgmtsl th," +12th +15tyesrr-- '1W,%n=%z=WtirtassthtmdarstztM)
Limitht Limit2at
Umiut TAB -40'C TA: -55'C
Puma: T. w. 29C tn + 89C to + 1290 Units Test Conditions/Comments
(m 160 190 230 ns min Data Valid SetupTime
tDH 30 30 M) na min Data Valid Hold Time
ms 30 40 $0 nsmin Wet CSLSB toWSctup Time
m IS 20 25 nsmin t%Bfiortrsmtorrti"Hoid Time
trars 30 40 50 ns min LDAC to Tmt" Setup Time
thn 15 20 25 nsmin ir6hThoiWHo1d Time
In 170 200 240 ns min Write Pulse Width
M fEltRWMli0E CHARACTERISTICS
1hestrtttamtttristitsamitttludaHtrhsigrGiidartaumtrattdanrnotsthiertttuest
“w: +10% G=Gt=thl,thmtumplifierisM5M Bmmmw
vms+5v vm-nszHsv
mm Vain. Ta" +2$'C T; = Tmm,TaeAx TA. + IST TR =Tm,rm Units Tet: CottdititmstGtrtmeats
otrtrnthuretttSeutittgTitrte Ls - I - usury Toth0t%oftirl_nge.
lore 10.1 = 1m,CaT- UPF.
DAC reistcraltertutety
_lgMaLtrjtluiLltap4Illllc-,-
Digital 10 Annie; Glitch Measured with 'u, = 0V,
1mm 400 - 330 nV-sccxyp 10mm " 1001mm -13pF,
DAC register alternately
loaded with I" la and mo;
Mulu'plyin; Fccdduouh Enor’ 3 S 3 , mV p-p typ Vm = t SV, lokHz sinevnvc
DAC register lmded withall0s.
Total Harmonic Distortion - " - - 85 - dB typ me- 6V an: Ca thHi,
DAC register loaded with all Is.
Pow Supply Rejection
AGAINIA V99 20.015 , 0.03 30.0] 10.02 %per%ittax AVnD- :5%
Output Clpldnncc
lana’in " 200 200 200 2(1) pF max DAC rcgistcr lauded with all ls.
100 an loo 100 pF mu DAC register loaded with .1103.
Output Noise Voluxc Density
(tim-Noi) H - 15 - nVNl-Iz ryp Measured between Rrwatdiovr
ltkar-dhrai-stttt-datai-d.
‘me-MIJVM ~40'Cwu5'c
A,IV¢iem: 40'an HS'C
S.Tthaa: “5512-0 ' WT
'r-ear-tsehr-xo-emi-r-ttisa-is-pe-crm.
'0ees'tkaebmoe"seMr-itttmnettst'trr.
REV. A
nl‘nhuu UDV I Lino r "A - UI‘ A unrlnllu nu ' La l "Eu a
ABSOLUTE MAXIMUM RATINGS‘ Operating Temperature Range
(TU " ' 2S'Cualessothetwisenoted) Commercinl (J, K versions) ......... ~40 to +85°C
vm, (pin It) to DGND ................. + 17V Industrial (h, B versions) ......... -40'C to +89'C
VREF (pin 19) to AGND ................ ' 25V Extended (S, T versions) ......... - 55'C to +125°C
Wm (pin 20) m AGND ................ t 25V Storage Temperature ------------ -65'C to + 150'C
Digital Input Voltage Lad Temperature (Soldering, 10secs) ........ + 300°C
(pins 4-17) to DGND ......... -0.3V, VDD+0.3V Sm m those listed m AM t mm mm m m
. a " u e " y a
VP“ I to Tte, ....F......_. - 0.3V, Vrm+th3V permanent damage to the device. This is 1 mm rating only Ind functional
AGND lo DGND ............. - th3V, Vnn + 0.3V opcnu'on ofthe device ll these or my other COMM: above those indicated
Power Dissitntion(Any Package) in the operational sections of this specification is not implied. Exposure to
To + 75'C ..................... 450mW woolute maximum rating audition: for extended puiods may affect device
Derates above + 75°C ................ 6mWPC "lubilitr.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect-
ed; however. permanent damage may occur on unconnectcd devices subject to high energy
ekctmstatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged m the destination socket before devices are removed.
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PINCONFIGURATIONS
DIP, SOIC LCCC
u,, ' . " " , 3 J k ,
m I " V- l t , a "
can ' E v. "
m a 1R't1 " W m 4 " n Yen,
m I mmuuu) a m m I " Fri
m . " m em I £3,551, " am
1mm , El mum] wmu , " m
be! ' El nu MI I u culls!)
a ' " on ' " " " II
Du " " m t g g E i
ORDERING GUIDE'
Temperature Relative Full-Scale Package
Model' Range Accuracy Error Option3
AD75410N -4trCto +85°C t 11.33 2 61.83 N-20
AD7548KN - 40''C to +85°C , 1/2LSB :SLSB N-20
AD7S481P -40''Cto + 85''C t. ILSB :6LSB P-20A
AD7S48KP -40°Cto +85''C tt/2LSB t3LSB P-20A
AD7S481R -40"Cto +85''C L lLSB :GLSB R-20
AD7S48KR -40"Cto +85'C , 1121.83 331.88 R-20
AD7S48AQ .-40'Cto + 85'C , ILSB 161.38 Q-20
AD7S48BQ -40°Cto +85'C ' 1121.88 131.83 Q20
AD75485Q -stt to ' 125''C f.. ILSB :GLSB Q-20
AD7548TQ - 55°C to + 125°C t l/2LSB t SLSB Q-20
AD75488E - 55"an +125°C t lLSB $61.88 E-20A
AD7548TE V -5rcto + 125°C , 1/2LSB :SLSB E-ZOA
'Amlog Devin: resents the right to ship mum: (package outline DUO) packages
in lieu of cerdip We outline 0-20) packages.
't, order 1UL.STDatB, cus, B pmuscd pans, ndd/EBSB to put number.
Contact your loal sales offtce for military data sheet.
'tt - Indies: Cemnic Chip Carrier; N a Plastic DIP; F ... Plastic Leaded
Chip Carricr;Q - Cudip; R - SUIC.
REV. A
HNHLIUIJ utw 1 LED r HA - 1.m - UIII'IHHU nu l L 1 “D D
AD'IS48
PIN FUNCTION DESCRIPTION
rm MNEMONIC nnscmmon
I lnm- DAC cumm (IIIT bus. NomuIIy mmimltd or virtual ground of outpul arnptirset
2 AGN " Analog Ground.
, DCND Digital Croumd.
4 eEil.Tii Chip Select Most Sitttiticaat(M$) Byte. Acme tow Input, Used in combmzmm Wtth VI to load
external dam into the input vep'mez or in mhumkm with WK and IBM: to loud cxtcrml data into
bath input and DAC regiuers, V
S nFIW hm Furmwmu Override. When this input u LOW. data m the UM. rcgmcr is norm] Iu om: ul
twaovcrridc codes wlcetcd byCTR L. When Ihc oserridc signal is removed, thc DAC output
munn ttt 'du, the value in the DAC register. With DMRN HIGH. CTRI. utkux uiIhcr a ml
or right Nstifted input date formal . For normal opcnuon. DFy0tTft" is held H IGH.
DFm CTIL FUNCTION
0 I) DAC. register conerttsrwrrtkidett by all 0's
0 1 DAC register cmitcansuvcvilcrs by all 1's
l 0 Utt.ittstiGtd input dm selected
l l Rightjustirsed input data selected
6 CTRL Control Input. See pin ' Minion.
FMOST SIGNIFICANT BYTE-FIP LEASTSIGNIFICANT BYTE.“
5d tCrrr'juinrierFrry mobs} xlrht Ix ] CTRI.- "n"
x lexlx [a44--uuG/ws-'nrrisuru-r'A Ld CTRL-j'
Xe Gmuarcsmes,
, Dirt Dan Bil 7. Mnu Signifiottt Bil (M SB).
I OB6 Dos Bit 6,
9 OBS Data thh 5.
lil DB4 Dm Bit 4.
I I DN Datit Bil 3.
I2 DN Data Bi: t.
" mu Data Bit l.
u Plow thu Bit 0. Last Sipifreuu Bit (LSB).
l5 LDAC Load DAC Input. active LOW. This signal. in combination wuh others, I) used (uluad III: UM;
ruliswr trom otherthe mpuI registeror tht cxlcmul dau bus.
u, CST.“ Chip Sckct LCIM Signirtcam (1.5) Ibyte. Active LOW input, Used in ctrmhittatitttt with W In kod
cxnurnal dala into the input regiuer m in mmbinaI'wn with \i’i and 1.0.“: u, load extertsal data
mm both mpul and DAC registers,
I 7 WW WRITE Input. This mire krw signal, iiacumbinaim wiIh others is used in 1ttadingcrtterrut dam
into the AD7548 input register and ie. transferring data from the inpul register Io the DAC regislcr.
W! tWB_1ul93ti IIch FUNCTION,
0 I 0 I Load LS Itrre m Input Regime.
o I 0 0 Load " Byte mlnput Register md DAG Register,
0 0 I 1 Load MS Bre Inth Register, .
0 ty I 0 had MS Hymn Input Register and DACRetister.
0 I I 0 Load Inpm Registerto DAC Register.
1 x X X No Dan Trarrstrr
" V", . " to 4 ISV Supplylnpul.
19 V." Meant: Veins: Input.
N In Fudback Resistor. Used for nonml WA ronvmion
CONTROL INPUT INFORMATION
Figure la shows the data load timing diagram for the AD7548. Figure Ib shows the simplified input control structure of the AD7548.
ts- l1.“
-", I----', II._ " unnu
m l t I I W
I --a, t.- -l F- " "
m l I I l I l ''"d,,T mu nvrm
I l u -o4 ' .J n-v. w
I I " ' l.’ t . . - N
mar I I . I I "
I l l l W -
= 2sed " "ue tut; musty
I l l I W - i " i
je-it'-','' Egg " €51.50 o-cts-
lMUf uaIsrns
"m \__I L_J N am o--- cdD
mom u A "
t. Au. mm SIGNAL ms: mo nu nuts KASUKD mom um " ms ttF av. iii p
t. . I, , m
E mm: unsunoum nammcc um I: 'a-',--''. omLttzznwc
1 CW mu 0 mo atn mu In um BE mnmmosn.
a. POI Lm-Jusmtn mu CTIL- "e m nrm- vsv,
Ion mn‘r-Jumnsn nAu 'mu.. osv m ttr66ii= av.
Figure M. AD7548 Timing Diagram Figure tb. Simplified AD7548 Input Control Structure
REV. A .5.
