AD7547AQ ,LC2MOS PARALLEL LOADING DUAL 12-BIT DACSpecifications subject to change without notice.
load = 1000, CEXT = l3pF. DAC registers alterna ..
AD7547BQ ,LC2MOS PARALLEL LOADING DUAL 12-BIT DACcharacteristics are included for Design Guidance only and are not subject to test
(IG, = + 12ll to ..
AD7547CQ ,LC2MOS PARALLEL LOADING DUAL 12-BIT DACGENERAL DESCRIPTION
The AD7547 contains two 12-bit current output DACs on one
monolithic chip. ..
AD7547JN ,LC2MOS PARALLEL LOADING DUAL 12-BIT DACSpecifications subject to change without notice.
load = 1000, CEXT = l3pF. DAC registers alterna ..
AD7547JP ,LC2MOS PARALLEL LOADING DUAL 12-BIT DACGENERAL DESCRIPTION
The AD7547 contains two 12-bit current output DACs on one
monolithic chip. ..
AD7547JR ,LC2MOS PARALLEL LOADING DUAL 12-BIT DACANALOG
DEVICES
V
chmos
Parallel Loading Dual 12-Bit Mt
AD7547
ADG711BR ,CMOS Low Voltage 4 ohm Quad SPST SwitchesSpecifications subject to change without notice.–2– REV. 0ADG711/ADG712/ADG7131(V = +3 V 6 10%, GND ..
ADG711BR-REEL , CMOS Low Voltage, 4 Ω Quad, SPST Switches
ADG711BRU ,CMOS Low Voltage 4 ohm Quad SPST SwitchesSPECIFICATIONSDD B Version–408C toParameter +258C +858C Units Test Conditions/Comments ANA ..
ADG711BRU-REEL , CMOS Low Voltage, 4 Ω Quad, SPST Switches
ADG711BRUZ , CMOS Low Voltage, 4 Ω Quad, SPST Switches
ADG711BRUZ , CMOS Low Voltage, 4 Ω Quad, SPST Switches
AD7547AQ-AD7547BQ-AD7547CQ-AD7547JN-AD7547JP-AD7547JR-AD7547KN-AD7547KN/+-AD7547KP-AD7547LN-AD7547LP
LC2MOS PARALLEL LOADING DUAL 12-BIT DAC
ANALOG
DEVICES
Parallel Loading Dual 12-Bit Mt
AD7547
FEATURES
Two 12-Bit DACs in One Package
DAC Ladder Resistance Matching: 0.5%
Space Saving Skinny DIP and Surface
Mount Packages
4-0uadrant Multiplication
Low Gain Error (1LSB max Over Temperature)
Fast Interface Timing
APPLICATIONS
Automatic Test Equipment
Programmable Filters
Audio Applications
Synchro Applications
Process Control
GENERAL DESCRIPTION
The AD7547 contains two 12-bit current output DACs on one
monolithic chip. Also on-chip are the level shifters, data registers
and control logic for easy microprocessor interfacing. There are
12 data inputs. m, 6%, W control DAC selection and
loading. Data is latched into the DAC registers on the rising
edge of W. The device is speed compatible with most micro-
processors and accepts TTL, 74HC and 5V CMOS logic level
inputs.
The D/A converters provide 4-quadrant multiplication capabilities
with separate reference inputs and feedback resistors. Monolithic
construction ensures that thermal and gain error tracking is
excellent. 12-bit monotonicity is guaranteed for both DACs over
the full temperature range.
The AD7547 is manufactured using the Linear Compatible
CMOS (LCZMOS) process. This allows fast digital logic and
precision linear circuitry to be fabricated on the same die.
REV. A
Information furnished by Analog Devices is believed to be accurate
and reliable. However, no responsibility is assumed by Analog Devices
for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implica-
tion or otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
_/.',"h,
- 0 CK DAC A REGISTER
AD7547
o AGND
CSA 'iy-4Dy-- 4 Vnm
22 Vam;
Cai, "ma
Ce" Imus
m (ii)- I
=. _.' 3 CK DAC B REGISTER
le) “L-
DGND D511 DBO
(MSB) (LSB)
PRODUCT HIGHLIGHTS
1. DAC to DAC Matching
Since both DACs are fabricated on the same chip, precise
matching and tracking is inherent. Many applications which
are not practical using two discrete DACs are now possible.
Typical matching: 0.5%.
2. Small Package Size
The AD7547 is available in 0.3" wide 24-pin DIPs and SOICs
and in 28-terminal surface mount packages.
3. Wide Power Supply Tolerance
The device operates on a + 12V to + 15V VDD, with i 10%
tolerance on this nominal figure. All specifications are guaran-
teed over this range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577
Telex: 924491 Cable: ANALOG NORWOODMASS
A07547-SPEiyFliym01G
1 (h, = +12ll to +15ll, 110%. VREFA = hm, = Ithl; lam = tam, = AGND
= W. All specifications u, to u, unless otherwise specified.)
Parameter J, A Versions K, B Versions L, C Versions S Version T Version U Version Units Test Conditions/Comments
ACCURACY
Resolution 12 l 12 12 12 12 Bits
Relative Accuracy :1 xlQ ' l 2 : l LT l 2 It l: LSBmax
DifferentialNonlinearity : 1 "_" 1 "_- l ' 1 - 1 l LSBmax Allgrades guaranteed
monotonic over temperature.
Gain Error : 6 "_" 3 z l : 6 x3 : 2 LSB max Measured using Rpm, Rrim,
Both DAC registers loaded
with all I's.
Gain Temperature Coefficient';
AGain/hTernrmrature : 5 _ 5 : S LT 5 : S : 5 ppm 'C max Typical value is lppm/oC
Output Leakage Current
IUL'TA
' 25'C 10 10 10 10 10 10 nA max DAC A Register loaded
Tmmto Tmax 150 150 150 250 250 250 nA max with all0's.
lot-rs
+ 25'C 10 10 10 10 10 10 nA max DAC B Registerloaded
Tm". 10TH." 150 150 150 250 250 250 nA max with all O's.
REFERENCE INPUT
Input Resistance 9 9 9 9 9 9 kfl min Typical Input Resistance _ 14kit
20 20 20 20 20 20 lulmax
VREFA: VREFH
Input Resistance Match : 3 : 3 7 1 : 3 7 3 : 1 % max Typically t 0.5%
DIGITAL INPUTS
Vm {Input High Voltage) 2.4 2.4 2.4 2.4 2.4 2.4 V min
Vu (Input LowVohage) 0.8 0.8 0.8 0.8 0.8 0.8 Vmax
[IN (Input Current)
+ 25°C :1 xl tl l t xl “A max VIN = Vm,
Tmmtonax :10 el0 :10 -10 :10 -10 pAmax
Cm (Input Capacitance/ 10 10 10 10 10 pF max
POWER SUPPLY3
Von 10.8/16.S 108/165 1081165 l0.8‘l6.5 10.8 16.5 10.8 l6.5 V min’V max
loo 2 L2 2 2 2 2 mA max
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance only and are not subject to test
(IG, = +121fto +15ll;hm = hm, = +1011, lam = lam = AGND = W. Output Amplifiers are A0644 except where stated.)
Parameter TA = + 25°C TA = Tman, Tu,, Units Test Conditions/Comments
Output Current Settling Time 1.5 - 115 max To 0.01% of full-scale range. Iorrr load = lot/il, Cm” = 13pF.
DAC output measured from rising edge of WR.
Typical Value of Settling Time is 0.8ws.
Digital-to-Analog Glitch Impulse 7 - nV-s typ Measured with Vruirra = Vruiru, = ()V.IovTA,Iocrr,
load = l00ft, CEXT = 13pF. DAC registers alternately
loaded with all 0's and all I's.
AC Feedthrough'
'krr,, lo Imam 7 70 - 65 dB max VRFFA, Verses = 20Vp-p 10kHz sinewave. DAC
Vkpm tolorrr, 7 70 _ 65 dB max registers loaded with all O's.
Power Supply Rejection
AGain ‘AVDD t 0.01 : 0.02 % per % max AVDD = Von max - Vor, min
Output Capacitance
Cur“ 70 70 pF max DAC A, DAC B loaded with all O's.
Cot-m 7O 70 pF max
Cup” 140 140 pF max DAC A, DAC B loaded with all 1's.
Corn; 140 140 pF max
Channel-io-Channel Isolation
VHF" to lou-B - 84 - dB typ VREFA = 20V p-p lOkHz sinewave, VREFB = 0V.
Both DACs loaded with all I's.
Van to 1our, - 84 - dB typ VREFB = 20V p-p lOkHz sinewave, VREFA = 0V.
Both DACs loaded with all I's.
Digital Crosstalk 7 - nV-s typ Measu red for a Code Transition ofall 0's to all I's,
Iocra, Iocm, Load - 1000,CEXT = 13pF
Output Noise Voltage Density 25 - nV/\ E WP Measured between Rpm and IOLTA or Rrm, and lom-H.
tl0Hz-100kHz) _ Frequency ofmeasurement is lOHz-lOOkHz.
Total Harmonic Distortion 7 82 - dB typ VIN = 6V rms, lkHz. Both DACs loaded with all ls.
'Temperature nngeas follows: J, K, L Versions; - 40'C to + 85°C.
A, B,CVersions: - 40°C to t 85''C,
S,T, U Versions: - 55°C to el25'C,
zSample tested It 25°C to ensun compliance.
'Functional It Voo = w with degraded specirtcatimts.
Yin 12 (DGND) on ceramic DIP: is connected to lid.
Srrirtctitiorts subject toclunge without notice.
REV. A
AD7547
TIMING CHARACTERISTICS (IG, = 10.8V to lii.5ll, hen = vm = +IW, lam = Im = AGND = illl)
Limit at Limit at
Limit at TA = - 40°C TA = - 55°C
Parameter T, = + 25°C to + 85°C to + 125°C Units Test Conditions/Comments
t, 60 80 80 ns min Data Setup Time
t2 25 25 25 ns min Data Hold Time
ts 80 80 100 ns min Chip Select to Write Setup Time
t4 0 0 0 ns min Chip Select to Write Hold Time
ts 80 80 100 ns min Write Pulse Width
Specifications subject to change without notice.
[--t, ,------1 tz [T
ABSOLUTE MAXIMUM RATINGS' DATA 'yyyyh ijeeerffC,
(TA = 25°C unless otherwise stated) P_“ __"<_‘ -l ov
Vor, to DGND .................. -0.3V, +17V - _ --)' I c- SV
VREFA, vREFB t0 AGND, .................. t 25V CSA, CSB
VRFBA, VRFBB to AGND, .................. t 25V H-ts--- 5V
Digital Input Voltage to DGND
IOUTA: IOUT]; to DGND
AGND to DGND ..............
Power Dissipation (Any Package)
To + 75°C
Derates above + 75°C ..................
Operating Temperature Range
Commercial Plastic (J, K, L Versions) . . . .
Industrial Hermetic (A, B, C Versions) . . . . -400C to + 85°C
Extended Hermetic (S, T, U Versions) . . . . -55T to + 125°C
Storage Temperature ............. --650C to + 150°C
Lead Temperature (Soldering, 10secs) + 300°C
-0.3V, Vor, +0.3V
-0.3V, Vor, +0.3V
-0.3V, Vor, +0.3V
- 40°C to + 85°C
*Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
EET ESE W FUNCTION
X X 1 No Data Transfer
1 l X No Data Transfer
-3- _f 0 A Rising Edge on (W or CSB Loads
Data to thc Respective DAC from [he Data Bus
0 1 I DAC A Register Loaded from Data Bus
1 o I DAC B Register Loaded from Data Bus
0 o I DAC A and DAC B Registers Loaded
from Data Bus
l. X = Don'tcare
2. I means rising edge triggered
Table /. AD7547 Truth Table
CAUTION
l. ALL INPUT SIGNAL RISE Al rIFALL TIMES MEASURED FROM 10%
TO 90% OF +5v t, = t = vm+vt
2. TIMING MEASUREMEN'T REFOERENCE LEVEL IS"'-L"
Figure 1. Timing Diagram for AD7547
ORDERING GUIDEl
Temperature Relative Gain Package
Model2 Range Accuracy Error Option3
AD7547JN - 40°C to + 85°C t lLSB t 6LSB N-24
AD7547KN - 40°C to + 85°C t 1/2LSB , 3LSB N-24
AD7547LN - 40°C to + 85°C t 1/2LSB t lLSB N-24
AD7547JP - 40°C to + 85°C t ILSB t 6LSB P-28A
AD7547KP - 40°C to + 85°C t 1/2LSB t 3LSB P-28A
AD7547LP - 40°C to + 85°C t 1/2LSB t lLSB P-28A
AD7547JR - 40°C to + 85°C ce lLSB t 6LSB R-24
AD7547KR - 40°C to + 85°C t 1/2LSB t 3LSB R-24
AD7547LR - 40°C to + 85°C t l/2LSB t lLSB R-24
AD7547AQ - 40°C to + 85°C t lLSB t 6LSB Q-24
AD7547BQ - 40°C to + 85°C t 1/2LSB t 3LSB Q-24
AD7547CQ - 40°C to + 85°C , l/2LSB t ILSB Q-24
AD7547SQ - 55°C to + 125°C i ILSB t 6LSB Q-24
AD7547TQ - 55°C to + 125°C , 1/2LSB : 3LSB Q-24
AD7547UQ - 55°C to +125°C , 1/2LSB i 2LSB Q-24
AD7547SE - 55°C to + 125°C i lLSB t 6LSB E-28A
AD7547TE - 55°C to + 125°C , 1/2LSB t SLSB E-28A
AD7547UE - 55°C to + 125°C t 1/2LSB : 2LSB E-28A
IAnalog Devices reserves the right to ship ceramic packages ID-24A) in lieu
of cerdip packages (Q-24).
2To order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact your local sales office for military data sheets.
3E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P - Plastic Leaded
Chip Carrier; Q = Cerdip; R = SOIC.
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are removed.
iisiitiiiiriiti) SENSIY igiaiilIl%
REV. A
AD7547
PIN CONFIGURATIONS
NC = NO CONNECT
DIP, SOIC LCCC PLCC
© qt m '
AGND'I o 24 kwms E g E E ' ll g 5 5 o C, g F,
i ' U o D 3 T I .0 d a 0 u >
n: = d E -0 ' > -
“WE Esusr, 4321282726 nannm a:
Rm 3 22 Vam
vnm E 21 Vor, vnm Von Vnm a Van
CSA 5 20 CSB CSA CSB c-st-x a css
- Lsa DBO - -
[L531 DBO I 6 AD7547 IS WR l I AD7547 WR (LSB) DB0 AD7547 wn
TOP VIEW NC NC
031 I 7 [NottaScale1 a 0311 IMSB] TOP VIEW NC a (Nut): VISEWI 1 NC
DB1 INatto Scale) DB11(MSB) o 0 Cale
DB2 I a 17 DB10 DB1 " Danlmssl
DB2 DBIO
DB3 9 16 DES DB2 m Dew
M33 DES
DB4 IO 15 Dan DB3 m Des
DB5 ll " DB7 12 13 14 15 " 17 18
DGND 12 la Des i', g g 2 ir'g' ti,: ['i',1 E E m E ps E
C V U" © C2 ul ts m
8 o if, E 3 8 8
PIN F UNCTION DESCRIPTION (DIP)
NC = NO CONNECT
PIN MNEMONIC DESCRIPTION
1 AGND Analog Ground.
2 IOUTA Current output terminal of DACA.
3 RFBA Feedback resistor for DACA.
4 VREFA Reference input to DACA.
s cm'' Chip Select Input for DAC A. Active low.
6-18 DB0-DBll 12 data inputs, DBO (LSB)-DB11(MSB).
12 DGND Digital Ground.
19 W Write Input. Data transfer occurs on rising edge of W. See Table I.
20 C-SIT Chip Select Input for DACB. Active low.
21 Vor, Power supply input. Nominally + 12V to + 15V with t 10% tolerance.
22 VREFB Reference input to DACB.
23 RFBB Feedback resistor of DACB.
24 IOUTB Current output terminal of DACB.
CIRCUIT INFORMATION
D/A SECTION
The AD7547 contains two identical 12-bit multiplying D/A
converters. Each DAC consists of a highly stable R-2R ladder
and 12 N-channel current steering switches. Figure 2 shows a
simplified D/A circuit for DAC A. In the R-2R ladder, binary
weighted currents are steered between 1otrrA and AGND. The
current flowing in each ladder leg is constant, irrespective of
switch state. The feedback resistor Rrma is used with an op-amp
(see Figures 4 and S) to convert the current flowing in IotrrA to
a voltage output.
2R 2R 2R 2 2R
S11 S10 so
' 40 AGND
Figure 2. Simplified Circuit Diagram for DACA
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows the equivalent circuit for one of the D/A converters
(DAC A) in the AD7547. A similar equivalent circuit can be
drawn for DACB. Note that AGND is common to both DAC A
and DAC B.
. AGND
Figure 3. Equivalent Analog Circuit for DACA
Cova, is the output capacitance due to the N-channel switches
and varies from about 50pF to 150pF with digital input code.
The current source ILKG is composed of surface and junction
leakages and approximately doubles every 10°C. Ro is the equi-
valent output resistance of the device which varies with input
DIGITAL CIRCUIT INFORMATION
The digital inputs are designed to be both TTL and 5V CMOS
compatible. All logic inputs are static-protected MOS gates with
typical input currents of less than lnA.
REV. A
AD7547
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 4 shows the circuit diagram for unipolar binary operation.
With an ac input, the circuit performs 2-quadrant multiplication.
The code table for Figure 4 is given in Table II.
Operational amplifiers Al and A2 can be in a single package
(AD644, AD712) or separate packages (ADS44, AD711,
AD OP-27). Capacitors Cl and C2 provide phase compensation
to help prevent overshoot and ringing when high speed op-amps
are used.
For zero offset adjustment, the appropriate DAC register is
loaded with all 0's and amplifier offset adjusted so that VOUTA
or VOUTB is 0V. Full-scale trimming is accomplished by loading
the DAC register with all I's and adjusting R1 (R3) so that
VOUTA (Voum) = - VIN (4095/4096). For high temperature
operation, resistors and potentiometers should have a low Tem-
perature Coefficient. In many applications, because of the excellent
Gain T.C. and Gain Error specifications of the AD7547, Gain
Error trimming is not necessary. In fixed reference applications,
full-scale can also be adjusted by omitting R1, R2, R3, R4 and
trimming the reference voltage magnitude.
Figure 4. AD7547 Unipolar Binary Operation
Binary Numberin
DAC Register Analog Output,
MSB LSB VOUTA or Vom
1111 1111 1111 -vrN(t-15,)
1000 0000 0000 -vof-t4) = -U2Vm
0000 0000 0001 -vm(4o-ls)
0000 0000 0000 0V
Table II. Unipolar Binary Code Table for Circuit of
Figure 4
REV. A
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
The recommended circuit diagram for bipolar operation is shown
in Figure 5. Offset binary coding is used.
With the appropriate DAC register loaded to 1000 0000 0000,
adjust R1 (R3) so that VotrrA (VOUTB) = 0V. Alternatively, R1,
R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, R10)
varied for Voum (VOUTB) = 0V. Full-scale trimming can be
accomplished by adjusting the amplitude of VIN or by varying
the value of R5 (R8).
If R1, R2 (R3, R4) are not used, then resistors R5, R6, R7 (R8,
R9, R10) should be ratio matched to 0.01% to ensure gain error
performance to the data sheet specification. When operating
over a wide temperature range, it is important that the resistors
be of the same type so that their temperature coefficients match.
The code table for Figure 5 is given in Table Ill.
Figure 5. Bipolar Operation (Offset Binary Coding)
BinaryNumberin
DAC Register Analog Output,
MSB LSB VOUTA or VOUI'B
1111 1111 1111 +Vm(%)
1000 0000 0001 +VrN(-2o-14s)
1000 0000 0000 OV
0111 1111 1111 -vm(2o-14g)
0000 0000 0000 -vm(22444-l') = -Vm
Table III. Bipolar Code Table for Offset Binary Circuit
of Figure 5.
