AD7545KN ,12-Bit/ Buffered/ Multiplying CMOS DACGENERAL DESCRIPTION The AD7545 is particularly suitable for single supply operationThe AD7545 is a ..
AD7545KN ,12-Bit/ Buffered/ Multiplying CMOS DACFeatures Description• 12-Bit Resolution The AD7545 is a low cost monolithic 12-bit, CMOSmultiplying ..
AD7545KN ,12-Bit/ Buffered/ Multiplying CMOS DACSpecifications subject to change without notice.–2– REV. AAD7545t MODE SELECTIONCHtCSVDDWRITE MODE: ..
AD7545KN ,12-Bit/ Buffered/ Multiplying CMOS DACSPECIFICATIONS REF OUT1V = +5 V V = +15 VDD DD Limits Limits1 1Parameter Version T = + 25CT T T ..
AD7545KN ,12-Bit/ Buffered/ Multiplying CMOS DACSpecifications subject to change without notice.–2– REV. AAD7545t MODE SELECTIONCHtCSVDDWRITE MODE: ..
AD7545KP ,CMOS 12-Bit Buffered Multiplying DACCHARACTERISTICSChip Select to Write Setup Time All 280 380 180 200 ns min See Timing Diagramt 200 2 ..
ADG708BRU ,CMOS, 3 ohm Low Voltage 4-/8-Channel MultiplexersSPECIFICATIONSDD SS B Version C Version–408C –408CParameter +258C to +858C +258C to +858C Uni ..
ADG708BRUZ-REEL , Low Voltage 4-/8-Channel Multiplexers
ADG708CRU ,CMOS, 3 ohm Low Voltage 4-/8-Channel MultiplexersAPPLICATIONSData Acquisition SystemsCommunication SystemsA1 A2 EN A0 A1 ENA0Relay ReplacementAudio ..
ADG708CRUZ , Low Voltage 4-/8-Channel Multiplexers
ADG709BRU ,CMOS, 3 ohm Low Voltage 4-/8-Channel MultiplexersGENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe ADG708 and ADG709 are low voltage, CMOS analog 1. Single/ ..
ADG709CRU ,CMOS, 3 ohm Low Voltage 4-/8-Channel MultiplexersSPECIFICATIONS (V = 3 V 6 10%, V = 0 V, GND = 0 V, unless otherwise noted)DD SS B Version C V ..
AD7545AQ-AD7545BQ-AD7545CQ-AD7545GCQ-AD7545GLN-AD7545GUQ-AD7545JN-AD7545JN.-AD7545JP-AD7545KN-AD7545KP-AD7545LN-AD7545LP
CMOS 12-Bit Buffered Multiplying DAC
REV.A
CMOS 12-Bit
Buffered Multiplying DAC
FUNCTIONAL BLOCK DIAGRAM
RFB
OUT 1
AGND
VDD
DGND
DB11–DB0
(PINS 4–15)
VREF
FEATURES
12-Bit Resolution
Low Gain TC: 2 ppm/�C typ
Fast TTL Compatible Data Latches
Single +5 V to +15 V Supply
Small 20-Lead 0.3" DIP and 20-Terminal Surface Mount
Packages
Latch Free (Schottky Protection Diode Not Required)
Low Cost
Ideal for Battery Operated Equipment
PIN CONFIGURATIONS
DIP LCCC PLCC
GENERAL DESCRIPTIONThe AD7545 is a monolithic 12-bit CMOS multiplying DAC
with onboard data latches. It is loaded by a single 12-bit wide
word and directly interfaces to most 12- and 16-bit bus systems.
Data is loaded into the input latches under the control of the CS
and WR inputs; tying these control inputs low makes the input
latches transparent, allowing direct unbuffered operation of the
DAC.
The AD7545 is particularly suitable for single supply operation
and applications with wide temperature variations.
The AD7545 can be used with any supply voltage from +5 V to
+15 V. With CMOS logic levels at the inputs the device dissi-
pates less than 0.5 mW for VDD = +5 V.
DB6DB5DB4DB3DB2
DGND
AGND
DB11 (MSB)
DB10
DB9
REF
DB8
DB7
VDD
OUT 1
DB0 (LSB)
DB11912310111213
DB11 (MSB)
DB10
DB9
DB8
DB7
VDD
DB0 (LSB)
DB1
DB6
DB5
DB4DB3DB2
DGNDAGNDOUT 1V
REF
AD7545–SPECIFICATIONSDIGITAL INPUTS
SWITCHING CHARACTERISTICS
NOTESTemperature range as follows: J, K, L, GL versions, 0°C to +70°C; A, B, C, GC versions, –25°C to +85°C; S, T, U GU versions, –55°C to +125°C.This includes the effect of 5 ppm max gain TC.
(VREF = +10 V, VOUT1 = O V, AGND = DGND unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*(TA = + 25°C unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +17 V
Digital Input Voltage to DGND . . . . . . .–0.3 V, VDD +0.3 V
VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
VPIN1 to DGND . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Power Dissipation (Any Package) to +75°C . . . . . . .450 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature
TERMINOLOGY
RELATIVE ACCURACYThe amount by which the D/A converter transfer function
differs from the ideal transfer function after the zero and full-
scale points have been adjusted. This is an endpoint linearity
measurement.
DIFFERENTIAL NONLINEARITYThe difference between the measured change and the ideal
change between any two adjacent codes. If a device has a differ-
ential nonlinearity of less than 1 LSB it will be monotonic, i.e.,
the output will always increase for an increase in digital code
applied to the D/A converter.
PROPAGATION DELAYThis is a measure of the internal delay of the circuit and is mea-
sured from the time a digital input changes to the point at which
the analog output at OUT1 reaches 90% of its final value.
DIGITAL-TO-ANALOG GLITCH IMPULSEThis is a measure of the amount of charge injected from the
digital inputs to the analog outputs when the inputs change
state. It is usually specified as the area of the glitch in nV secs
and is measured with VREF = AGND and an ADLH0032CG as
the output op amp, C1 (phase compensation) = 33 pF.
Commercial (J, K, L, GL) Grades . . . . . . . . 0°C to +70°C
Industrial (A, B, C, GC) Grades . . . . . . . . –25°C to +85°C
Extended (S, T, U, GU) Grades . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7545 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE1NOTESAnalog Devices reserves the right to ship either ceramic (D-20) in lieu of cerdip
packages (Q-20).To order MIL-STD-883, Class B process parts, add /883B to part number.
Write Cycle Timing Diagram
CHIP
SELECT
WRITE
DATA IN
(DB0–DB11)
VDD
VDD
VDDMODE SELECTION
NOTES:
VDD = +5V; tr = tf = 20ns
VDD = +15V; tr = tf = 40ns
ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO
90% OF VDD.
TIMING MEASUREMENT REFERENCE LEVEL IS VIH + VIL/2.
AD7545
CIRCUIT INFORMATION—D/A CONVERTER SECTIONFigure 1 shows a simplified circuit of the D/A converter section
of the AD7545 and Figure 2 gives an approximate equivalent
circuit. Note that the ladder termination resistor is connected to
AGND. R is typically 11 kΩ.
RRRRVREF
RFB
OUT 1
AGND
DB11
(MSB)
DB0
(LSB)
DB10DB9DB1Figure 1.Simplified D/A Circuit of AD7545
The binary weighted currents are switched between the OUT1
bus line and AGND by N-channel switches, thus maintaining a
constant current in each ladder leg independent of the switch
state.
The capacitance at the OUT1 bus line, COUT1, is code depen-
dent and varies from 70 pF (all switches to AGND) to 200 pF
(all switches to OUT1).
One of the current switches is shown in Figure 2. The input
resistance at VREF (Figure 1) is always equal to RLDR (RLDR is
the R/2R ladder characteristic resistance and is equal to value
“R”). Since RIN at the VREF pin is constant, the reference termi-
nal can be driven by a reference voltage or a reference current,
ac or dc, of positive or negative polarity. (If a current source is
used, a low temperature coefficient external RFB is recommended
to define scale factor.)
TO LADDER
AGNDOUT 1
FROM
INTERFACE
LOGICFigure 2.N-Channel Current Steering Switch
CIRCUIT INFORMATION—DIGITAL SECTIONFigure 3 shows the digital structure for one bit.
The digital signals CONTROL and CONTROL are generated
from CS and WR.
VIN
CONTROLCONTROL
TO AGND SWITCH
TO OUT1 SWITCHFigure 3.Digital Input Structure
The input buffers are simple CMOS inverters designed so that
power supply. To minimize power supply currents it is recom-
mended that the digital input voltages be as close as practicably
possible to the supply rails (VDD and DGND).
The AD7545 may be operated with any supply voltage in the
range 5 ≤ VDD ≤ 15 volts. With VDD = +15 V the input logic
levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.
BASIC APPLICATIONSFigures 4 and 5 show simple unipolar and bipolar circuits using
the AD7545. Resistor R1 is used to trim for full scale. The
“G” versions (AD7545GLN, AD7545GCQ, AD7545GUD)
have a guaranteed maximum gain error of ±1 LSB at +25°C
(VDD = +5 V), and in many applications it should be possible to
dispense with gain trim resistors altogether. Capacitor C1 provides
phase compensation and helps prevent overshoot and ringing when
using high speed op amps. Note that all the circuits of Figures 4, 5
and 6 have constant input impedance at the VREF terminal.
The circuit of Figure 1 can either be used as a fixed reference
D/A converter so that it provides an analog output voltage in the
range 0 to –VIN (note the inversion introduced by the op amp),
or VIN can be an ac signal in which case the circuit behaves as
an attenuator (2-Quadrant Multiplier). VIN can be any voltage
in the range –20 ≤ VIN + 20 volts (provided the op amp can
handle such voltages) since VREF is permitted to exceed VDD.
Table II shows the code relationship for the circuit of Figure 4.
VDD
VIN
DB11–DB0
ANALOG
COMMON
R2*
(SEE TEXT)
*REFER TO TABLE IFigure 4.Unipolar Binary Operation
Table I.Recommended Trim Resistor Values vs. Grades for
VDD = +5 V
Table II.Unipolar Binary Code Table for Circuit of Figure 4
Figure 5 and Table III illustrate the recommended circuit and
code relationship for bipolar operation. The D/A function itself
uses offset binary code and inverter U1 on the MSB line con-
verts twos complement input code to offset binary code. If ap-
propriate; inversion of the MSB may be done in software using
an exclusive –OR instruction and the inverter omitted. R3, R4
and R5 must be selected to match within 0.01% and they should
be the same type of resistor (preferably wire-wound or metal
foil), so their temperature coefficients match. Mismatch of R3
value to R4 causes both offset and full-scale error. Mismatch of
R5 and R4 and R3 causes full-scale error.
Figure 5.Bipolar Operation (Twos Complement Code)
Table III.Twos Complement Code Table for Circuit of
Figure 5Figure 6 shows an alternative method of achieving bipolar out-
put. The circuit operates with sign plus magnitude code and has
the advantage of giving 12-bit resolution in each quadrant, com-
pared with 11-bit resolution per quadrant for the circuit of Fig-
ure 5. The AD7592 is a fully protected CMOS change-over
switch with data latches. R4 and R5 should match each other to
0.01% to maintain the accuracy of the D/A converter. Mismatch
between R4 and R5 introduces a gain error.
R2*VDDVIN
Table IV.12-Plus Sign Magnitude Code Table for Circuit of
Figure 6Note: Sign bit of “0” connects R3 to GND.
APPLICATIONS HINTS
Output Offset: (CMOS D/A converters exhibit a code depen-dent output resistance which, in turn, causes a code dependent
amplifier noise gain. The effect is a code dependent differential
nonlinearity term at the amplifier output that depends on VOS
where VOS is the amplifier input offset voltage. To maintain
monotonic operation it is recommended that VOS be no greater
than 25 × 10–6) (VREF) over the temperature range of operation.
Suitable op amps are AD517L and AD544L. The AD517L is
best suited for fixed reference applications with low bandwidth
requirements: it has extremely low offset (50 µV) and in most
applications will not require an offset trim. The AD544L has a
much wider bandwidth and higher slew rate and is recommended
for multiplying and other applications requiring fast settling. An
offset trim on the AD544L may be necessary in some circuits.
General Ground Management: AC or transient voltagesbetween AGND and DGND can cause noise injection into the
analog output. The simplest method of ensuring that voltages at
AGND and DGND are equal is to tie AGND and DGND
together at the AD7545. In more complex systems where the
AGND and DGND intertie is on the backplane, it is recom-
mended that two diodes be connected in inverse parallel
between the AD7545 AGND and DGND pins (IN914 or
equivalent).
Digital Glitches: When WR and CS are both low the latchesare transparent and the D/A converter inputs follow the data
inputs. In some bus systems, data on the data bus is not always
valid for the whole period during which WR is low and as a
result invalid data can briefly occur at the D/A converter inputs
during a write cycle. Such invalid data can cause unwanted
glitches at the output of the D/A converter. The solution to this
problem, if it occurs, is to retime the write pulse WR so that it
only occurs when data is valid.
Another cause of digital glitches is capacitive coupling from the
digital lines to the OUT1 and AGND terminals. This should be
minimized by screening the analog pins of the AD7545 (Pins 1,
2, 19, 20) from the digital pins by a ground track run between
Pins 2 and 3 and between Pins 18 and 19 of the AD7545. Note
how the analog pins are at one end of the package and separated
from the digital pins by VDD and DGND to aid screening at
the board level. On-chip capacitive coupling can also give rise
AD7545VDD = +5 volts. However, great care should be taken to ensure
that the +5 V used to power the AD7545 is free from digitally
induced noise.
Temperature Coefficients: The gain temperature coefficientof the AD7545 has a maximum value of 5 ppm/°C and a typical
value of 2 ppm/°C. This corresponds to worst case gain shifts of
2 LSBs and 0.8 LSBs respectively over a 100°C temperature
range. When trim resistors Rl and R2 are used to adjust full-
scale range, the temperature coefficient of R1 and R2 should
also be taken into account. The reader is referred to Analog
Devices Application Note “Gain Error and Gain Temperature
Coefficient of CMOS Multiplying DACs,” Publication Number
E630–10–6/81.
SINGLE SUPPLY OPERATIONThe ladder termination resistor of the AD7545 (Figure 1) is
connected to AGND. This arrangement is particularly suitable
for single supply operation because OUT1 and AGND may be
biased at any voltage between DGND and VDD. OUT1 and
AGND should never go more than 0.3 volts less than DGND or
an internal diode will be turned on and a heavy current may
flow which will damage the device. (The AD7545 is, however,
protected from the SCR latch-up phenomenon prevalent in
many CMOS devices.)
Figure 7 shows the AD7545 connected in a voltage switching
mode. OUT1 is connected to the reference voltage and AGND
is connected to DGND. The D/A converter output voltage is
available at the VREF pin and has a constant output impedance
equal to R. RFB is not used in this circuit.
+15V
REFERENCE
VOLTAGE
15 VOLT CMOS DIGITAL INPUTSFigure 7. Single Supply Operation Using Voltage
Switching Mode
The loading on the reference voltage source is code dependent
and the response time of the circuit is often determined by the
behavior of the reference voltage with changing load conditions.
To maintain linearity, the voltages at OUT1 and AGND should
remain within 2.5 volts of each other, for a VDD of 15 volts. If
VDD is reduced from 15 V, or the differential voltage between
OUT1 and AGND is increased to more than 2.5 V, the differ-
ential nonlinearity of the DAC will increase and the linearity of
the DAC will be degraded. Figures 8 and 9 show typical curves
illustrating this effect for various values of reference voltage and
VDD. If the output voltage is required to be offset from ground
by some value, then OUT1 and AGND may be biased up. The
effect on linearity and differential nonlinearity will be the same
as reducing VDD by the amount of the offset.
VDD – Volts
DNL
LSBFigure 8. Differential Nonlinearity vs. VDD for Figure 7
Circuit. Reference Voltage = 2.5 Volts. Shaded Area Shows
Range of Values of Differential Nonlinearity that Typically
Occur for L, C and U Grades.
VREF – Volts
DNL
LSB
–1.5Figure 9. Differential Nonlinearity vs. Reference Voltage
for Figure 7 Circuit. VDD = 15 Volts. Shaded Area Shows
Range of Values of Differential Nonlinearity that Typically
Occur for L, C and U Grades.
The circuits of Figures 4, 5 and 6 can all be converted to single
supply operation by biasing AGND to some voltage between
VDD and DGND. Figure 10 shows the twos complement bipolar
circuit of Figure 5 modified to give a range from +2 V to +8 V
about a “pseudo-analog ground” of 5 V. This voltage range
would allow operation from a single VDD of +10 V to +15 V.
The AD584 pin-programmable reference fixes AGND at +5 V.
VIN is set at +2 V by means of the series resistors R1 and R2.
There is no need to buffer the VREF input to the AD7545
with an amplifier because the input impedance of the D/A con-
verter is constant. Note, however, that since the temperature
coefficient of the D/A reference input resistance is typically
–300 ppm/°C; applications that experience wide temperature
variations may require a buffer amplifier to generate the +2.0 V
at the AD7545 VREF pin. Other output voltage ranges can be
obtained by changing R4 to shift the zero point and (R1 + R2)
