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AD7545ABQ-AD7545ACQ-AD7545AKN-AD7545AKP-AD7545AKR-AD7545ALN-AD7545ALP-AD7545ATQ
CMOS 12-Bit Buffered Multiplying DAC
REV.C
CMOS 12-Bit
Buffered Multiplying DAC
FUNCTIONAL BLOCK DIAGRAMFEATURES
Improved Version of AD7545
Fast Interface Timing
All Grades 12-Bit Accurate
20-Lead DIP and Surface Mount Packages
Low Cost
PIN CONFIGURATIONS
DIP/SOICLCCCPLCC
GENERAL DESCRIPTIONThe AD7545A, a 12-bit CMOS multiplying DAC with internal
data latches, is an improved version of the industry standard
AD7545. This new design features a WR pulse width of 100 ns,
which allows interfacing to a much wider range of fast 8-bit and
16-bit microprocessors. It is loaded by a single 12-bit-wide word
under the control of the CS and WR inputs; tying these control
inputs low makes the input latches transparent, allowing unbuf-
fered operation of the DAC.
AD7545A–SPECIFICATIONSDYNAMIC PERFORMANCE
DIGITAL INPUTS
POWER SUPPLY
NOTES
1Temperature range as follows:K, L Versions = 0°C to +70°C; B, C Versions = –25°C to +85°C; T, U Versions = –55°C to +125°C.
2Sample tested to ensure compliance.
3DB0–DB11 = 0 V to VDD or VDD to 0 V.
4Feedthrough can be further reduced by connecting the metal lid on the ceramic package to DGND.
6Logic inputs are MOS gates. Typical input current (+25°C) is less than 1 nA.
Specifications subject to change without notice.
(VREF = �10 V, VOUT1 = O V, AGND = DGND unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*(TA = + 25°C unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V, +17 V
Digital Input Voltage to DGND . . . . . . .–0.3 V, VDD +0.3 V
VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
VPIN1 to DGND . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
Power Dissipation (Any Package) to 75°C . . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature Range
Commercial (KN, LN, KP, LP) Grades . . . 0°C to +70°C
Industrial (BQ, CQ, BE, CE) Grades . . . . –25°C to +85°C
Extended (TQ, UQ, TE, UE) Grades . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are removed.
ORDERING GUIDEAD7545AUQ
AD7545ATE
NOTESTo order MIL-STD-883, Class B process parts, add /883B to part number.
Contact local sales office for military data sheet.E = Leadless Ceramic Chip Carrier (LCCC); N = Plastic DIP; P = Plastic
Leaded Chip Carrier (PLCC); Q = Cerdip; R = Small Outline IC.
WRITE CYCLE TIMING DIAGRAM
AD7545A
CIRCUIT INFORMATION—D/A CONVERTER SECTIONFigure 1 shows a simplified circuit of the D/A converter section
of the AD7545A, and Figure 2 gives an approximate equivalent
circuit. Note that the ladder termination resistor is connected to
AGND. R is typically 15 kΩ.
The binary weighted currents are switched between the OUT1
bus line and AGND by N-channel switches, thus maintaining a
constant current in each ladder leg independent of the switch
state.
Figure 1.Simplified D/A Circuit of AD7545A
The capacitance at the OUT1 bus line, COUT1, is code-
dependent and varies from 70 pF (all switches to AGND) to
150 pF (all switches to OUT1).
One of the current switches is shown in Figure 2. The input
resistance at VREF (Figure 1) is always equal to R. Since RIN at
the VREF pin is constant, the reference terminal can be driven by
a reference voltage or a reference current, ac or dc, of positive or
negative polarity. (If a current source is used, a low temperature
coefficient external RFB is recommended to define scale factor.)
Figure 2.N-Channel Current Steering Switch
CIRCUIT INFORMATION—DIGITAL SECTIONFigure 3 shows the digital structure for one bit.
The digital signals CONTROL and CONTROL are generated
from CS and WR.
Figure 3.Digital Input Structure
The input buffers are simple CMOS inverters designed such
input buffers operate in their linear region and draw current
from the power supply. To minimize power supply currents it is
recommended that the digital input voltages be as close to the
supply rails (VDD and DGND) as is practically possible.
The AD7545A may be operated with any supply voltage in the
range 5 ≤ VDD ≤ 15 volts. With VDD = +15 V the input logic
levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.
BASIC APPLICATIONSFigures 4 and 5 show simple unipolar and bipolar circuits using
the AD7545A. Resistor R1 is used to trim for full scale. The L,
C, U grades have a guaranteed maximum gain error of ±1 LSB
at +25°C, and in many applications it should be possible to
dispense with gain trim resistors altogether. Capacitor C1 pro-
vides phase compensation and helps prevent overshoot and
ringing when using high speed op amps. Note that all the cir-
cuits of Figures 4, 5 and 6 have constant input impedance at the
VREF terminal.
The circuit of Figure 4 can either be used as a fixed reference
D/A converter so that it provides an analog output voltage in the
range 0 to –VIN (note the inversion introduced by the op amp)
or VIN can be an ac signal in which case the circuit behaves as
an attenuator (2-Quadrant Multiplier). VIN can be any voltage
in the range –20 ≤ VIN ≤ +20 volts (provided the op amp can
handle such voltages) since VREF is permitted to exceed VDD.
Table II shows the code relationship for the circuit of Figure 4.
Figure 4.Unipolar Binary Operation
Table I.Recommended Trim Resistor Values vs. Grades
Table II.Unipolar Binary Code Table for Circuit of Figure 4
Figure 5 and Table III illustrate the recommended circuit and
code relationship for bipolar operation. The D/A function itself
uses offset binary code and inverter U1 on the MSB line con-
verts twos complement input code to offset binary code. If ap-
propriate, inversion of the MSB may be done in software using
an exclusive –OR instruction and the inverter omitted. R3, R4
and R5 must be selected to match within 0.01%, and they
should be the same type of resistor (preferably wire-wound or
metal foil), so that their temperature coefficients match. Mis-
match of R3 value to R4 causes both offset and full-scale error.
Mismatch of R5 to R4 and R3 causes full-scale error.
Figure 5.Bipolar Operation (Twos Complement Code)
Table III.Twos Complement Code Table for Circuit of
Figure 5Figure 6 and Table IV show an alternative method of achieving
bipolar output. The circuit operates with sign plus magnitude
code and has the advantage that it gives 12-bit resolution in
each quadrant compared with 11-bit resolution per quadrant for
the circuit of Figure 5. The AD7592 is a fully protected CMOS
change-over switch with data latches. R4 and R5 should match
each other to 0.01% to maintain the accuracy of the D/A con-
verter. Mismatch between R4 and R5 introduces a gain error.
Refer to Reference 1 (supplemental application material) for
additional information on these circuits.
Figure 6.12-Bit Plus Sign Magnitude Converter
Table IV.12-Bit Plus Sign Magnitude Code Table for Circuit
of Figure 6Note:Sign bit of “0” connects R3 to GND.
APPLICATIONS HINTS
Output Offset:CMOS D/A converters such as Figures 4, 5
and 6 exhibit a code dependent output resistance which, in turn,
can cause a code dependent error voltage at the output of the
amplifier. The maximum amplitude of this error, which adds
to the D/A converter nonlinearity, depends on VOS, where VOS
is the amplifier input offset voltage. To maintain specified accuracy
with VREF at 10V, it is recommended that VOS be no greater than
0.25mV, or (25 × 10–6) (VREF), over the temperature range of
operation. Suitable op amps are AD517 and AD711. The AD517
is best suited for fixed reference applications with low band-
width requirements: it has extremely low offset (150µV max for
lowest grade) and in most applications will not require an offset
trim. The AD711 has a much wider bandwidth and higher slew
rate and is recommended for multiplying and other applications
requiring fast settling. An offset trim on the AD711 may be
necessary in some circuits.
General Ground Management:AC or transient voltages
between AGND and DGND can cause noise injection into the
analog output. The simplest method of ensuring that voltages at
AGND and DGND are equal is to tie AGND and DGND
together at the AD7545A. In more complex systems where the
AGND and DGND intertie is on the backplane, it is recom-
mended that two diodes be connected in inverse parallel between
the AD7545A AGND and DGND pins (1N914 or equivalent).
AD7545A
Invalid Data:When WR and CS are both low, the latches are
transparent and the D/A converter inputs follow the data inputs.
In some bus systems, data on the data bus is not always valid for
the whole period during which WR is low, and as a result invalid
data can briefly occur at the D/A converter inputs during a write
cycle. Such invalid data can cause unwanted signals or glitches
at the output of the D/A converter. The solution to this prob-
lem, if it occurs, is to retime the write pulse, WR, so it only
occurs when data is valid.
Digital Glitches:Digital glitches result due to capacitive cou-
pling from the digital lines to the OUT1 and AGND terminals.
This should be minimized by screening the analog pins of the
AD7545A (Pins 1, 2, 19, 20) from the digital pins by a ground
track run between Pins 2 and 3 and between Pins 18 and 19 of
the AD7545A.
Note how the analog pins are at one end (DIP) or side (LCC
and PLCC) of the package and separated from the digital pins
by VDD and DGND to aid screening at the board level. On-chip
capacitive coupling can also give rise to crosstalk from the digital-
to-analog sections of the AD7545A, particularly in circuits with
high currents and fast rise and fall times. This type of crosstalk is
minimized by using VDD = +5 volts. However, great care should
be taken to ensure that the +5V used to power the AD7545A is
free from digitally induced noise.
Temperature Coefficients:The gain temperature coefficient
of the AD7545A has a maximum value of 5ppm/°C and a typi-
cal value of 2ppm/°C. This corresponds to worst case gain shifts
of 2LSBs and 0.8LSBs respectively over a 100°C temperature
range. When trim resistors R1 and R2 (such as in Figure 4) are
used to adjust full-scale range, the temperature coefficient of R1
and R2 should also be taken into account. The reader is referred
to Analog Devices Application Note “Gain Error and Gain
Temperature Coefficient to CMOS Multiplying DACs,” Publi-
cation Number E630c–5–3/86.
SINGLE SUPPLY OPERATIONThe ladder termination resistor of the AD7545A (Figure 1) is
connected to AGND. This arrangement is particularly suitable
for single supply operation because OUT1 and AGND may be
biased at any voltage between DGND and VDD. OUT1 and
AGND should never go more than 0.3 volts less than DGND or
an internal diode will be turned on and a heavy current may
flow that will damage the device. (The AD7545A is, however,
protected from the SCR latchup phenomenon prevalent in many
CMOS devices.)
Figure 7 shows the AD7545A connected in a voltage switching
mode. OUT1 is connected to the reference voltage and AGND
is connected to DGND. The D/A converter output voltage is
available at the VREF pin and has a constant output impedance
equal to R. RFB is not used in this circuit and should be tied to
OUT1 to minimize stray capacitance effects.
The loading on the reference voltage source is code-dependent
and the response time of the circuit is often determined by the
behavior of the reference voltage with changing load conditions.
To maintain linearity, the voltages at OUT1 and AGND should
remain within 2.5 volts of each other, for a VDD of 15 volts. If
VDD is reduced from 15V, or the differential voltage between
OUT1 and AGND is increased to more than 2.5V, the differ-
ential nonlinearity of the DAC will increase and the linearity of
the DAC will be degraded. Figures 8 and 9 show typical curves
illustrating this effect for various values of reference voltage and
VDD. If the output voltage is required to be offset from ground
by some value, then OUT1 and AGND may be biased up. The
effect on linearity and differential nonlinearity will be the same
as reducing VDD by the amount of the offset.
Figure 8.Differential Nonlinearity vs. VDD for Figure 7
Circuit. Reference Voltage = 2.5 Volts. Shaded Area Shows
Range of Values of Differential Nonlinearity that Typically
Occur for all Grades.
Figure 9.Differential Nonlinearity vs. Reference Voltage
