AD7543 ,12-Bit, Multiplying Iout, SERIALfeatures excellent gain T.C. Iprm/OC typ;
Sppm/OC max), +5V operation and latch-free operation.
( ..
AD7543GBQ ,CMOS SERIAL INPUT 12-BIT DACFEATURES
Resolution: 12 Bits
Nonlinearity: i1/2LSB Tmin to Tmax
Low Gain T.C.: 2ppm/°C typ ..
AD7543GKN ,CMOS SERIAL INPUT 12-BIT DACfeatures excellent gain T.C. Iprm/OC typ;
Sppm/OC max), +5V operation and latch-free operation.
( ..
AD7543GKR ,CMOS SERIAL INPUT 12-BIT DACapplications.
The DAC's logic circuitry consists of a 12-bit serial-in parallel-
out shift regi ..
AD7543JN ,CMOS SERIAL INPUT 12-BIT DACfeatures excellent gain T.C. Iprm/OC typ;
Sppm/OC max), +5V operation and latch-free operation.
( ..
AD7543JNZ , CMOS Serial Input 12-Bit DAC
ADG609BN ,3 V/5 V, 4/8 Channel High Performance Analog MultiplexersSPECIFICATIONS1(V = +5 V 6 10%, V = –5 V 6 10%, GND = 0 V, unless otherwise noted)DUAL SUPPLY DD SS ..
ADG609BR ,3 V/5 V, 4/8 Channel High Performance Analog MultiplexersCHARACTERISTICSt 80 80 ns typ R = 300 Ω, C = 35 pF;TRANSITION L L100 130 100 150 ns max V = 3.5 V/0 ..
ADG611YRU ,1 pC Chanrge Injection, 100 pA Leakage, CMOS +-5 V/+5 V/+3 V Quad SPST SwitchesGENERAL DESCRIPTION PRODUCT HIGHLIGHTS1. Ultralow Charge Injection (1 pC typically)The ADG611, ADG6 ..
ADG612YRU-REEL7 ,CMOS ±5 V/5 V/3 V Quad SPST SwitchesGENERAL DESCRIPTION PRODUCT HIGHLIGHTS1. Ultralow Charge Injection (1 pC typically)The ADG611, ADG6 ..
ADG619BRM ,CMOS +-5 V/ +5V 4 OHM SINGLE SPDT SWITCHESCHARACTERISTICSADG619t 80 ns typ R = 300 Ω , C = 35 pFON L L120 155 ns max V = 3.3 V, Test Circuit ..
ADG619BRT ,CMOS +-5 V/ +5V 4 OHM SINGLE SPDT SWITCHESGENERAL DESCRIPTION Table I. Truth Table for the ADG619/ADG620The ADG619 and the ADG620 are monolit ..
AD7543
12-Bit, Multiplying Iout, SERIAL
ANALOG
DEVICES
Serial Input 12-Bit Mil
AD7543
FEATURES
Resolution: 12 Bits
Nonlinearity: tl/2LSB Tmin to Tmax
Low Gain T.C.: 2ppm/°C typ, Sppm/'c max
Serial Load on Positive or Negative Strobe
Asynchronous CLEAR Input for Initialization
Full 4-Quadrant Multiplication
Low Multiplying Feedthrough: 1LSB max ti 10kHz
Requires no Schottky Diode Output Protection
Low Power Dissipation: 40mW max
+5V Supply
Small Size:
Package
Low Cost
16-Pin DIP or 20-Terminal Surface Mount
GENERAL DESCRIPTION
The AD7543 is a precision 12-bit monolithic CMOS multi-
plying DAC designed for serial interface applications.
The DAC's logic circuitry consists of a 12-bit serial-in parallel-
out shift register (Register A) and a 12-bit DAC input register
(Register B). Serial data at the AD7S43 SRI pin is clocked into
Register A on the leading or trailing edge (user selected) of the
strobe input. Once Register A is full its contents are loaded in-
to Register B under control of the LOAD inputs.
FUNCTIONAL BLOCK DIAGRAM
AD7543
1 OUT1
12-BIT D/A CONVERTER
2 OUT
"si""'" 1 3 AGND
DAC REGISTER B
REGISTER A m
t2.BIT SHIFT REGISTER 7 s
12 DGND
Initialization is simplified by the use of the CLR input which
provides an asynchronous reset of Register B.
Packaged in 16-pin DIP and 20-pin LCCC and PLCC, the
AD7543 features excellent gain T.C. Iprm/OC typ;
Sppm/OC max), +5V operation and latch-free operation.
(No protection Schottky Diodes required.)
PIN CONFIGURATIONS
DIP LCCC PLCC
j-" z " 's S o m E
D D E " '
V O O I ' O o a I >
OUT1 1 o 16'an 3 2 1 2019 EIBIIEEIB
cum 2 El v“,
AGND E El vm, AGND 4 18 V00 AGND n Von
- STB, 5 17 m -
STBI E AD7543 E CLR NC 6 AD7543 16 NC STBI a AD7543 cm
- TOP VIEW TOP VIEW C
L01 5 El DGND NC a rovvnzw N
E (Not to Scale) m 7 (Not to Sealel 15 DGND - (Not to Scale)
NC cc E STB4 L01 DGND
NC 8 " STB4
sm 7 In staa NC El s BO
STB2 a 9 m 9 to " 13
a g g g a m m
m tr, .1 r- - N
NC=NOCONNECT tn 5, m E li 3
NC = NOCONNECT tr, " tr,
REV. B
Information furnished by Analog Devices is believed to be accurate
and reliable. However, no responsibility is assumed by Analog Devices
for its use; nor for any infringements of patents or other rights of third
parties which may result from its use> No license is granted by implica-
tion or otherwise under any patent or patent rights of Analog Devices.
NC = NDCONNECT
One Technology Way, PO. Box 9106, Norwood, MA 02062-9106, U.S.A,
Tel: 617/329-4700 Fax: 6171326-8703 wa: 710/394-6577
Telex: 924491 Cable: ANALOG NORWOODMASS
AD7543 -SPEiyFliWl0lG (VDD = +5ll, VREF = +1illl, Voun'= me = illl, unless otherwise noted.)
Limit At' Limit Atl
Limit At TA " -40''C TA . -ss"c
mu" TA " ogs''C to +85°C & ei2S''C Units Conditions/Comments
ACCURACY
Resolution 12 12 12 Bits
Relative Accuracy'
J. A, S Versions " 11 tl LSB max
K, B, T Versions 21/2 11/2 11/2 LSB max
GK, GB, GT Versions 11/2 21/2 11/2 LSB max
Differential Noruinearity2
J, A, S Versions 12 t2 " LSB max Monotonic to 11 bits from Tmin w Tmu
K, B, T Versions tl 21 tl LSB max Monotonic to 12 bits from Tmin to Tmax
GK, GB, GT Versions 11 tl tl LSB max Monotonic to 12 bits from Tmin to Tmax
Gain Error2
J, K, A, B, S. T 112.3 t13.5 214.5 LSB max Using internal RFB only (gain error can be
GK, GB, GT 11 Al 22 LSB max trimmed to zero using circuits of Figures 6 & 7)
Gain Temperature Coefficient
AGainlATempcraturc 5 S 5 ppm/OC max Typical value is prm/OC
Power Supply Rejection
AGIin/AVDD 0.005 0.01 0.01 ‘16 per % max VDD = " 75V to +5.25V
Output Leakage Current
bun (Pin 4) 1 10 200 nA max DAC Register loaded with all Os
kwr2 (Pin 5) 1 10 200 nA max DAC Register loaded with all ls
DYNAMIC PERFORMANCE
Current Settling Tune3 2.0 2.0 2.0 Ms max To 1/2LSiOUT123d = 1009. DAC output measured from falling
edge of LD1 and LD, see Figure 5.
Multiplying Feedthrough Errors 2.5 2.5 2.5 mV p-p max VREF = tlov, 10kHz sine wave
REFERENCE INPUT
Input Resistance(pin 15) 8/15/25 8/15/25 8/15/25 ki2 rmn/typ/max Typical temperuure cocmucm 15 -woppm/'c
ANALOG OUTPUTS
Output Cafacuancc
COUTI 75 75 75 pF max Register B loaded to 0000 0000 0000
(OUT13 260 260 260 pF max Register B loaded to 1111 1111 1111
COUTzl 75 75 75 pF max RegisterBloaded to 1111 1111 1111
COUTZJ 260 260 260 pf max Register B loaded to 0000 0000 0000
LOGIC INPUTS
VINH(Log1cHlGH Voltage) 030 53.0 " o V mm
VINL (Logic LOW Voltage) *0.8 00.8 +0.8 V max
' 1 1 1 PA max le = OVor Voo
Cm (Input Capacitance)' 8 8 8 pF mu
Input Codmg 12-Bit Unipolar Binary or 12-Bit Offset
Bmary (see Figures 6 and 7), serial load
(MSB First)
swncnmc CHARACTERISTICS'
tDSI 50 100 100 ns mm Serul Input STBl used as a strobe
105.. 0 0 0 ns mm to Strobe fEY, used " a strobe
(pg; 0 0 0 ns mm Setup Time STB3 used as a strobe
tDS2 20 40 40 ns mm STB used as a strobe
IDHI 30 60 60 ns mm Sun] In ur STB1 used as a strobe
10114 80 160 160 ns mm to $er b $34 uscd as a strobe
‘DHS 80 160 160 ns mm 11 ld T o e STB used as a strobe
tDH2 60 120 120 ns mm 0 1me STB2 used as a strobe
tsm 80 160 160 ns min SR1 data pulse wudrh
'STBI 80 160 160 ns mm STE] pulse wrdth
(5154 100 200 200 ns mm STB4 pulse wuith
[STE] 100 200 200 ns mm WE, pulse w1dth
tSTB2 80 160 160 ns min STB2 pulse wrdth
tLDi, tLD2 150 300 300 ns min Load pulse w1dth
tASB 0 0 0 ns mm Min time between strobmg LSB Into Regstcr A and loadmg Regmu B
tCLR 200 400 400 ns mm CLR pulse width
POWER SUPPLY
VDD (Supply Voltage) +5 +5 +5 V
IDD (Supply Current) 2.5 2.5 2.5 mA max Digital Inputs = VIN” or VINL
'Temperature ranges as follows: JN, KN, GKN Version; -4W'C ro e85"C
AQ, BQ, GBQ Versions: -40'C. to -85''C
SQ, TQ, GTQ Versions: -55"C to t 125"C
' Terminology on following page.
'Guaranteed but not lested.
'Lagic inputs are MOS gates. Typical input current 1+25"CJ is less than lnA.
'Sample rested " +25°C to ensure compliance.
Specifications subject to change without notice.
REV. B
AD7543
ABSOLUTE MAXIMUM RATINGS'
(TA = + 25°C unless otherwise noted)
ORDERING GUIDE
Temperature Relative Gain Package
VDD t0 AGND ................... 0V, +7V Model Range Accuracy Error Option'
X81131; {00%;an . . . . . . . . . . . . . . . . . ’V 0‘23: AD7543JN -40oCto +85°C 11LSB 112.3LSB N-16
DGND to AGND ................. VDD + iGir AD7543KN -40''C to + 85°C 11/2LSB 112.3LSB N-16
. . B................ DD . AD7543GKN -40oC to + 85°C t 1/2LSB t lLSB N-l6
Digital Input Voltage to DGND -0.3V, VDD +0.3V AD7543JP -4(Y'C to + 85°C 11LSB 112.3LSB P-20A
stty,', chtho AGND ....... -0.3V, VDD to +0.3V AD7543KP -40°C to +23% t 1/2LSB 112.3LSB P-20A
VREF to 1t2 ..................... 125v AD7543GKP -40oC to + 85°C 11/2LSB 11LSB P-20A
RFB tfl: . . ..................... t25V AD7543JR -40°Cto + 85°C 11LSB 112.3LSB R-l6
Poy.erissipation(Package) AD7543KR -40'Cto + 85°C 11/2LSB 112.3LSB R-16
Plastic o AD7543GKR -40'Cto + 85°C 11/2LSB 11LSB R-16
To +70 C . . . .0 ................ 670mW AD7543AQ _400C to +850C t ILSB $1231.88 Q-16
perates above +70 C by ............ 8.3mWf'C AD7543BQ _400C to + 850C t 1/2LSB t12.3LSB Q-16
Cerdip 0 AD7543GBQ -40oCto + 85°C t l/2LSB 11LSB Q-16
To +75 C . . . l ................ 15/tee,' AD7543SQ - 55°C to +125°C 1 lLSB 112.3LSB Q-l6
Dean‘s above +75 C by ............. 6mW/ C AD7543TQ - 55°C to +125°C 11/2LSB 112.3LSB Q-16
opfratingTt.Trrreurt Range . AD7543GTQ - 55°C to +125°C 11/2LSB 11LSB Q-16
Commercial (L K, GK Versions) ..... -40oC to +85''C AD75438E -55°Ct0 + 125°C t lLSB 112.3LSB E-20A
Industrial(A,B,GB Versions) ...... -40oC to +85''C AD7543TE -55oCto +125°C 11/2LSB 112.3LSB E-20A
Extended (S, T, GT Versions) ...... -55T to +125°C AD7543GTE _ 55°C to + 125°C t 1/2LSB t ILSB E-20A
............ -65"C to + 150°C
+ 300°C
Storage Temperature
Lead Temperature (Soldering, 10secs)
*E = Leadless Ceramic Chip Carrier (LCCC); N = Plastic DIP; P = Plastic Leaded
*Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
CAUTION
Chip Carrier (PLCC); Q = Cerdip; R = Small Outline IC (SOIC).
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect-
ed; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
ililq.JJ..ilFBl,sssses,ss
PIN MNEMONIC FUNCTION
1 OUTl DAC current output bus, Normally terminated at op amp virtual ground
2 OUT2 DAC current output bus. Normally terminated at AGND
3 AGND Analog Ground
4 STBl Register A Strobe 1 input, see Table ll
5 m DAC Register B Load 1 input. When L_Dl and LT) go low the contents
of Register A are loaded into DAC Register B
6 N/C No Connection
7 SR1 Serial Data Input to Register A
8 STB2 Register A Strobe 2 input, see Table II
9 m DAC Register B Load 2 input. When 171r1 and TM go low the contents
of Register A are loaded into DAC Register B
10 STBS Register A Strobe 3 input, see Table II
11 STB4 Register A Strobe 4 input, see Table II
12 DGND Digital Ground
13 m Register B CLEAR input (active LOW), can be used to asynchronously
reset Register B to 0000 0000 0000
14 VDD +5V Supply Input
15 VREF Reference input. Can be positive or negative dc voltage or ac signal
16 RF] DAC Feedback Resistor
Table h Pin Function Description, DIP Configuration
REV. B
AD7543
TERMINOLOGY
RELATIVE ACCURACY
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function, It is measured after
adjusting for ideal zero and full scale and is expressed in % or
ppm of full-scale range or (sub) multiples of lLSB.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the difference between the mea-
sured change and the ideal I LSB change between any two
adjacent codes. A specified differential nonlinearity of i1
LSB max over the operating temperature range ensures
monoronicity,
GAIN ERROR
Gain is defined as the ratio of the DAC's Full Scale output
to its reference input voltage. An ideal AD7543 would exhibit
a gain of -4095/4096. Gain error is adjustable using external
trims as shown in Figures 6 and 7.
OUTPUT LEAKAGE CURRENT
Current which appears at OUT1 with Register B loaded to all
O's or at OUT 2 with Register B loaded to all I's.
MULTIPLYING FEEDTHROUGH ERROR
AC error due to capacitive feedthrough from VRIiF terminal
to OUT1 with DAC register loaded to all O's.
GENERAL CIRCUIT INFORMATION
The AD7543, a 12-bit multiplying D/A converter, consists of
a highly stable thin film R-2R ladder and twelve N-channel
current switches on a monolithic chip. Most applications
require the addition of only an output operational amplifier
and a voltage or current reference.
The simplified D/A circuit is shown in Figure I. An inverted
R-2R ladder structure is used-that is, the binarily weighted
currents are switched between the OUT1 and OUT2 bus lines,
thus maintaining a constant current in each ladder leg indepen-
dent of the switch state.
DACREGISTERB
Figure 1. AD7543 Functional Diagram
One of the current switches is shown in Figure 2. The input
resistance at VREF (Figure 2) is always equal to RLDR
(RLDR is the R/2R ladder characteristic resistance and is
equal to value "R''). The reference terminal can be driven
by a reference voltage or a reference current, ac or dc, of
positive or negative polarity. If a current source is used, a
low temperature coefficient external RFB is recommended to
define scale factor.
TOLADDER
INTERFACE
OUT2 OUT1
Figure 2. N-Channel Current Steering Switch
EQUIVALENT CIRCUIT ANALYSIS
The equivalent circuits for all digital inputs LOW and all
digital inputs HIGH are shown in Figures 3 and 4. In Figure
3 with all digital inputs LOW, the reference current is switched
to OUT2. The current source [LEAKAGE is composed of sur-
face and junction leakages to the substrate, while the 1/4096
current source represents a constant 1 least significant bit cur-
rent drain through the termination resistor on the R-2R ladder.
The "ON" capacitance of the output N-channel switch is
260pF, as shown on the OUT2 terminal. The "OFF" switch
capacitance is 75pF, as shown on the OUT1 terminal. Analysis
of the circuit for all digital inputs HIGH, as shown in Figure
4, is similar to Figure 3; however, the "ON" switches are now
on terminal OUT1, hence the 260pF at that terminal.
'LEAKAGE g
R Att 15k
- A) OUT2
IRES l 'l4096 'LEAKAGE $260pF
Figure 3. AD7543 DAC Equivalent Circuit
All Digital Inputs LOW
'LEAKAGE 6
Figure 4. AD7543 DAC Equivalent Circuit
A// Digital Inputs HIGH
-4- REV.B
Applications - A07543
AD7543 Logic Inputs
Register A Control Inputs Register B Control Inputs AD7543 Operation Notes
STB4 Was STB2 STBl CH E m
0 1 0 I X X X Data Appearing At SR1 Strobed Into Register A 2,3
0 l J- o X X X Data Appearing At SRI Strobed into Register A 2,3
0 1 0 o x X X Data Appearing At SR1 Strobed Into Register A 2,3
I 1 0 O X X X Data Appearing At SRI Strobed Into Register A 2,3
1 x X X
X 0 X X . _
X x 1 X No Operation (Register A) 3
X X X 1
0 X X Clear Register B To Code 0000 0000 0000 (Asynchronous Operation) 1,3
1 l X .
1 1 No Operation (Register B) 3
l 0 0 Load Register B With The Contents of Register A 3
NOTES:
l. CLR =0 Asynchronously resets Register B to 0000 0000 0000, but has no effect on Register A.
2. Serial data IS loaded into Register A MSB first, on edges shownjis positive edgetis negative edge.
3. 0= Logic LOW.1= Logic HIGH. X = Don't Care.
Table th AD7543 Truth Table
I-tsm--]
tos1, tosz. tosa
tom . mm. mm
)si( BIT1 )x( >< '
' MSB BIT 2 - C)yC
BIT11 A, LSB )f
STROBE INPUT I 1 u 2
(STB1, STB2, STB4) I l
tsrtet
(NOTE) I ma:
HAND m
STRQBE WAVEFORM IS INVERTED IF
STB3 IS USED TO STROBE SERIAL DATA
BITS INTO REGISTER A.
$734 I
Ids-Te-L- LOADING REGISTER A------;
LOADING REGISTER a / _r
WITH CONTENTS OF REGISTER A
F igure 5. Timing Diagram
INTERFACE LOGIC INFORMATION
Shown in the AD8543 Functional Diagram Register A is a 12-
bit shift register. Serial data appearing at pin SR1 is clocked
into the shift register on the leading (rising) edge of STBl,
STB2 or STB4 or on the leading (falling) edge of ST-B3. Table
11 defines the various logic states required on the Register A
control inputs, while Figure 5 illustrates the Register A
loading sequence.
Once Register A is full, the data is transferred to Register B
by bringing tTI5T and 1Ti55momentarily LOW.
Register B can be asynchronously reset to 0000 0000 0000
by bringing am momentarily LOW. This allows the DAC
output voltage to be set to a known condition, thus simplify-
ing system initialization procedure. When operating the
AD7543 in the unipolar circuit of Figure 6, 3 CLEAR causes
the DAC output voltage to equal ov, When using the bipolar
circuit of Figure 7, a CLEAR causes the DAC output to equal
-VREF.
REV. B
APPLYING THE AD7543
UNIPOLAR BINARY OPERATION
(2AIUADRANT MULTIPLICATION)
Figure 6 shows the analog circuit connections required for uni-
polar binary (2-quadrant multiplication) operation. The logic
inputs are omitted for clarity. With a dc reference voltage or
current (positive or negative polarity) applied at pin 15, the
circuit is a unipolar D/A converter. With an ac reference volt-
age or current (again of + or - polarity) the circuit provides
2-quadrant multiplication (digitally controlled attenuation).
The input/output relationship is shown in Table m.
R1 provides full scale trim capability [i.e.-load the DAC
register to 1111 1111 1111, adjust RI for VOUT = -VREF
(4095/4096)] . Alternatively, Full Scale can be adjusted by
omitting R1 and R2 and trimming the reference voltage
magnitude.
C1 phase compensation (10pF to 25pF) may be required for
stability when using high speed amplifiers. (C1 is used to can-
cel the pole formed by the DAC internal feedback resistance
and output capacitance at OUTl).
