AD7542BQ ,CMOS uP-COMPATIBLE 12-BIT DACFEATURES
Resolution: 12 Bits
Nonlinearity: d: 1/2LSB Tmin to Tmax
Low Gain Drift: 2ppm/°C ..
AD7542JN ,CMOS uP-COMPATIBLE 12-BIT DACANALOG
DEVICES
CMOS
pp-Compatible 12-Bit Mt
AD7542
FUNCTIONAL BLOCK DIAGRAM
VREF
AD7542JN ,CMOS uP-COMPATIBLE 12-BIT DACGENERAL DESCRIPTION
The AD7542 is a precision 12-bit CMOS multiplying DAC
designed for direct int ..
AD7542JN ,CMOS uP-COMPATIBLE 12-BIT DACapplications.
One Technology Way, P.0. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-47 ..
AD7542JP ,CMOS uP-COMPATIBLE 12-BIT DACFEATURES
Resolution: 12 Bits
Nonlinearity: d: 1/2LSB Tmin to Tmax
Low Gain Drift: 2ppm/°C ..
AD7542KN ,CMOS uP-COMPATIBLE 12-BIT DACGENERAL DESCRIPTION
The AD7542 is a precision 12-bit CMOS multiplying DAC
designed for direct int ..
ADG608BN ,3 V/5 V, 4/8 Channel High Performance Analog MultiplexersCHARACTERISTICSt 50 50 ns typ R = 300 Ω, C = 35 pF;TRANSITION L L75 90 75 100 ns max V = ±3.5 V, V ..
ADG608BR ,3 V/5 V, 4/8 Channel High Performance Analog MultiplexersAPPLICATIONSDECODER DECODERAutomatic Test EquipmentData Acquisition SystemsA0 A1 A2 EN A0 A1 ENComm ..
ADG608BRU ,3 V/5 V, 4/8 Channel High Performance Analog MultiplexersGENERAL DESCRIPTIONThe ADG608 and ADG609 are monolithic CMOS analog mul-PRODUCT HIGHLIGHTStiplexers ..
ADG608TRU ,3 V/5 V, 4/8 Channel High Performance Analog MultiplexersSpecifications subject to change without notice.–2– REV. AADG608/ADG6091SINGLE SUPPLY (V = +5 V 6 1 ..
ADG609BN ,3 V/5 V, 4/8 Channel High Performance Analog MultiplexersSPECIFICATIONS1(V = +5 V 6 10%, V = –5 V 6 10%, GND = 0 V, unless otherwise noted)DUAL SUPPLY DD SS ..
ADG609BR ,3 V/5 V, 4/8 Channel High Performance Analog MultiplexersCHARACTERISTICSt 80 80 ns typ R = 300 Ω, C = 35 pF;TRANSITION L L100 130 100 150 ns max V = 3.5 V/0 ..
AD7542BQ-AD7542JN-AD7542JP-AD7542KN-AD7542KP
CMOS uP-COMPATIBLE 12-BIT DAC
ANALOG
DEVICES
pp-Compatible 12-Bit Mt
AD7542
FEATURES
Resolution: 12 Bits
Nonlinearity: Le. 1/2LSB Tmin to Tm,
Low Gain Drift: 2ppmf'C typ, 5ppml°C max
Microprocessor Compatible
Full 4-Ouadrant Multiplication
Fast Interface Timing
Low Power Dissipation: 40mW max
Low Cost
Small Size: 16-pin DIP and 20-Terminal Surface
Mount Package
Latch Free (Protection Schottky Not Required)
GENERAL DESCRIPTION
The AD7542 is a precision 12-bit CMOS multiplying DAC
designed for direct interface to ' or 8-bit microprocessors.
The functional diagram shows the AD7542 to consist of three
4-bit data registers, a 12-bit DAC register, address decoding
logic and a 12-bit CMOS multiplying DAC. Data is loaded
into the data registers in three 4-bit bytes, and subsequently
transferred to the 12-bit DAC register. All data loading or
data transfer operations are identical to the WRITE cycle of a
static RAM. A clear input allows the DAC register to be easily
reset to all zeros when powering up the device.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
t6 NPR
IZ-BIT MU LTlPLWNG DAC
AD7542
EL" " 12.BtTDAC REGISTER
H-BVTE M.BYTE DGND
REGISTER
tgr ' ADDRESS
DECDDE
REGISTER REGISTER
Al " DO(LSB)
D3 (MSB)
The AD7542 is manufactured using an advanced thin-film on
monolithic CMOS fabrication process. Multiplying capability,
low power dissipation, +5V operation, small size (16-pin DIP
and 20 terminal surface mount packages) and easy pp interface
make the AD7542 ideal for many instrumentation, industrial
control and avionics applications.
One Technology Way, PO. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703 wa: 710/394-6577
Telex: 924491 Cable: ANALOG NORWOODMASS
AD7542 - SPECIFICATIONS th, = +51], her = +1011, me = Vom = Illl unless otherwise noted)
Limit At' Limit Atl
Limit At TU-- -40°C TA: - 55°C
Parameter TU = + 29'C to + 8!PC & + IZS'C Units Conditions/Comments
ACCURACY
Resolution 12 12 12 Bits
Relative Accuracy'
J, A, S Versions 11 11 11 LSB max
K. B, T Versions 11/2 11/2 11/2 LSB max
GK, GB, GT Versions 11/2 11/2 11/2 LSB max
Differential Nonlincarity2
J, A, S Versions tl tl 11 LSB mu All grades are guaranteed monotonic
K, B, T Versions 11 tl tl LSB max Tmin to Tmax
GK, GB, GT Versions tl tl tl ISB max
Gain Error2
J, K, A, B, S, T 23 i4 14 LSB max Using internal RFB only (gain error can be
GK, GB, GT 11 tl 12 LSB max trimmed to zero using circuits of Figure 4 & S)
Gain Temperature Coefficient
AGain/ATemperature S , 5 ppm/°C max Typical value is 2ppm/°C
Power Supply Rejection
AGain/AVDD 0.005 0.01 0.01 96 per % max VDD = +4.7SV to +5.2sv
Output Leakage Current
I001: 10 10 200 nA max DAC Register loaded with all Os
ksur2 10 10 200 nA max DAC Register loaded with all ls
DYNAMIC PERFORMANCE
Current Settling Times 2.0 2.0 2.0 us max To 1/2 LSB, OUTl load = 10012. DAC output
measured from falling edge of Wit.
Multiplying Feedthrough Error' 2.5 2.5 2.5 mV " max VREF = 110V, 10KHz sine wave
REFERENCE INPUT
Input Resistance 8/15/25 8/15/25 8/15/25 kn min/typhnax
ANALOG OUTPUTS
Output Ca acitance
(bun 75 75 75 pF mix DAC register loaded to 0000 0000 0000
COUTla 260 260 260 pF mu DACregisterloaded to 1111 1111 1111
tksvras 75 " 75 pF max DAC registerloaded to 1111 1111 1111
COUT23 260 260 260 pf max DAC register loaded to 0000 0000 0000
LOGIC INPUTS
vom (Logic HIGH Voltage) +2.4 +2.4 +2.4 V min
VINL (Logic LOW Voltage) +0.8 +0.8 +0.8 V max
ur/ 1 1 1 " max Vm = ov or VDD
Cm (Input Capacitance)a 8 8 8 pF max
Input Coding 12-Bit Unipolar Binary or 12-Bit Offset
Binary (See Figures 4 and 5). Data is
Loaded into Data Registers in 4-Bit Bytes.
SWITCHING CHARACTERISTICS' (See Figure l)
twn go 120 160 ns min twat WRITE pulse width
mm: o 10 10 ns min tAwtl; Address-to-WRITE hold time
tcwn 0 1o 10 ns min (CWH: Chip sclect-to-WRITE hold time
ttuae 200 200 250 ns min tCLR: Minimum CLEAR pulse width
ttnes 10 20 20 ns min tcws: Chip select-to-WRITE setup time
[AWS 40 40 40 ns min tAws= Address valid-to-WRITE setup time
IDS 60 100 100 ns min IDs: Data setup time
tDH 10 10 10 ns min ID": Data hold time
POWER SUPPLY
VDD (Supply Voltage) +5 " +5 V 15% for specified performance
IDD (Supply Current) 2.5 2,5 2.5 mA max Digital Inputs = Vom or VINL
'Tempcnnu! Ranges " follows: l, K, GK Versions; -40'C m +85''C
A, B, GB Versions; -4o°C to + 85'C
S, T, GT Versions; - 55"C to + 125°C
'see definitions on next page.
'Guaranteed but not tested.
'tami: inputs m MOS gates. Typical input current (+ 25'C) is less than.lnA.
'Sample med u + MT to ensure compliance.
Stmirrcations subject to change without node:
-2- REV. A
AD7542
ABSOLUTE MAXIMUM RATINGS'
(T, - + 25°C unless otherwise noted)
Vor, to AGND ................... 0V, + 7V
V01) to DGND ................... 0V, f 7V
AGND to DGND ................. VDD +0.3V
DGND to AGND ................. VDD + 0.3V
Digital Input Voltage to GND
VOUTI) VOUTZ to AGND
-0.3V, VDD +0.3V
-0.3V, VDD +0.3V
Vrwa; to AGND .....................
Vern, to AGND .....................
Power Dissipation (Package)
Plastic
To + 70°C
Derates above + 70°C by ........
Ceramic
To + 75°C
Derates above + 75°C by ........
Operating Temperature Range
Commercial (J, K, GK Versions) .....
Industrial (A, B, GB Versions) ......
Extended (S, T, GT Versions)
Storage Temperature
Lead Temperature (Soldering, 10secs)
..... 6mW/"C
b . . . 8.3mW/°C
- 40°C to + 85''C
- 40°C to + 85°C
-55T to + 125°C
- 65°C to + 150°C
+ 300°C
*COMMENTS: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are removed.
SD SENSITIVE DEVIC
ORDERING GUIDE
Temperature Relative Gain Package
Model' Range Accuracy Error Option'
AD754ZIN - 40'C to + 85°C , lLSB t SLSB N-16
AD7542KN - 40''C to + 85°C ' 1/2LSB t 3LSB N-16
AD7542GKN -40°C to + 85°C t l/2LSB t 1LSB N-16
AD75421P - 40°C to + 85°C t JLSB t 3LSB P-20A
AD7542KP -40'C to + 85'C t l/2LSB t SLSB P-ZOA
AD7542GKP - 40°C to + 85'C t 1/2LSB t lLSB P-20A
AD7542AQ - 40°C to + 85°C t ILSB t 3LSB Q-16
AD7542BQ - 40'C to + 85°C t 1/2LSB t 3LSB Q-16
AD7542GBQ - 40'C to + 85''C t l/2LSB t ILSB Q-16
AD7542SQ - 55°C to + 125°C t lLSB t SLSB Q-16
AD7S42TQ - 55°C to + 125°C t 1/2LSB t SLSB Q-16
AD7542GTQ - 55°C to + 125°C i 1/2LSB t ILSB Q-16
AD7542SE - 55°C to + 125°C t lLSB t BLSB E-20A
AD7542TE - 55°C to + 125°C , l/2LSB t 3LSB E-20A
AD7542GTE - 55°C to + 125°C t l/2LSB I lLSB E-20A
'To tttder MJL-STD-883 Class B processed parts, add M83B to part number.
'E = Ladies Ceramic Chip Cartier; N = Plastic DIP; P = Plastic Leaded Chip Carrier;
Q = Cerdip. For outline information set Package Information section.
PIN CONFIGURATIONS
0UT1 E
OUT2 E
AGND E
D3 (MSB) cr
DI LT.
Do (LSB) E
REV. A
AD7542
TOP VIEW
(Not to Scale)
AGND 4
D3 IMSB) 5
m OUTZ
F-- ADDRESS BUS VALID -----e
AO-AI w,
DATA BUS
NOTE: TIMING MEASUREMENT REFERENCE
LEVEL IS
y.Lr.t.'h_hL
Figure 1. AD7542 Timing Diagram
AD7542
TOP VIEW
(Not to Scale]
18 Voo
TOP VIEW
15 DGND (Not to Scale)
D0 (LSBI a
NC = NO CONNECT
NC = NO CONNECT
A07542
TERMINOLOGY
RELATIVE ACCURACY
Relative accuracy or endpoint nonlinearity is a measure of
the maximum deviation from a straight line passing through
the endpoints of the DAC transfer function. " is measured
after adjusting for zero and full scale and is expressed in % or
ppm of full scale range or (sub) multiples of lLSB.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the difference between the meas-
ured change and the ideal lLSB change between any two ad-
jacent codes. A specified differential nonlinearity of tlLSB
max over the operating temperature range insures monotonicity.
GAIN ERROR
Gain is defined as the ratio of the DAC's Full Scale output
to its reference input voltage. An ideal AD7542 would exhibit
a gain of -4095/4096. Gain error is adjustable using external
trims as shown in Figures 4 and 5.
OUTPUT LEAKAGE CURRENT
Current which appears at OUT] with the DAC register loaded
to all Os or at OUT2 with the DAC register loaded to all Is.
MULTIPLYING FEEDTHROUGH ERROR
AC error due to capacitive feedthrough from VREF terminal
to OUTl with DAC register loaded to all Os.
Table J. Pin Function Description (DIP Pin Numbers)
PIN MNEMONIC FUNCTION
1 OUTI DAC current output bus. Normally
terminated at op amp
virtual ground
2 OUT2 DAC current output bus. Normally
terminated at ground
3 AGND Analog Ground
4 D3 Data Input (MSB)
5 D2 Data Input
6 D1 Data Input
7 D0 Data Input (LSB)
8 tTg- Chip Select Input
9 W WRITE Input
10 A0 Address Bus Input
11 AI Address Bus Input
12 DGND Digital Ground
13 ttit- Clear Input
14 VDD +5V Supply Input
15 VREF Reference Input
16 RFB DAC Feedback Resistor
Analog Circuit Description
GENERAL CIRCUIT INFORMATION
The AD7542, a 12-bit multiplying D/A converter, consists of
a highly stable thin film R-2R ladder and twelve N-channel
current switches on a monolithic chip. Most applications
require the addition of only an output operational amplifier
and a voltage or current reference.
The simplified D/A circuit is shown in Figure 2. An inverted
R-2R ladder structure is used-that is, the binarily weighted
currents are switched between the OUTl and OUT2 bus lines,
thus maintaining a constant current in each ladder leg indepen-
dent of the switch state.
VREF -
DAC REGISTER
Figure 2. D/A Simplified Circuit Diagram
One of the current switches is shown in Figure 3. The input
resistance at VREF (Figure 2) is always equal to RLDR (RLDR
is the R/2R ladder characteristic resistance and is equal to
value "R"), Since Rm at the VREF pin is constant, the refer-
ence terminal can be driven by a reference voltage or a refer-
ence current, ac or dc, of positive or negative polarity. (If a
current source is used, a low temperature coefficient RFB is
recommended to define scale factor.)
TO LADDER
FROM C
INTERFACE
OUT2 0UT1
Figure 3. N-Channel Current Steering Switch
REV. A
Applying the AD7542
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 4 shows the analog circuit connections required for uni-
polar binary (2-quadrant multiplication) operation. The logic
inputs are omitted for clarity. With a dc reference voltage or
current (positive or negative polarity) applied at VREF, the
circuit is a unipolar D/A converter. With an ac reference volt-
age or current the circuit provides 2-quadrant multiplication
(digitally controlled attenuation). The input/output relation-
ship is shown in Table ll.
RI provides full scale trim capability [i.e.-load the DAC
register to 1111 1111 1111, adjust RI for VOUT = -VREF
(4095/4096)] . Alternatively, Full Scale can be adjusted by
omitting R1 and R2 and trimming the reference voltage
magnitude.
C1 phase compensation (10 to 33pF) may be required for
stability when using high speed amplifiers. (Cl is used to cancel
the pole formed by the DAC internal feedback resistance and
output capacitance at OUTl).
Amplifier A1 should be selected or trimmed to provide
Vos < 10% of the voltage resolution at VOUT' Additionally,
the amplifier should exhibit a bias current which is low over
the temperature range of interest (bias current causes output
offset at VOUT equal to 13 times the DAC feedback resistance,
nominally 15kf2). The AD711K is a high-speed implanted
FET-input op amp with low, factory-trimmed Vos.
210V Von
VREF vav
-0 V001
12 3 OUTZ
ADTHX (SEE TEXT)
1 LOGIC INPUTS OMIYTED FOR CLARITY. MP PIN NUMBERS SHOWN,
2 SEE APPLICATION HINT NO '
Figure 4. Unipolar Binary Operation (2-0uadrant
Multiplication)
Table II. Unipolar Binary Code Table for Circuit of Figure 4
BINARY NUMBER IN
DAC REGISTER ANALOG OUTPUT, Vovr
MSB LSB
111111111111 -vRErt(4-4l'-1i')'
1000 0000 0000 -vREr(42-t-4d-)= -1/2VREF
0000 0000 0001 -VREF(d-sm)
0000 0000 0000 ov
REV. A
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
Figure 5 and Table III illustrate the circuitry and code relation-
ship for bipolar operation. With a dc reference (positive or
negative polarity) the circuit provides offset binary operation.
With an ac reference, the circuit provides full 4-quadrant
multiplication.
With the DAC register loaded to 1000 0000 0000, adjust R1
for VOUT = 0V (alternatively, one can omit RI and R2 and
adjust the ratio of R3 to R4 for VOUT = OV), Full scale
trimming can be accomplished by adjusting the amplitude of
VREF or by varying the value of R5.
As in unipolar operation, A1 must be chosen for low Vos and
low IB. R3, R4 and R5 must be selected for matching and
tracking. Mismatch of R3 to R4 causes both offset and Full
Scale error. Mismatch of R5 to R4 or R3 causes Full Scale
error. C1 phase compensation (10pF to 25pF) may be required
for stability.
, mv v00
VREF HN
" F"t-,,-7..T3,,,:- iiridr R5
C1 33pF 20k
15 14 16 OUTT R3
1 - 10k
oun A1
AD71'IK
(SEE TEXT]
AD75421
1 LOGIC INPUTS OMITTED FOR CLARITY, DIP PIN NUMBERS SHOWN.
2 SEE APPLICATION HINT NO, 4
Figure 5. Bipolar Operation (4-0uadrant Multiplication)
Table III. Bipolar Code Table for Offset Binary Circuit of
Figure 5
BINARY NUMBER IN
DAC REGISTER ANALOG OUTPUT, VoUT
MSB LSB
111111111111 +VREF(§8:;)
1000 0000 0001 -vREr(-2-o14-s-)
1000 0000 0000 0V
0111 1111 1111 -vmir(2--o14-e)
0000 0000 0000 ‘VREF(§g:§)
