AD7541AJN ,CMOS 12-Bit Monolithic Multiplying DACGENERAL DESCRIPTIONBIT 1 (MSB) BIT 2 BIT 3 BIT 12 (LSB)The Analog Devices AD7541A is a low cost, hi ..
AD7541AJP ,CMOS 12-Bit Monolithic Multiplying DACSPECIFICATIONSDD REFT =T =A A1Parameter Version +258CT T Units Test Conditions/CommentsMIN, MAXACCU ..
AD7541AKN ,CMOS 12-Bit Monolithic Multiplying DACSpecifications subject to change without notice.–2– REV. BAD7541AABSOLUTE MAXIMUM RATINGS* Operatin ..
AD7541AKP ,CMOS 12-Bit Monolithic Multiplying DACspecifications over the AD7541:endpoint linearity with several new high performance grades.1. Gain ..
AD7541AKR ,CMOS 12-Bit Monolithic Multiplying DACCMOSa12-Bit Monolithic Multiplying DACAD7541A
AD7541AKR ,CMOS 12-Bit Monolithic Multiplying DACSpecifications subject to change without notice.–2– REV. BAD7541AABSOLUTE MAXIMUM RATINGS* Operatin ..
ADG512BN ,LC2MOS Precision 5 V/3 V Quad SPST SwitchesFEATURES+3 V, +5 V or 65 V Power SuppliesUltralow Power Dissipation (<0.5 mW)S1 S1 S1Low Leakage (< ..
ADG512BR ,LC2MOS Precision 5 V/3 V Quad SPST Switchesfeatures make thetion. This allows multiple outputs to be tied together forADG511, ADG512 and ADG51 ..
ADG512TQ ,LC2MOS Precision 5 V/3 V Quad SPST SwitchesSPECIFICATIONSDual Supply (V = +5 V 6 10%, V = –5 V 6 10%, GND = 0 V, unless otherwise noted)DD SSB ..
ADG513BR ,LC2MOS Precision 5 V/3 V Quad SPST SwitchesCHARACTERISTICSt 250 250 ns typ R = 300 W , C = 35 pF;ON L L500 500 ns max V = +2 V; Test Circuit 4 ..
ADG513BR ,LC2MOS Precision 5 V/3 V Quad SPST SwitchesSPECIFICATIONSDual Supply (V = +5 V 6 10%, V = –5 V 6 10%, GND = 0 V, unless otherwise noted)DD SSB ..
ADG526ABQ ,CMOS LATCHED 8/16 CHANNEL ANALOG MULTIPLEXERSANALOG
CMOS
DEVICES Latched 8/ 16 Channel Analog Multiplexers
AM52M/li0tyifl7h
AD7541AAQ-AD7541ABQ-AD7541AJN-AD7541AJP-AD7541AKN-AD7541AKP-AD7541AKR-AD7541ATQ
CMOS 12-Bit Monolithic Multiplying DAC
REV.B
CMOS
12-Bit Monolithic Multiplying DAC
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Improved Version of AD7541
Full Four-Quadrant Multiplication
12-Bit Linearity (Endpoint)
All Parts Guaranteed Monotonic
TTL/CMOS Compatible
Low Cost
Protection Schottky Diodes Not Required
Low Logic Input Leakage
GENERAL DESCRIPTIONThe Analog Devices AD7541A is a low cost, high performance
12-bit monolithic multiplying digital-to-analog converter. It is
fabricated using advanced, low noise, thin film on CMOS
technology and is available in a standard 18-lead DIP and in
20-terminal surface mount packages.
The AD7541A is functionally and pin compatible with the in-
dustry standard AD7541 device and offers improved specifica-
tions and performance. The improved design ensures that the
device is latch-up free so no output protection Schottky diodes
are required.
This new device uses laser wafer trimming to provide full 12-bit
endpoint linearity with several new high performance grades.
PRODUCT HIGHLIGHTS
Compatibility:The AD7541A can be used as a direct replace-
ment for any AD7541-type device. As with the Analog Devices
AD7541, the digital inputs are TTL/CMOS compatible and
have been designed to have a ±1μA maximum input current
requirement so as not to load the driving circuitry.
Improvements:The AD7541A offers the following improved
specifications over the AD7541:Gain Error for all grades has been reduced with premium
grade versions having a maximum gain error of ±3LSB.Gain Error temperature coefficient has been reduced toppm/°C typical and 5ppm/°C maximum.Digital-to-analog charge injection energy for this new device
is typically 20% less than the standard AD7541 part.Latch-up proof.Improvements in laser wafer trimming provides 1/2LSB max
differential nonlinearity for top grade devices over the operat-
ing temperature range (vs. 1LSB on older 7541 types).All grades are guaranteed monotonic to 12 bits over the
operating temperature range.
ORDERING GUIDE1NOTESAnalog Devices reserves the right to ship either ceramic (D-18) or cerdip (Q-18)
hermetic packages.To order MIL-STD-883, Class B process parts, add /883B to part number. Contact
local sales office for military data sheet.E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = Small Outline IC.
AD7541A–SPECIFICATIONSPOWER SUPPLY
AC PERFORMANCE CHARACTERISTICS
These Characteristics are included for Design Guidance only and are not subject to test. VDD = +15 V, VIN = +10 V except where noted,
OUT1 = 0UT2 = GND = 0 V, Output Amp is AD544 except where noted.MULTIPLYING FEEDTHROUGH ERROR
(VDD = +15 V, VREF = +10 V; OUT 1 = OUT 2 = GND = 0 V unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±25 V
Digital Input Voltage to GND . . . . . . . . –0.3 V, VDD + 0.3 V
OUT 1, OUT 2 to GND . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Power Dissipation (Any Package)
To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
TERMINOLOGY
RELATIVE ACCURACYRelative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is expressed in % of full-
scale range or (sub)multiples of 1LSB.
DIFFERENTIAL NONLINEARITYDifferential nonlinearity is the difference between the measured
change and the ideal lLSB change between any two adjacent
codes. A specified differential nonlinearity of ±1LSB max over
the operating temperature range insures monotonicity.
GAIN ERRORGain error is a measure of the output error between an ideal
DAC and the actual device output. For the AD7541A, ideal
maximum output is
4096 (VREF ).
Gain error is adjustable to zero using external trims as shown in
Figures 4, 5 and 6.
OUTPUT LEAKAGE CURRENTCurrent which appears at OUTI with the DAC loaded to all 0s
or at OUT2 with the DAC loaded to all 1s.
MULTIPLYING FEEDTHROUGH ERRORAC error due to capacitive feedthrough from VREF terminal to
OUT1 with DAC loaded to all 0s.
OUTPUT CURRENT SETTLING TIMETime required for the output function of the DAC to settle to
within 1/2 LSB for a given digital input stimulus, i.e., 0 to full
scale.
PROPAGATION DELAYThis is a measure of the internal delay of the circuit and is mea-
sured from the time a digital input changes to the point at which
the analog output at OUT1 reaches 90% of its final value.
DIGITAL-TO-ANALOG CHARGE INJECTION (QDA)This is a measure of the amount of charge injected from the
digital inputs to the analog outputs when the inputs change
state. It is usually specified as the area of the glitch in nV secs
and is measured with VREF = GND and a Model 50K as the
output op amp, C1 (phase compensation) = 0 pF.
Operating Temperature Range
Commercial (J, K Versions) . . . . . . . . . . . . . 0°C to +70°C
Industrial (A, B Versions) . . . . . . . . . . . . . –25°C to +85°C
Extended (S, T Versions) . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7541A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
DIP/SOIC LCCC PLCC19123
OUT 2OUT 1NC
REF
GND
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
VDD
BIT 12 (LSB)
BIT 11
BIT 10
BIT 9GND
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
VDD
BIT 12 (LSB)
BIT 11
BIT 10
BIT 9
OUT 2OUT 1NCR
REF
AD7541A
GENERAL CIRCUIT INFORMATIONThe simplified D/A circuit is shown in Figure 1. An inverted
R-2R ladder structure is used—that is, the binarily weighted
currents are switched between the OUT1 and OUT2 bus lines,
thus maintaining a constant current in each ladder leg indepen-
dent of the switch state.
10kΩ10kΩ10kΩS2S3S12
VREF
OUT2
OUT1
RFEEDBACK
BIT 12 (LSB)BIT 3BIT 2BIT 1 (MSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
LOGIC: A SWITCH IS CLOSED TO IOUT1 FOR
ITS DIGITAL INPUT IN A "HIGH" STATE.Figure 1.Functional Diagram (Inputs HIGH)
The input resistance at VREF (Figure 1) is always equal to RLDR
(RLDR is the R/2R ladder characteristic resistance and is equal to
value “R”). Since RIN at the VREF pin is constant, the reference
terminal can be driven by a reference voltage or a reference
current, ac or dc, of positive or negative polarity. (If a current
source is used, a low temperature coefficient external RFB is
recommended to define scale factor.)
EQUIVALENT CIRCUIT ANALYSISThe equivalent circuits for all digital inputs LOW and all digital
inputs HIGH are shown in Figures 2 and 3. In Figure 2 with all
digital inputs LOW, the reference current is switched to OUT2.
The current source ILEAKAGE is composed of surface and junc-
tion leakages to the substrate, while the I/4096 current source
represents a constant 1-bit current drain through the termina-
tion resistor on the R-2R ladder. The ON capacitance of the
output N-channel switch is 200pF, as shown on the OUT2
terminal. The OFF switch capacitance is 70pF, as shown on
the OUT1 terminal. Analysis of the circuit for all digital inputs
HIGH, as shown in Figure 3 is similar to Figure 2; however, the
ON switches are now on terminal OUT1, hence the 200pF at
that terminal.
15kΩ
VREF
RFB
OUT1
OUT2Figure 2.DAC Equivalent Circuit All Digital Inputs LOW
VREF
RFB
OUT2
OUT1
APPLICATIONS
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)Figure 4 shows the analog circuit connections required for uni-
polar binary (2-quadrant multiplication) operation. With a dc
reference voltage or current (positive or negative polarity) ap-
plied at Pin 17, the circuit is a unipolar D/A converter. With an
ac reference voltage or current, the circuit provides 2-quadrant
multiplication (digitally controlled attenuation). The input/
output relationship is shown in Table II.
R1 provides full-scale trim capability [i.e., load the DAC register
to 1111 1111 1111, adjust R1 for VOUT = –VREF (4095/4096)].
Alternatively, Full Scale can be adjusted by omitting R1 and R2
and trimming the reference voltage magnitude.
C1 phase compensation (10pF to 25pF) may be required for
stability when using high speed amplifiers. (C1 is used to cancel
the pole formed by the DAC internal feedback resistance and
output capacitance at OUT1).
Amplifier A1 should be selected or trimmed to provide VOS ≤
10% of the voltage resolution at VOUT. Additionally, the ampli-
fier should exhibit a bias current which is low over the tempera-
ture range of interest (bias current causes output offset at VOUT
equal to IB times the DAC feedback resistance, nominally 11kΩ).
The AD544L is a high speed implanted FET input op amp with
low factory-trimmed VOS.
Figure 4.Unipolar Binary Operation
Table I.Recommended Trim Resistor Values vs. Grades
Table II.Unipolar Binary Code Table for Circuit of Figure 4
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)Figure 5 and Table III illustrate the circuitry and code relation-
ship for bipolar operation. With a dc reference (positive or nega-
tive polarity) the circuit provides offset binary operation. With
an ac reference the circuit provides full 4-quadrant multiplication.
With the DAC loaded to 1000 0000 0000, adjust R1 for
VOUT = 0V (alternatively, one can omit R1 and R2 and adjust
the ratio of R3 to R4 for VOUT = 0 V). Full-scale trimming can
be accomplished by adjusting the amplitude of VREF or by vary-
ing the value of R5.
As in unipolar operation, A1 must be chosen for low VOS and
low IB. R3, R4 and R5 must be selected for matching and track-
ing. Mismatch of 2R3 to R4 causes both offset and full-scale
error. Mismatch of R5 to R4 or 2R3 causes full-scale error. C1
phase compensation (10pF to 50pF) may be required for sta-
bility, depending on amplifier used.
VIN
BIT 1 – BIT 12DIGITAL
GROUND
ANALOG
COMMON
AD544J
*FOR VALUES OF R1 AND R2
SEE TABLE 1.Figure 5.Bipolar Operation (4-Quadrant Multiplication)
Table III.Bipolar Code Table for Offset Binary Circuit of
Figure 5Figure 6 and Table IV show an alternative method of achieving
bipolar output. The circuit operates with sign plus magnitude
code and has the advantage of giving 12-bit resolution in each
quadrant, compared with 11-bit resolution per quadrant for the
circuit of Figure 5. The AD7592 is a fully protected CMOS
changeover switch with data latches. R4 and R5 should match
each other to 0.01% to maintain the accuracy of the D/A con-
verter. Mismatch between R4 and R5 introduces a gain error.
Figure 6.12-Bit Plus Sign Magnitude Operation
Table IV.12-Bit Plus Sign Magnitude Code Table for Circuit
of Figure 6Note: Sign bit of “0” connects R3 to GND.
AD7541A
APPLICATIONS HINTS
Output Offset: CMOS D/A converters exhibit a code-dependentoutput resistance which in turn can cause a code-dependent
error voltage at the output of the amplifier. The maximum am-
plitude of this offset, which adds to the D/A converter nonlin-
earity, is 0.67 VOS where VOS is the amplifier input offset
voltage. To maintain monotonic operation it is recommended
that VOS be no greater than (25 × 10–6) (VREF) over the tempera-
ture range of operation. Suitable op amps are AD517L and
AD544L. The AD517L is best suited for fixed reference appli-
cations with low bandwidth requirements: it has extremely low
offset (50μV) and in most applications will not require an offset
trim. The AD544L has a much wider bandwidth and higher
slew rate and is recommended for multiplying and other appli-
cations requiring fast settling. An offset trim on the AD544L
may be necessary in some circuits.
Digital Glitches: One cause of digital glitches is capacitivecoupling from the digital lines to the OUT1 and OUT2 termi-
nals. This should be minimized by screening the analog pins of
the AD7541A (Pins 1, 2, 17, 18) from the digital pins by a
ground track run between Pins 2 and 3 and between Pins 16
and 17 of the AD7541A. Note how the analog pins are at one
end of the package and separated from the digital pins by VDD
and GND to aid screening at the board level. On-chip capacitive
coupling can also give rise to crosstalk from the digital-to-analog
sections of the AD7541A, particularly in circuits with high cur-
rents and fast rise and fall times.
Temperature Coefficients: The gain temperature coefficientof the AD7541A has a maximum value of 5ppm/°C and a typi-
cal value of 2ppm/°C. This corresponds to worst case gain shifts
of 2LSBs and 0.8LSBs, respectively, over a 100°C temperature
range. When trim resistors R1 and R2 are used to adjust full-
scale range, the temperature coefficient of R1 and R2 should
also be taken into account. The reader is referred to Analog
Devices Application Note “Gain Error and Gain Temperature
Coefficient of CMOS Multiplying DACs,” Publication Number
E630c-5-3/86.
SINGLE SUPPLY OPERATIONFigure 7 shows the AD7541A connected in a voltage switching
mode. OUT1 is connected to the reference voltage and OUT2
is connected to GND. The D/A converter output voltage is
available at the VREF pin (Pin 17) and has a constant output
impedance equal to RLDR. The feedback resistor RFB is not used
in this circuit.
VOUT = 0V TO +10V
SYSTEM
GROUND
VDD = +15V
VREF
+2.5V
VOUT ±VREF D (1 +R2/R1) WHERE 0 ≤ D ≤ 1
i.e., D IS A FRACTIONAL REPRESENTATION OF THE DIGITAL INPUTFigure 7.Single Supply Operation Using Voltage Switch-
ing Mode
The reference voltage must always be positive. If OUT1 goes
more than 0.3V less than GND, an internal diode will be turned
on and a heavy current may flow causing device damage (the
AD7541A is, however, protected from the SCR latch-up
phenomenon prevalent in many CMOS devices). Suitable refer-
ences include the AD580 and AD584.
The loading on the reference voltage source is code-dependent
and the response time of the circuit is often determined by the
behavior of the reference voltage with changing load conditions.
To maintain linearity, the voltage at OUT1 should remain within
2.5V of GND, for a VDD of 15V. If VDD is reduced from 15V
or the reference voltage at OUT1 increased to more than 2.5V,
the differential nonlinearity of the DAC will increase and the
linearity of the DAC will be degraded.
SUPPLEMENTAL APPLICATION MATERIALFor further information on CMOS multiplying D/A converters,
the reader is referred to the following texts:
CMOS DAC Application Guide, Publication Number
G872b-8-1/89 available from Analog Devices.
Gain Error and Gain Temperature Coefficient of CMOS
Multiplying DACs Application Note, Publication Number
E630c-5-3/86 available from Analog Devices.
Analog-Digital Conversion Handbook—available from Analog
Devices.
