AD7537 ,LCcharacteristics are included for Design Guidance only and are not subject to test.(V = +12 V to +15 ..
AD7537CQ ,LC2MOS (8+4) Loading Dual 12-Bit DACfeatures on the AD7537 include an asynchronous CLRare not practical using two discrete DACs are now ..
AD7537CQ ,LC2MOS (8+4) Loading Dual 12-Bit DACGENERAL DESCRIPTIONThe AD7537 contains two 12-bit current output DACs on onemonolithic chip. A sepa ..
AD7537JN ,LC2MOS (8+4) Loading Dual 12-Bit DACspecifications T to T unless otherwise noted.)OUTB MIN MAXJ, A K, B L, C S T UParameter Versions Ve ..
AD7537JP ,LC2MOS (8+4) Loading Dual 12-Bit DACGENERAL DESCRIPTIONThe AD7537 contains two 12-bit current output DACs on onemonolithic chip. A sepa ..
AD7537KN ,LC2MOS (8+4) Loading Dual 12-Bit DACspecifications.DDS, T, U Versions: –55°C to +125°C4Pin 12 (DGND) on ceramic DIPs is connected to li ..
ADG508ATQ ,CMOS 4/8 CHAANNEL ANALOG MULTIPLEXERSGENERAL DESCRIPTION
The ADG508A and ADG509A are CMOS monolithic analog
multiplexers with 8 chan ..
ADG508FBN ,4/8 Channel Fault-Protected Analog MultiplexersGENERAL DESCRIPTIONThe ADG508F, ADG509F and ADG528F are CMOS analog3. Low RON.multiplexers, the AD ..
ADG508FBNZ , 8-Channel/4-Channel Fault-Protected Analog Multiplexers
ADG508FBRN ,4/8 Channel Fault-Protected Analog MultiplexersGENERAL DESCRIPTIONThe ADG508F, ADG509F and ADG528F are CMOS analog3. Low RON.multiplexers, the AD ..
ADG508FBRNZ , 8-Channel/4-Channel Fault-Protected Analog Multiplexers
ADG508FBRW ,4/8 Channel Fault-Protected Analog MultiplexersSPECIFICATIONSDual Supply (V = +15 V 6 10%, V = –15 V 6 10%, GND = 0 V, unless otherwise noted)DD S ..
AD7537
LC
FUNCTIONAL BLOCK DIAGRAMREV.0
LC2MOS
(8+4) Loading Dual 12-Bit DAC
FEATURES
Two 12-Bit DACs in One Package
DAC Ladder Resistance Matching: 0.5%
Space Saving Skinny DIP and Surface Mount Packages
4-Quadrant Multiplication
Low Gain Error (1 LSB max Over Temperature)
Byte Loading Structure
Fast Interface Timing
APPLICATIONS
Automatic Test Equipment
Programmable Filters
Audio Applications
Synchro Applications
Process Control
GENERAL DESCRIPTIONThe AD7537 contains two 12-bit current output DACs on one
monolithic chip. A separate reference input is provided for each
DAC. The dual DAC saves valuable board space, and the
monolithic construction ensures excellent thermal tracking.
Both DACs are guaranteed 12-bit monotonic over the full tem-
perature range.
The AD7537 has a 2-byte (8 LSBs, 4 MSBs) loading structure.
It is designed for right-justified data format. The control signals
for register loading are A0, A1, CS, WR and UPD. Data is
loaded to the input registers when CS and WR are low. To
transfer this data to the DAC registers, UPD must be taken low
with WR.
Added features on the AD7537 include an asynchronous CLR
line which is very useful in calibration routines. When this is
taken low, all registers are cleared. The double buffering of the
data inputs allows simultaneous update of both DACs. Also,
each DAC has a separate AGND line. This increases the device
versatility; for instance one DAC may be operated with
AGND biased while the other is connected in the standard
configuration.
The AD7537 is manufactured using the Linear Compatible
CMOS (LC2MOS) process. It is speed compatible with most
microprocessors and accepts TTL, 74HC and 5 V CMOS logic
level inputs.
PRODUCT HIGHLIGHTS1. DAC to DAC Matching:
Since both DACs are fabricated on the same chip, precise
matching and tracking is inherent. Many applications which
are not practical using two discrete DACs are now possible.
Typical matching: 0.5%.
2. Small Package Size:
The AD7537 is packaged in small 24-pin 0.3" DIPs and in
28-terminal surface mount packages.
3. Wide Power Supply Tolerance:
The device operates on a +12 V to +15 V VDD, with ±10%
tolerance on this nominal figure. All specifications are
guaranteed over this range.
AD7537–SPECIFICATIONS
(VDD = +12 V to +15 V, 610%, VREFA = VREFB = 10 V; IOUTA = AGND = 0 V,
IOUTB = AGNDB = 0 V. All specifications TMIN to TMAX unless otherwise noted.)
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance only and are not subject to test.
(VDD = +12 V to +15 V; VREFA = VREFB = +10 V; IOUTA = AGNDA = 0 V, IOUTB = AGNDB = 0 V. Output Amplifiers are AD644 except where noted.)Output Current Settling Time
AC Feedthrough
Power Supply Rejection
Output Capacitance
Channel-to-Channel Isolation
Output Noise Voltage Density
AD7537
PIN FUNCTION DESCRIPTION (DIP)3RFBA
4VREFA
LCCCDIP
PLCC
PIN CONFIGURATIONS
CIRCUIT INFORMATION – D/A SECTIONThe AD7537 contains two identical 12-bit multiplying D/A
current flowing in each ladder leg is constant, irrespective of
switch state. The feedback resistor RFBA is used with an op amp
(see Figures 4 and 5) to convert the current flowing in IOUTA to
a voltage output.
Figure 2.Simplified Circuit Diagram for DAC A
EQUIVALENT CIRCUIT ANALYSISFigure 3 shows the equivalent circuit for one of the D/A con-
verters (DAC A) in the AD7537. A similar equivalent circuit
can be drawn for DAC B.
COUT is the output capacitance due to the N-channel switches
and varies from about 50 pF to 150 pF with digital input code.
The current source ILKG is composed of surface and junction
leakages and approximately doubles every 10°C. R0 is the
equivalent output resistance of the device which varies with
input code.
DIGITAL CIRCUIT INFORMATIONThe digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA.
Table I. AD7537 Truth TableNOTES: X = Don’t care
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)Figure 4 shows the circuit diagram for unipolar binary opera-
tion. With an ac input, the circuit performs 2-quadrant multipli-
cation. The code table for Figure 4 is given in Table II.
Operational amplifiers A1 and A2 can be in a single package
(AD644, AD712) or separate packages (AD544, AD711,
AD OP27). Capacitors C1 and C2 provide phase compensation
to help prevent overshoot and ringing when high-speed op amps
are used.
For zero offset adjustment, the appropriate DAC register is
loaded with all 0s and amplifier offset adjusted so that VOUTA or
VOUTB is 0 V. Full-scale trimming is accomplished by loading
the DAC register with all 1s and adjusting R1 (R3) so that
VOUTA (VOUTB) = –VIN (4095/4096). For high temperature op-
eration, resistors and potentiometers should have a low Tem-
perature Coefficient. In many applications, because of the
excellent Gain T.C. and Gain Error specifications of the
AD7537, Gain Error trimming is not necessary. In fixed refer-
ence applications, full scale can also be adjusted by omitting R1,
R2, R3, R4 and trimming the reference voltage magnitude.
Figure 4.AD7537 Unipolar Binary Operation
Table II.Unipolar Binary Code Table for
Circuit of Figure 4
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)The recommended circuit diagram for bipolar operation is
shown in Figure 5. Offset binary coding is used.
With the appropriate DAC register loaded to 1000 0000 0000,
adjust R1 (R3) so that VOUTA (VOUTB) = 0 V. Alternatively, R1,
R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, 10)
varied for VOUTA (VOUTB) = 0 V. Full-scale trimming can be ac-
complished by adjusting the amplitude of VIN or by varying the
value of R5 (R8).
If R1, R2 (R3, R4) are not used, then resistors R5, R6, R7 (R8,
R9, R10) should be ratio matched to 0.01% to ensure gain error
performance to the data sheet specification. When operating
over a wide temperature range, it is important that the resistors
be of the same type so that their temperature coefficients match.
The code table for Figure 5 is given in Table III.
Figure 5.Bipolar Operation (Offset Binary Coding)
Table III.Bipolar Code Table for Offset Binary
Circuit of Figure 5
