AD7536JN ,LC2MOS 14-BIT uP-COMPATIBLE DACCHARACTERISTICS
(h, = +11.4ll to +15.75ll,llar = + lihl, b, = vas = thl, Ilss = IN OR - 300mV,
..
AD7536JP ,LC2MOS 14-BIT uP-COMPATIBLE DACcharacteristics also ensure exceptional
stability of linearity and gain error over the full temper ..
AD7536KN ,LC2MOS 14-BIT uP-COMPATIBLE DACspecifications u, to u, unless otherwise stated. See Figure ti
for Suggested Specification Circuit ..
AD7537 ,LCcharacteristics are included for Design Guidance only and are not subject to test.(V = +12 V to +15 ..
AD7537CQ ,LC2MOS (8+4) Loading Dual 12-Bit DACfeatures on the AD7537 include an asynchronous CLRare not practical using two discrete DACs are now ..
AD7537CQ ,LC2MOS (8+4) Loading Dual 12-Bit DACGENERAL DESCRIPTIONThe AD7537 contains two 12-bit current output DACs on onemonolithic chip. A sepa ..
ADG508AKR ,CMOS 4/8 CHAANNEL ANALOG MULTIPLEXERSSpecifications
Wide Supply Ranges (10.8V to 16.5V)
Extended Plastic Temperature Range
( --40oC t ..
ADG508ATQ ,CMOS 4/8 CHAANNEL ANALOG MULTIPLEXERSGENERAL DESCRIPTION
The ADG508A and ADG509A are CMOS monolithic analog
multiplexers with 8 chan ..
ADG508FBN ,4/8 Channel Fault-Protected Analog MultiplexersGENERAL DESCRIPTIONThe ADG508F, ADG509F and ADG528F are CMOS analog3. Low RON.multiplexers, the AD ..
ADG508FBNZ , 8-Channel/4-Channel Fault-Protected Analog Multiplexers
ADG508FBRN ,4/8 Channel Fault-Protected Analog MultiplexersGENERAL DESCRIPTIONThe ADG508F, ADG509F and ADG528F are CMOS analog3. Low RON.multiplexers, the AD ..
ADG508FBRNZ , 8-Channel/4-Channel Fault-Protected Analog Multiplexers
AD7536JN-AD7536JP-AD7536KN
LC2MOS 14-BIT uP-COMPATIBLE DAC
ANALOG
DEVICES
M-Bit MP Compatible Mil
AD7536
FEATURES
Full 4-Quadrant Multiplication without External
Resistors
All Grades 14-Bit Monotonic over the Full Temperature
Low Output Leakage (\20nA) over the Full
Temperature Range
Low Gain Temperature Coefficient, 2ppm/°C
APPLICATIONS
Control and Measurement in High Temperature
Environments
Digital Audio
Precision Servo Control
All Microprocessor Based Control Systems
GENERAL DESCRIPTION
The AD7536 is a l4-bit monolithic CMOS TYA converter. The
part is laser trimmed and specified as a dedicated bipolar DAC.
The resistors needed for 4-quadrant multiplication are contained
on the chip. Thus, the user requires only the AD7536, a voltage
reference and two op-amps for bipolar operation. The AD7536
has the same low leakage configuration (patent pending) as the
other members of the 14-bit CMOS DAC family. The excellent
output leakage current characteristics also ensure exceptional
stability of linearity and gain error over the full temperature
range.
The device is speed compatible with most microprocessors and
accepts TTL or 5V CMOS logic level inputs. There is standard
Chip Select and Memory Write logic for easy interfacing. The
AD7536 has full protection against CMOS "latch-up" phenomena
and does not require the use of external Schottky diodes or the
die of a FET Input op-amp.
PIN CONFIGURATIONS
DIP LCCC
lmv ' VW
C AGNDS
AGNDS 5 CSLSB AGND,
AGNDF s LDAC norm
AD7536
DGND , AD7536 csmsa (MSBI DB13 FOP VIEW
Tov VIEW DE” {Not to Scalel
imssi man s INot to Sealer DB0 \LSBV
mm 9 Dill
Dibll 10 ms;
DB10 ll DB 12 13 u th 16 n 18
DB9112 DB4 'g's8raa's'ti,'kiliil
-i th D G a D a th
DEE I3
DB 18
Information furnished by Analog Devices is believed to be accurate
and reliable. However, no responsibility is assumed by Analog Devices
for its use; nor for any infringements of patents or other rights of third
parties which may result from its use, No license is granted by implica-
tion or otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
VINV RINT VREF )it
A.h f\ A
\23/ , 2 26
V, Rss,
DAC LADDER IOUT
AD7536 "
DAC REGISTER Q W:
1;; lil'
INPUT INPUT
REGISTER I REGISTER
0313 DB0 DGND Vss
PRODUCT HIGHLIGHTS
l. Bipolar Operation
The AD7536 gives the user 4-Quadrant Multiplication without
any external resistors.
2. Guaranteed Monotonicity
14-bit monotonicity is guaranteed over the full temperature
range for all grades.
3. Low Output Leakage
The device has excellent output leakage current characteristics
at all temperatures.
DB0 ALSE
AGNDS WR
AGNDF CSLSB
DGND AD7536 LDAC
TOP VIEW csmsa
(MSBI DB13 (Nor tro Scale!
0312 a DBDllSB‘
Dan m DBI
One Technology Way; Norwood, Massachusetts 02062-9106
Tel: 617/329-4700 TWX: 710/394-6577
West Coast Mid-West Texas
714/641 -9391 312/350-9399 21 4/231 -5094
(Von = +11.4ll to +15.75V2, her = +lilll, +me = mesI = illl, Ilss = 1
1107536 - SPECIFI iyrnimsl 1:322:13: 21131131315 tlnrtutit03)Ux unless otherwise stated. See Figure 5
AD7S36]N AD7536KN
Parameter AD7536AQ AD7536BQ AD7536SQ AD7536TQ Units Test Comiitions/Comments
ACCURACY
Resolution 14 14 14 14 Bits ILSB = ZVREp/Z"
Relative Accuracy E 2 E 1 ' 2 t 1 LSB max All grades guaranteed monotonic
Differential Nonlinearity : l : I _ l : 1 LSB max over temperature.
Gain Error : 16 t 8 : 16 t 8 LSB max Measured using internal Rm and
includes effects of leakage
current and gain T.C.
Offset Error t 4 t 4 t 4 t 4 LSB max Errordue to mismatch between RH; and
offset resistor. lt also includes leakage
current to I, 'UT and is measured when
DAC is loaded with all O's.
Gain Temperature Coefficient',
AGain/ATemperature I S t 5 t 5 t 5 ppmf'C max Typical Value is2ppmf'C
Offset Temperature Coemciend
AOffset/hTemperature t 5 t 2.5 t 5 t 2.5 ppm/N', max Typical Value is lppm/''C
INPUT RESISTANCES
VRFII Input Resistance, Pin 2 3 3 3 , kn min Typical Input Resistance = 6kil
13 13 13 l 3 kt 1 max
' Input Resistance, Pin 28 2 2 2 2 kn min Typical Input Resistance 7 4kit
8 8 8 8 " 1 max
DIGITAL INPUTS
VIN(lnput HighVoltage) 2.4 2.4 2.4 2.4 Vmin
Vu (Input Low Voltage) 08 0 8 0.8 0.8 V max
Irs (Input Current)
925°C :1 tl I tl pAmax VIN 0Voer)
Tm,,, to'l‘m. : 10 t 10 10 r, 10 WA max
(1m (Input Capacitance)' 7 7 7 pF max
POWER SUPPLY
VnhRange 11.4/15.75 ll.4/15.75 11.4/15.75 11.4/1S.7S V,,,,,,/V,,,a, Speciricationguaranteed over
Vss Range 200/ 500 200/ 7 500 200/ 200/ - 500 mV min/mV max this range.
Inn 4 4 4 4 mA max Alldigilalinpuls anur Vm
500 500 500 500 " max All digital inputsOV or vm,
Power Supply Rejection
AGairb.Won t0.02 , 0.02 t 0.02 20.02 % per%max ISU, - Voomax-Viurmin
NI P ERFO RMAN t E These characteristics are included for Design Guidance only and are not subject to test
tlhihRNrrERlSTlt
(IU = +11.4V to +15.Rill, lla, = + lilll, VP, = mes = W, Ilss = ill! ilit - 300mll,
See Figure 6 for Suggested Specification Circuit)
Parameter TA = 25"C TA = Tm," T.,m Units Test Conditions/Comments
Current Settling Time 1.5 - us max To 0.003% of full scale range.
Iorrr load - 1000,
Cr:xr = HPF. DAC registeraltcrnately
loaded with all l'sand all Ws.
Typical value of Settling Time
is 0.8115.
Digital-to-Analog Glitch Impulse 50 - nV-sec typ Measured with Wrir: - 0V. IOUT load
=l00il,Crixr =13pF.DAC
register alternately loaded with all
1's and all O's.
Multiplying Feedthrough Errors 4 - mV p-p typ VREF = t 10V, lkHz sine wave
DAC register loaded with 10 0000 0000 0000
Output Capacitance
Co, 7 (Pin 4) 260 260 pF max DAC register loaded with all I's
Covr (Pin 4) 130 130 pF max DAC register loaded with all 0's
Output Noise Voltage Density
Llon - lOOkHz) 50 - nV/Vm typ Measured between Rrm and [OUT
"rempersture range as follows: IN, KN Versions: Oto + 70°C
- 25"C to + 85°C
- 55"Cto ' 1250C
AQ, BQ Versions:
SQ, TQ Versions:
'srrcifications are guaranteed for a VI,” of + 11.4V to + 15.75V. At Vm, = 5V, the device is fully functional with degraded specifications,
'Only the D. U.T. (Le. , AD75 36) is subjected to full temperature conditions.
'Guaranteed by Product Assurance testing,
'Feedthrough can be further reduced by connecting the metal lid on the ceramic package to DGND.
Specifications subject to change without notice.
A07535
TIMING CHARACTERISTICS
1llspircifieati0nsutoU, unlm otherwise staiM.Stst+gvte1 firrTiming Diagram.)
Limit at
Limit at TA = 0 to + 70''C Limit at
Parameter TA = 25''C TA = - 25''C to + 85''C TA = - 55°C to + 125''C Units Test Conditions/Comments
t) O 0 0 ns min CSMSB or CSLSB to WR Setup Time
tg 0 0 0 ns min CSMSB or CSLSB to WR Hold Time
ts 170 200 240 ns min LDAC Pulse Width
u 170 200 240 ns min Write Pulse Width
ts 140 160 180 ns min Data Setup Time
to 20 20 30 ns min Data Hold Time
Specifications subject to change without notice.
GAIN ERROR
ANALOG OUTPUT -L
t,el _ ha; I ,’
- -f I y SV 8191 ,’/
CSMSB - V --
I I t, 12 OV " REF 8192 AJ'' -f
I f OFFSET ERROR
, , ’I _ ’1 f 5V 1"
CSLSB 1 I I t I l I I ’1
L1. -- i" I 0V "
I I F- 3 -H 5V f o"
LDAC I I I I A', f
-d 1. t "
- ' i-- q F- SV oO
OV rr ,
r-j.tsl-"j_,,iu_l_gi' ,
DAC LOADED I DAC LOADED
DATA siziif-s1-/'-1ya,,, v,,-,,;--','-';,,,,,,,,,,',, OV WITH ALL WS ,5’ WITH ALL rs
NOTES o"'
I, ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM f
10% TO 90% OF +5v. t, =1.= 20ns. 2.}
b, + v, OFFSET -
2. TIMING MEASUREMENT REFERENCE LEVEL Is ERROR /'
3. |_F LD-ttc IS ACTIVATED PRIOR TO THE RISING EDGE OF '
w_n THEN IT MUST STAY LOW FOR ts on LONGER AFTER Fr, GOES HIGH. T It. -Vrter
ANALOG OUTPUT
Figure 1. AD7536 Timing Diagram
Figure 2. AD7536 Transfer Function
ORDERING INFORMATION PRICING (100 + )$
AD7536JN $18.95
Temperature Relative Full Scale Package AD7536KN $28.45
Model Range Accuracy Error Options'
AD7536JN 0°C to + 70°C t 2LSB tl6LSB N-28 AD7536AD $28.95
AD7536KN 0°C to + 70°C t ILSB t 8LSB N-28 AD7536BD $38.45
AD7536JP 0°C to + 70°C t 2LSB t 16LSB P-28A AD7536SD $80.70
AD7536KP 0°C to + 70°C t lLSB t 8LSB P-28A AD7536TD $113.05
AD7S36AQ - 25°C to + 85°C t 2LSB t 16LSB Q-28
AD7536BQ - 2VCto + 85°C t ILSB t 8LSB Q-28
AD7536SQ - 55°C to +125°C t 2LSB tl6LSB Q-28
AD7536TQ - 55°C to +125°C t ILSB t 8I.SB Q-28
AD7536SE - 55Tto + 125°C t 2LSB t 16LSB E-28A
AD7536TE - 55'Cto +125°C t lLSB t SLSB E-28A
'E = Leadless Ceramic ChipCarrier; N i Plastic DIP; P = Plastic Leaded ChipCarrier;
Q = Cerdip; R
- SOIC.
A07536
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise stated)
Derates above + 75°C ............... 10mW/°C
Operating Temperature Range
Vor, (pin 26) to DGND ............. -0.3V, + 17V Commercial Plastic (JN, KN versions) . . . 0 to + 70°C
Vss (pin 27) to AGND ............. - 15V, +0.3V Industrial Ceramic (AQ, BQ versions) . - 25°C to + 85°C
VREF (pin 2) to AGND '. ................ t25V Extended Ceramic (SQ, TQ versions) . - 55°C to + 125°C
va (pin 28) to AGND ................. t25V Storage Temperature ......... - 65°C to + 150°C
Rrroa, (pin 1) to AGND ................. t25V Lead Temperature (Soldering, 10 secs) ...... + 300°C
Res (pin 3) t0 AGND .................. t25V . . .
Digit al Input Voltage (pins 8-25) to DGND -0.3V V *Stresses above those listed under P.bs.olute Maximem Ratings" may cause
, DD permanent damage to the device. This IS a stress rating only and functional
VPIN4 t0 DGND ................. -0.3V, Von operation of the device at these or any other conditions above those indicated
AGND to DGND ................ -0.3V, Vroo in the operational sections of this specification is not implied. Exposure to
Power Dissipation (Any package) absolute maximum rating conditions for extended periods may affect device
To + 75°C ....................... 1000mW reliability.
CAUTION
ESD (Electro-Static-Discha'fge) sensitive device. The digital control inputs are diode protected; how-
ever, permanent damage may occur on unconnected devices subject to high energy electrostatic fields.
Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged
to the destination socket before devices are removed.
TERMINOLOGY
LEAST SIGNIFICANT BIT (LSB)
This is the analog weighting of 1 bit of the digital word in a
DAC. For the AD7536 lLSB = 214
RELATIVE ACCURACY
Relative accuracy or end point nonlinearity is a measure of the
maximum deviation from a straight line passing through the
end-points of the DAC transfer function. It is measured after
adjusting for both endpoints (i.e., Offset and Gain Error are
adjusted out) and is normally expressed in Least Significant Bits
or as a percentage of full scale range.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the difference between the measured
change and the ideal lLSB change between any two adjacent
codes. A specified differential nonlinearity of + lLSB max over
the operating temperature range ensures monotonicity.
GAIN ERROR
Gain error is a measure of the output error between an ideal
DAC and the actual device output with all one's loaded after
offset error has been adjusted out. Gain error is adjustable to
zero with an external potentiometer.
OFFSET ERROR
Offset error is a measure of the mismatch between Rm, and the
internal offset resistor, ROFS. It also includes the leakage com-
ponent from the DAC (see Figure 8). It is present for all codes
and is expressed in Least Significant Bits.
DIGITAL-TO-ANALOG GLITCH IMPULSE
The amount of charge injected from the digital inputs to the
analog output when the inputs change state is called Digital-to-Ana-
log Glitch Impulse. This is normally specified as the area of the
glitch in either pA-secs or nV-secs depending upon whether the
glitch is measured as a current or voltage. It is measured with
OUTPUT CAPACITANCE
This is the capacitance from Iotrr to AGND.
LEAKAGE CURRENT
Leakage current flows into Iom- from the 14-bit DAC when all
the DAC switches are off. It contributes to the Linearity, Gain
and Offset error (see Figure 8).
MULTIPLYING FEEDTHROUGH ERROR
This is the ac error due to capacitive feedthrough from VREF
terminal to [OUT with DAC register loaded with
10 0000 0000 0000.
O‘VIAUJN
Function
Description
Contact point for internal resistors R1 and R2 which perform the inverting function on VREF with external
op-amp. See Figure 3.
Reference input to the DAC. It is internally connected to ROFS and R1. See Figure 3.
Feedback resistor. Used to close the loop around an external op-amp.
Current Output Terminal.
Analog ground sense line. Reference point for external circuitry. This pin should carry minimal current.
Analog ground force line; carries current from internal analog ground connections. AGNDF and AGNDs are tied
together internally.
Digital Ground
Data Bit 13. DAC MSB
Data Bit 12
Data Bit 1 1
Data Bit 10
Data Bit 9
Data Bit 8
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0. DAC LSB
Chip Select Most Significant (MS) Byte. Active LOW input.
Asynchronous Load DAC input. Active LOW.
Chip Select Least Significant (LS) Byte. Active LOW input.
Write input. Active LOW.
t5fGTgrt CSI-SB LD-AC W Operation
0 1 1 0 Load MS Input Register
1 0 l 0 Load LS Input Register
0 0 l 0 Load MS and LS Input Registers
l l 0 X Load DAC Register from Input Registers
0 0 0 0 All Registers are transparent
l l l x No operation
x x 1 1 No operation
NOTE X = Don't Care
Power supply input. Specifications apply for Vor, = + 12V t 5% to + 15V t 5%.
Bias pin for High Temperature Low Leakage configuration. To implement low leakage system, the pin should
be at a negative voltage. See Figure 5 or 6 for recommended circuitry.
This pin must be connected to the output of the external inverting op-amp. See Figure 3.
