AD7528 Fast Delivery |IC PHOENIX CO.,LIMITED

AD7528 ,CMOS Dual 8-Bit Buffered Multiplying DACGENERAL DESCRIPTION ORDERING GUIDEThe AD7528 is a monolithic dual 8-bit digital/analog converterTem ..
AD7528AQ ,CMOS Dual 8-Bit Buffered Multiplying DACCHARACTERISTICS See Timing DiagramChip Select to Write Set Up TimeAll 90 100 60 80 ns mintCSChip Se ..
AD7528BQ ,CMOS Dual 8-Bit Buffered Multiplying DACCHARACTERISTICS Output Amplifiers)V = +5 V V = +15 VDD DD1Parameter Version T = +25

AD7528
CMOS Dual 8-Bit Buffered Multiplying DAC
REV.BCMOS Dual 8-Bit
Buffered Multiplying DAC
FEATURES
On-Chip Latches for Both DACs
+5 V to +15 V Operation
DACs Matched to 1%
Four Quadrant Multiplication
TTL/CMOS Compatible
Latch Free (Protection Schottkys not Required)
APPLICATIONS
Digital Control of:
Gain/Attenuation
Filter Parameters
Stereo Audio Circuits
X-Y Graphics
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7528 is a monolithic dual 8-bit digital/analog converter
featuring excellent DAC-to-DAC matching. It is available in
skinny 0.3" wide 20-lead DIPs and in 20-lead surface mount
packages.
Separate on-chip latches are provided for each DAC to allow
easy microprocessor interface.
Data is transferred into either of the two DAC data latches via a
common 8-bit TTL/CMOS compatible input port. Control
input DAC A/DAC B determines which DAC is to be loaded.
The AD7528’s load cycle is similar to the write cycle of a ran-
dom access memory and the device is bus compatible with most
8-bit microprocessors, including 6800, 8080, 8085, Z80.
The device operates from a +5 V to +15 V power supply, dis-
sipating only 20 mW of power.
Both DACs offer excellent four quadrant multiplication charac-
teristics with a separate reference input and feedback resistor for
each DAC.
PRODUCT HIGHLIGHTS
1. DAC-to-DAC matching: since both of the AD7528 DACs are
fabricated at the same time on the same chip, precise match-
ing and tracking between DAC A and DAC B is inherent.
The AD7528’s matched CMOS DACs make a whole new
range of applications circuits possible, particularly in the
audio, graphics and process control areas.
2. Small package size: combining the inputs to the on-chip DAC
latches into a common data bus and adding a DAC A/DAC B
select line has allowed the AD7528 to be packaged in either a
small 20-lead DIP, SOIC or PLCC.
ORDERING GUIDE1
NOTESAnalog Devices reserves the right to ship side-brazed ceramic in lieu of cerdip. Parts
will be marked with cerdip designator “Q.”Processing to MIL-STD-883C, Class B is available. To order, add suffix “/883B” to
part number. For further information, see Analog Devices’ 1990 Military Products
Databook.N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
AD7528–SPECIFICATIONS(VREF A = VREF B = +10 V; OUT A = OUT B = O V unless otherwise noted)
SWITCHING CHARACTERISTICS3
POWER SUPPLY
AC PERFORMANCE CHARACTERISTICS5
CURRENT SETTLING TIME
PROPAGATION DELAY (From Digital In-
AC FEEDTHROUGH
(Measured Using Recommended P.C. Board Layout (Figure 7) and AD644 as
Output Amplifiers)
PLCC
CHANNEL-TO-CHANNEL ISOLATION
NOTESTemperature Ranges areJ, K, L Versions: –40°C to +85°C
A, B, C Versions: –40°C to +85°C
S, T, U Versions: –55°C to +125°CSpecifications applies to both DACs in AD7528.Guaranteed by design but not production tested.Logic inputs are MOS Gates. Typical input current (+25°C) is less than 1 nA.These characteristics are for design guidance only and are not subject to test.Feedthrough can be further reduced by connecting the metal lid on the ceramic package
(suffix D) to DGND.
Specifications subject to change without notice.
AD7528, ideal maximum output is VREF – 1 LSB. Gain error of
both DACs is adjustable to zero with external resistance.
Output Capacitance
Capacitance from OUT A or OUT B to AGND.
Digital to Analog Glitch lmpulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or
voltage signal. Glitch impulse is measured with VREF A,
VREF B = AGND.
Propagation Delay
This is a measure of the internal delays of the circuit and is
defined as the time from a digital input change to the analog
output current reaching 90% of its final value.
Channel-to-Channel Isolation
The proportion of input signal from one DAC’s reference input
which appears at the output of the other DAC, expressed as a
ratio in dB.
Digital Crosstalk
The glitch energy transferred to the output of one converter due
to a change in digital input code to the other converter. Speci-
fied in nV secs.
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V, +17 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V, +17 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . .VDD + 0.3 V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . .VDD + 0.3 V
Digital Input Voltage to DGND . . . . . . .–0.3 V, VDD + 0.3 V
VPIN2, VPIN20 to AGND . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
VREF A, VREF B to AGND . . . . . . . . . . . . . . . . . . . . . . .–25 V
VRFB A, VRFB B to AGND . . . . . . . . . . . . . . . . . . . . . . .–25 V
Power Dissipation (Any Package) to +75°C . . . . . . .450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . .6 mW/°C
Operating Temperature Range
Commercial (J, K, L) Grades . . . . . . . . . . .–40°C to +85°C
Industrial (A, B, C) Grades . . . . . . . . . . . .–40°C to +85°C
Extended (S, T, U) Grades . . . . . . . . . . .–55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C
CAUTION:
1. ESD sensitive device. The digital control inputs are diode
protected; however, permanent damage may occur on uncon-
nected devices subjected to high energy electrostatic fields.
Unused devices must be stored in conductive foam or shunts.
2. Do not insert this device into powered sockets. Remove
power before insertion or removal.
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is normally expressed in
LSBs or as a percentage of full scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of –1 LSB max over
the operating temperature range ensures monotonicity.
AD7528
OUT A
RFB A
VREF A
DAC A/DAC B
DGND
RFB B
VREF B
VDDOUT B
AD7528
INTERFACE LOGIC INFORMATION
DAC Selection:
Both DAC latches share a common 8-bit input port. The con-
trol input DAC A/DAC B selects which DAC can accept data
from the input port.
Mode Selection:
Inputs CS and WR control the operating mode of the selected
DAC. See Mode Selection Table below.
Write Mode:
When CS and WR are both low the selected DAC is in the write
mode. The input data latches of the selected DAC are transpar-
ent and its analog output responds to activity on DB0–DB7.
Hold Mode:
The selected DAC latch retains the data which was present on
DB0–DB7 just prior to CS or WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches.
Mode Selection Table
L = Low State; H = High State; X = Don’t Care.
WRITE CYCLE TIMING DIAGRAM
VDD
tDH
tAHtCH
VDD
VDD
VDD
CHIP SELECT
DAC A/DAC B
WRITE
DATA IN
(DB0 – DB7)
NOTES:
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED
FROM 10% TO 90% OF VDD.
VDD = +5V, tr = tf = 20ns;
VDD = +15V, tr = tf = 40ns;
2. TIMING MEASUREMENT REFERENCE LEVEL ISVIH + VIL
CIRCUIT INFORMATION—D/A SECTION
The AD7528 contains two identical 8-bit multiplying D/A con-
verters, DAC A and DAC B. Each DAC consists of a highly
stable thin film R-2R ladder and eight N-channel current steer-
ing switches. A simplified D/A circuit for DAC A is shown in
VREF A
AGNDRR
OUT A
RFB A
Figure 1.Simplified Functional Circuit for DAC A
Figure 1. An inverted R-2R ladder structure is used, that is, bi-
nary weighted currents are switched between the DAC output
and AGND thus maintaining fixed currents in each ladder leg
independent of switch state.
EQUIVALENT CIRCUIT ANALYSIS
Figure 2 shows an approximate equivalent circuit for one of the
AD7528’s D/A converters, in this case DAC A. A similar
equivalent circuit can be drawn for DAC B. Note that AGND
(Pin 1) is common for both DAC A and DAC B.
The current source ILEAKAGE is composed of surface and junc-
tion leakages and, as with most semiconductor devices, approxi-
mately doubles every 10°C. The resistor RO as shown in Figure
2 is the equivalent output resistance of the device which varies
with input code (excluding all 0s code) from 0.8 R to 2 R. R is
typically 11 kW. COUT is the capacitance due to the N-channel
switches and varies from about 50 pF to 120 pF depending
upon the digital input. g(VREF A, N) is the Thevenin equivalent
voltage generator due to the reference input voltage VREF A and
the transfer function of the R-2R ladder.
Figure 2.Equivalent Analog Output Circuit of DAC A
CIRCUIT INFORMATION–DIGITAL SECTION
The input buffers are simple CMOS inverters designed such
that when the AD7528 is operated with VDD = 5 V, the buffer
converts TTL input levels (2.4 V and 0.8 V) into CMOS logic
levels. When VIN is in the region of 2.0 volts to 3.5 volts the
input buffers operate in their linear region and pass a quiescent
current, see Figure 3. To minimize power supply currents it is
recommended that the digital input voltages be as close to the
supply rails (VDD and DGND) as is practically possible.
The AD7528 may be operated with any supply voltage in the
range 5 £ VDD £ 15 volts. With VDD = +15 V the input logic
levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.
Figure 3.Typical Plots of Supply Current, IDD vs. Logic
Input Voltage VIN, for VDD = +5 V and +15 V
Table I. Unipolar Binary Code Table
Note: 1 LSB =
Table II. Bipolar (Offset Binary) Code Table
Note: 1 LSB =
Table III. Recommended Trim Resistor
Values vs. Grade
VIN A
(± 10V)
VIN B
(± 10V)
VDD
DB0
DB7
DATA
INPUTS
DAC A/
DAC B
DGND
VOUT B
VOUT A
NOTES:
1R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
SEE TABLE III FOR RECOMMENDED VALUES.
2C1, C2 PHASE COMPENSATION (10pF–15pF) IS REQUIRED WHEN
USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION.
Figure 4.Dual DAC Unipolar Binary Operation
(2 Quadrant Multiplication); See Table I
VIN A
(± 10V)
VIN B
(± 10V)
VDD
DB0
DB7
DATA
INPUTS
DAC A/
DAC B
DGND
VOUT B
VOUT A
AGND
AGND
NOTES:
1R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
SEE TABLE III FOR RECOMMENDED VALUES.
ADJUST R1 FOR VOUT A = 0V WITH CODE 10000000 IN DAC A LATCH.
ADJUST R3 FOR VOUT B = 0V WITH CODE 10000000 IN DAC B LATCH.
2MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R6, R7 AND R9, R10.
3C1, C2 PHASE COMPENSATION (10pF–15pF) MAY BE REQUIRED
IF A1/A3 IS A HIGH SPEED AMPLIFIER.
Figure 5.Dual DAC Bipolar Operation
(4 Quadrant Multiplication); See Table II
AD7528
APPLICATIONS INFORMATION
Application Hints
To ensure system performance consistent with AD7528 specifi-
cations, careful attention must be given to the following points:GENERAL GROUND MANAGEMENT: AC or transient
voltages between the AD7528 AGND and DGND can cause
noise injection into the analog output. The simplest method
of ensuring that voltages at AGND and DGND are equal is
to tie AGND and DGND together at the AD7528. In more
complex systems where the AGND–DGND intertie is on the
backplane, it is recommended that diodes be connected in
inverse parallel between the AD7528 AGND and DGND
pins (1N914 or equivalent).OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a
code-dependent output resistance which in turn causes a
code-dependent amplifier noise gain. The effect is a code-
dependent differential nonlinearity term at the amplifier
output which depends on VOS (VOS is amplifier input offset
voltage). This differential nonlinearity term adds to the R/2R
differential nonlinearity. To maintain monotonic operation, it
is recommended that amplifier VOS be no greater than 10% of
1 LSB over the temperature range of interest.HIGH FREQUENCY CONSIDERATIONS: The output
capacitance of a CMOS DAC works in conjunction with the
amplifier feedback resistance to add a pole to the open loop
response. This can cause ringing or oscillation. Stability can
be restored by adding a phase compensation capacitor in
parallel with the feedback resistor.
DYNAMIC PERFORMANCE
The dynamic performance of the two DACs in the AD7528 will
depend upon the gain and phase characteristics of the output
amplifiers together with the optimum choice of the PC board
layout and decoupling components. Figure 6 shows the relation
INPUT FREQUENCY – Hz
ISOLATION – dB
20k50k100k200k1M500k
–50
Figure 6.Channel-to-Channel Isolation
AD644
VREF B*
VDD
C1 LOCATION
C2 LOCATION
VREF A*
DGND
DAC A/DAC B
PIN 8 OF TO-5 CAN (AD644)
AD7528 PIN 1
*NOTE
INPUT SCREENS
TO REDUCE
FEEDTHROUGH.
LAYOUT SHOWS
ship between input frequency and channel to channel isolation.
Figure 7 shows a printed circuit layout for the AD7528 and the
AD644 dual op amp which minimizes feedthrough and crosstalk.
SINGLE SUPPLY APPLICATIONS
The AD7528 DAC R-2R ladder termination resistors are con-
nected to AGND within the device. This arrangement is par-
ticularly convenient for single supply operation because AGND
may be biased at any voltage between DGND and VDD. Figure
8 shows a circuit which provides two +5 V to +8 V analog out-
puts by biasing AGND +5 V up from DGND. The two DAC
reference inputs are tied together and a reference input voltage
is obtained without a buffer amplifier by making use of the
constant and matched impedances of the DAC A and DAC B
reference inputs. Current flows through the two DAC R-2R
ladders into R1 and R1 is adjusted until the VREF A and VREF B
inputs are at +2 V. The two analog output voltages range from
+5 V to +8 V for DAC codes 00000000 to 11111111.
Figure 8.AD7528 Single Supply Operation
Figure 9 shows DAC A of the AD7528 connected in a positive
reference, voltage switching mode. This configuration is useful
in that VOUT is the same polarity as VIN allowing single supply
operation. However, to retain specified linearity, VIN must be in
the range 0 V to +2.5 V and the output buffered or loaded with
a high impedance, see Figure 10. Note that the input voltage is
connected to the DAC OUT A and the output voltage is taken
from the DAC VREF A pin.
Figure 9.AD7528 in Single Supply, Voltage Switching Mode

Partno	Mfg	Dc	Qty	Available	Descript
AD7528	AD	N/a	200	avai	CMOS Dual 8-Bit Buffered Multiplying DAC