AD7512DISQ ,25V; DI CMOS protected analog switchesfeatures of an
analog switch.
The AD7510DI and AD7511DI consist of four independent
SPST analo ..
AD7512DITQ ,Protected Analog SwitchesWuan-eDem.
ANALOG
DEVICES
Ill CMOS
Protected Analog Switches
AD75IODI/AD751IDI/A075120l
..
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ADG409BN ,LC2MOS 4-/8-Channel High Performance Analog Multiplexersapplications where the analog signal is unipolar, the2ADG408/ADG409 can be operated from a single r ..
ADG409BN ,LC2MOS 4-/8-Channel High Performance Analog MultiplexersFEATURESFUNCTIONAL BLOCK DIAGRAMS44 V Supply Maximum RatingsV to V Analog Signal RangeSS DDLow On R ..
ADG409BR ,LC2MOS 4-/8-Channel High Performance Analog MultiplexersSPECIFICATIONS1(V = +15 V, V = –15 V, GND = 0 V, unless otherwise noted)DUAL SUPPLY DD SSB Version ..
AD7512DISQ
25V; DI CMOS protected analog switches
ANALOG
DEVICES
DI CMOS
Protected Analog Switches
A0751illWll0751 1 Dl/AD751ZDI
FEATURES
Latch-Proof
Overvoltage-Proof: t25V
Low Ron! 75.0
Low Dissipation: 3mW
TTUCMOS Direct Interface
Silicon-Nitride Passivated
Monolithic Dielectrically-lsolated CMOS
Standard 14-]16-Pin DIPs and
20-Terminal Surface Mount Packages
GENERAL DESCRIPTION
The AD7SIODI, AD7SIlDI and AD7512DI are a family of
latch proof dielectrically isolated CMOS switches featuring over-
voltage protection up to t 25V above the power supplies. These
benefits are obtained without sacrificing the low "ON" resistance
(75n) or low leakage current (SOOpA), the main features of an
analog switch.
The AD7510DI and AD7511DI consist of four independent
SPST analog switches packaged in either a 16-pin DIP or a 20-
terminal surface mount package. They differ only in that the
digital control logic is inverted. The AD7512DI has two inde-
pendent SPDT switches packaged either in a 14-pin DIP or a
20-terminal surface mount package.
Very low power dissipation, overvoltage protection and TTL/
CMOS direct interfacing are achieved by combining a unique
circuit design and a dielectrically isolated CMOS process. Silicon
nitride passivation ensures long term stability while monolithic
construction provides reliability.
CONTROL LOGIC
AD75 IODI: Switch "ON" for Address "HIGH"
AD7511D1: Switch "ON" for Address "LOW"
AD7512D1: Address "HIGH" makes SI to Out I and $310
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
DIP FUNCTIONAL DIAGRAMS
Vsslt q ws-Els,
GNDE F‘[>°'\,_E] m GND 2
mE-J 6-352 At FC] LEM
Litrci,ittr,N,tir2 A24-1 354
'Ive),
AD751ODI
A3 E-n. AD7511D| FE " NC 5
L4 yo-
M Ei- 1 TOP “wa31 D3 NC 8
NCE E S4
T P VIEW
I (Not to Scale) o
(Not ttt ScaIe) 3 NC
NC = NO CONNECT
r-tso-SCC-l'','',
NC = NO CONNECT
ORDERING GUIDE
Temperature Package
Model' Range Option2
AD7510DIKN 0m + 70''C N-l6
AD75IODIKP 0 to + 70°C P-20A
AD7510DIKQ - 25°C to + 85°C Q-16
AD7510DISQ - 55°C to + 125°C Q-16
AD7510DISE - 55°C to + 125°C E-20A
AD7511DIKN 0to + 70°C N-l6
AD7511DIKP 0 to + 70°C P-20A
AD7511DIKQ -25°C to +85°C Q-16
AD7511DISQ - 55°C to + 125°C Q-16
AD7511D1TE - 55°C to + 125°C E-20A
AD7512D1KN Oto +70°C N-14
AD75 12DIKP 0to + 70°C P-20A
AD7512DIKQ -25t to +85°C Q-14
AD7512D1TQ - 55°C to + 125°C Q-14
AD7512DITE - 55°C to + 125°C E-NA
lTo order MIL-STD-883, Class B, processed parts, add/883B to
part number. See Analog Devices Military Products Danbook (1990)
for military data sheet.
2E = Leadlcss Ctramic ChipCarrier(LCCC); N = Plastic DIP;
P = Plastic Leaded ChipCarrier(PLCC); Q = Cctdip.
One Technology Way, PO. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703 wa: 710/394-6577
Telex: 924491 Cable: ANALOG NORWOODMASS
AD751IIDI/AD751 lol/lilly-SPECIFICATIONS
Specifications subject to change without notice.
E , g a a
a 2 , " "
At c a $2
" ' AD75100| " tt2
AD75TTm
NC ' rovvmw " MC
" , [Not IoSc-kl " "
u I u D3
I " " " "
3 32 Br,
NC - NOCONNECT
PIN CONFIGURATIONS
32120"
NC s n
AD7512Dt
" tt TOP VIEW "
NC ' um Io Suki "
NC a u
' " 1112 "
NC = NO CONNECT
AD7510DI
NC A0751 1m
TOP VIEW
" (~01 to SEALED
NC " NO CONNECT
AD75120|
TOP VIEW
[Not In Salli
(IG, = +1511, Ilss = -15V, unless otherwise noted.)
INDUSTRIAL VERSION (K)
PARAMETER MODEL VERSION o2s''c o to "tft: (N, p) TEST CONDITIONS
IN, P, Q) -2s°c to e8s''c (Q)
ANALOG SWITCH
RON‘ All K 7551 typ, 100:2 max 1759 max -10V < vo <_+1ov
RON vs VD (vs) All K 20% typ los = 1.0mA
RON min All K +o.s%/°c typ
RON 343; All K 1% ryp VD = o, lus = 1.0mA
58:1,, All K 0.01%/°c ryp
1D (15)0FF' All K 0.5nA typ, SnA max SOOnA max VD = -10V, VS = +10V and
VD = +10v. vs = -10v
Ity (ls)0N' All K 10m mu vs = VD = +10v
vs = Vo = -1ov
IOUT‘ AD7512DI K 15nA max 1500nA max vs, = vour = 210v.v52 = nov
and vs, = VOUT = t10V, VS] = HOV
DIGITAL CONTROL
vm' All K 0.8V max
vem' All 2.4V min
cm All K 79F typ
IN,.' All K lOnA max ve: = VDD
[Ml All K 10nA max Vm = 0
DYNAMIC
CHARACTERISTICS
ION AD7510DI K 180ns typ
AD7511DI K 350m ryp VIN = 0 to -3.OV
[OFF AD7510DI K 350ns typ
AD751 IDI K 180ns typ
hRANSrrtoN AD7512DI K 300ns typ
Cs (CD)0FF All K 8pF typ
Cs (CD)ON All K 17pF typ
cos (Cs-our) All K lpF typ VD (Vs) = ov
CDD (C55) All K 0.5pF ryp
cOUT AD7512IN K 17pF typ
All K 3 C t Measured at S or D terminal.
QM Op yp tk. = 1000pF, vIN = o to 3V.
VD (Vs) = +10V to -10V
POWER SUPPLY
IDD' All K 800PA max 800PA max All digital inputs = VIN"
Iss' All K 800PA max 800PA max
Inn' All K SOOpA max SOOuA max All digital inputs " VINL
Iss' All K S00PA max $00PA max
, 100% tested.
REV. A
M75ulll/li0751 1 DI/AD75120I
EXTENDED VERSIONS (S, T)
PARAMETER MODEL VERSION oas''c -ss°c to +125°c TEST CONDITIONS
ANALOG SWITCH
RON' All s, T 10052 max 1759 max -1ov < VD < +10v
los = 1mA
ID "spore' All s, T 3nA max 200nA max VD " -10V, vs = +10v and
VD = uov. Vs = -10V
ID (is)ON' All s, T 10 vs " VD = +10v and
Vs = VD = -1ov
IOUTI AD7512DI S. T 9nA max 600nA max V51 = VOUT = 110V
vs, = nov and
vs2 = VOUT = nov
vs, = nov
DIGITAL CONTROL
VM' All s, T o.sv max
VINE“, AD7SIODI s 2.4V min
AD7SIIDI T 2.4V min
AD7512DI T 2.4V min
AD7SIIDI s 3.0V min
AD7512D1 s 3.0V min
um": All s, T lOnA max Vrr: = vor,
bi. All s, T lOnA max IN = 0
DYNAMIC
CHARACTERISTICS
tos' AD7SIODI s, Lous max vIN = o to +3V
AD7SllDI s, T 1.0ps max
tops’ AD7510DI s, T 1.0ps max
AD7511DI s, T 1.0ps max
t-mmsmon3 AD7SIZDI s, T 1.0ps max
POWER SUPPLY
Yarn' All s, T 800PA max All digital inputs = VIN"
Iss All S, T 800PA max
[DD] All s, T 500M max All digital inputs . VINL
Iss All s, T 500PA max
'iotnt, tested.
'A pullup resistor, typicdly l-an is required to make AD7SllDlSQ end AD7512DISQ TTL compatible.
'Guuwteed. ttot production tested.
Speeiriiioas subject to chmge without notice.
ABSOLUTE MAXIMUM RATINGS‘
VDD to GND ...................... + 17V
Vss to GND ....................... - 17V
Overvolmge at Vo (V s)
(1 second surge) ................ 'a, +25V
or Vss - 25V
(Continuous) .................. Voo + 20V
or Vss - 20V
or 20mA , Whichever Occurs First
Switch Current (IDS, Continuous) ...... . . . . . . . 50mA
Switch Current ODS, Surge)
lms Duration, 10% Duty Cycle ........... 150mA
Digital Input Voltage Range ........ 0V to Von +0.3V
Power Dissipation (Any Package)
Up to +75''C .................... 450mW
Lhtat_es_ta)tove_t78'9y .........._. . . . 6mW/°C
CAUTION
Lead Temperature (Soldering, lOsec) ......... + 300°C
Storage Temperature ............ - 65°C to + 150°C
Operating Temperature
Commercial (KN, KP Versions) ........ 0 to + 70°C
Industrial (KQ Versions) ......... -25''C to + 85''C
Extended (SQ, TQ, SE, TE Versions) . . - 55°C to + 125°C
‘Sum above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect-
ed; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
REV. A
GEWIIMI
Ii I ESD SENS! IVE DEVICE
Nn51illMN511lll/M7512lll--0ircuit Description
i 43v” +15v
TTI. A LEVEL
CONTR)- SHIFTERI
INPUT DRIVER
tirte)
ovgs-Isv
NOTE: CIRCLED DEVICES IN
SEPARATE ISOLA‘IED POCKETS.
Figure f. Typical Output Switch Circuitry of AD75100/ Series
CIRCUIT DESCRIPTION
CMOS devices make excellent analog switches; however, problems
with overvoltage and latch-up phenomenon necessitated protection
circuitry. These protection circuits, however, either caused
degradation of important switch parameters such as Ros
or leakage, or provided only limited protection in the event of
overvoltage.
The AD7510DI series switches utilize a dielectrically isolated
CMOS fabrication process to eliminate the four-layer substrate
found in iunction-isolated CMOS, thus providing latch-free
operation.
A typical switch channel is shown in Figure 2. The output
switching element is comprised of device numbers 4 and 5.
Operation is as follows: for an "ON" switch, (in +) is Voo and
(in -) is Vss from the driver circuits. Device numbers 1 and 2
are "OFF" and number 3 in "ON". Hence, the backgates of the
P- and N-channel output devices (numbers 4 and S) are tied
together and floating. The circled devices are located in separate
dielectrically isolated pockets. Floating the output switch backgates
with the signal input increases the effective threshold voltage for
an applied analog signal, thus providing a flatter RON versus Vs
response.
For an "OFF" switch, device number 3 is "OFF," and the
backgates of devices 4 and S are tied through lkn resistors (R1
and R2) to the respective supply voltages through the "ON"
devices 1 and 2.
If a voltage is applied to the S or D (OUT) terminal which
exceeds Voz, or Vss, the S- or D-to-backgate diode is forward
biased; however, R1 and R2 provide current limiting action to
the supplies.
An equivalent circuit of the output switch element in Figure 3
shows that, indeed, the 1kft limiting resistors are in series with
the backgates of the P- and N-channel output devices - not in
series with the signal path between the S and D terminals.
It is possible to turn on an "OFF" switch by applying a voltage
in excess of VDD or Vss to the S or D terminal. If a positive
stress voltage is applied to the S or D terminal which exceeds
VDD by a threshold, then the P-channel (device 5) will turn on
creating a low impedance path between the S and D terminals.
A similar situation exists for negative stress voltages which
exceed Vss. In this case the N-channel provides the low impedance
path between the S and D terminals. The limiting factor on the
overvoltage protection is the power dissipation of the package
and is t 20V continuous (or 20mA whichever occurs first) above
the supply voltages.
P CHANNEL
N- CHANNEL
Figure 2. A075 100/ Series Output Switch
Diode E quivalent Circuit
REV. A
