AD75089JP ,MONOLITHIC OCTAL 12-BIT DACPORTfeatures
bipolar transistors for precise analog circuitry, CMOS transistors
for dense logic and a ..
AD7510DI ,Protected Analog SwitchesGENERAL DESCRIPTION
The AD7510DI, AD7SllDI and AD7512DI are I family of
larch proof dielectrica ..
AD7510DIJN ,DI CMOS Protected Analog SwitchesFEATURES
anh-Proaf
Overvoltng-Proof: t25V
an no": 75tt
Low Dissipation: 3mW
TTLICMOS ..
AD7510DIJP ,DI CMOS Protected Analog SwitchesGENERAL DESCRIPTION
The AD7510DI, AD7SllDI and AD7512DI are I family of
larch proof dielectrica ..
AD7510DIJQ ,DI CMOS Protected Analog SwitchesFEATURES
anh-Proaf
Overvoltng-Proof: t25V
an no": 75tt
Low Dissipation: 3mW
TTLICMOS ..
AD7510DIKD , DI CMOS Protected Analog Switches
ADG3242BRJ-REEL ,2.5 V/3.3 V, 2-Bit, Common Control Level Translator Bus SwitchCHARACTERISTICS4Propagation Delay A to B or B to A, t t , t C = 50 pF, V = SEL = 3 V 0.225 nsPD PHL ..
ADG3243BRJ-R2 ,2.5 V/3.3 V, 2-Bit, Individual Control Level Translator Bus SwitchSpecifications subject to change without notice.–2– REV. 0ADG3243ABSOLUTE MAXIMUM RATINGS* PIN CONF ..
ADG3245BRU ,2.5 V/3.3 V, 8 Bit, 2 Port Level Translator, Bus SwitchSpecifications subject to change without notice.–2– REV. 0ADG3245ABSOLUTE MAXIMUM RATINGS* LFCSP Pa ..
ADG3246BRU ,2.5 V/3.3 V, 10 Bit, 2 Port Level Translator, Bus SwitchSpecifications subject to change without notice.–2– REV. 0ADG3246ABSOLUTE MAXIMUM RATINGS* LFCSP Pa ..
ADG3247BRU ,2.5 V/3.3 V, 16 Bit (Dual 8 Bit) , 2 Port Level Translator, Bus SwitchSpecifications subject to change without notice.–2– REV. 0ADG3247ABSOLUTE MAXIMUM RATINGS* LFCSP Pa ..
ADG3249BRJ-REEL7 ,2.5 V/3.3 V, 2:1 Multiplexer/Demultiplexer Bus SwitchCHARACTERISTICS4Propagation Delay A to B or B to A, t t , t C = 50 pF, V = SEL = 3 V 0.225 nsPD PHL ..
AD75089JP
MONOLITHIC OCTAL 12-BIT DACPORT
ANALOG
DEVICES
Monolithic Octal
12-Bit DACPORT
M75088
FEATURES
Eight Complete Voltage Output DACs
On-Chip Voltage Reference
On-Chip Data Latches with Readback Feature
Output Voltage Range: :L-5 If
Compact M-Pin PLCC Package
APPLICATIONS
Automatic Test Equipment
Instrumentation
Avionics
Robotics
Process Control
PRODUCT DESCRIPTION
The AD75089 DACPORT® contains eight complete 12-bit, volt-
age output digital-to-analog converters in one monolithic IC. It
thus offers the highest density 12-bit D/A function available.
Each DAC offers flexibility, accuracy and good dynamic perfor-
mance. The R-2R structure is fabricated from thindilm resistors
that are laser-trimmed to achieve guaranteed monotonicity over
the full operating temperature range. DAC-to-DAC matching
performance is specified.
The output amplifier combines the best features of bipolar and
MOS devices to achieve good dynamic performance and low off-
set. Settling time is under 10 M, and each output can drive a
2 mA, 500 pF load. Short circuit protection allows indefinite
shorts to Vac, V00, Vss, and GND.
Digital circuitry is implemented in CMOS logic. The fast, low
power, digital interface allows this DACPORT to interface with
most microprocessors through a single 12-bit wide bus. A read-
back feature allows the internal DAC registers to be read back
through the digital port as 12-bit words. When disabled, the
readback drivers are placed in a high impedance mode.
A RESET control pin is provided to allow simultaneous asyn-
chronous reset of all DAC data latches, causing the DAC out-
puts to go to the negative extreme of their range.
The analog portion of the DACPORT consists of eight DAC
cells, eight output amplifiers, a voltage reference, a control
amplifier and switches. Each DAC cell is an inverting R-2R
type. The output current from each DAC is switched to the
DACPORT is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
vnsrgyr VREFIN
oW A c, ANALOG C.' Am
Vnsr . - SUPPLY
GND - '
AGND . ANALOG _ -1
GROUND ANAL C.' v
V SUPPLY "
VHEF .
-lrA'r-"'"D", ',fji':y . v
iris"""'"] OUT
D11 . . v
$0 _ Vnsr am
D8 . 124m
s - - t2-BtT DAC TCC;
07 . LATCH Ct:) . . Gm,
D6 T, we 1ltt'11fr]
DS - BUFFER ' Vans
5 - Cl ll
D3 T, ' - HVEOFEIGHT T, i/le..'.
D2 0 RET5
m . a - fi'lt'l'l"'"'o' [,' vow
m , 2 - AD75089 C.' Van:
, - T. a,,
' Vou‘n
V Cl :naz
REF r ' OUT
10GNDC ',.i.:'.CsvC, Fic,','
12-arr . _
o-ltr/l, 123n'DAc CC,):) e v
rlptrrj m
IG, . 05V LOGIC SUPPLY T. vnm
DIGITAL
DGND Cl comm. LOGIC
tt7t'irEia2matttttrr
on-chip application resistors and output amplifier. The chip may
be operated from the internal reference or an external reference.
The high performance and functional completeness of this
DACPORT result from their fabrication in Analog Devices'
BiMOS II process. This epitaxial BiCMOS process features
bipolar transistors for precise analog circuitry, CMOS transistors
for dense logic and analog switches, laser-trimmed thin-film
resistors and double-level metal interconnects.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
M75iW-SPEtllFltyirlthl $c;.;.~;i:v.::-:.:.1221:rm;V..¥;;:~.;.;:2°:.r.-::' hz, pins
Parameter Min Typ Max Units
RESOLUTION 12 Bits
ANALOG OUTPUT
Voltage Range, Vom- max to VOUT min t5 Volts
Output Current (Each Channel, Source or Sink) 2 mA
Load Capacitance (Each Channel) 500 pF
Short Circuit Current (Each Channel) 25 50 mA
ACCURACY
Gain Error, Including Internal Reference - 15 t8 15 LSB
Integral Linearity Error -1 t 1/2 1 LSB
Integral Linearity Error, TMIN to TMAX tl LSB
Differential Linearity Error -3/4 tl/4 3/4 LSB
Differential Linearity Error, TMIN to TMAX t l/2 LSB
Gain Error Drift t10 ppm of FSRPC
Offset Drift t7 ppm of F SWT
Noise, 0.1 to 2 MHz Bandwidth 200 p.V rms
REFERENCE INPUT
Input Resistance 10 Mn
Voltage Range +5.5/-3.0 Volts
REFERENCE OUTPUT
Output Voltage 4.95 5.05 Volts
Temperature Coefficient t 15 ppmf'C
POWER REQUIREMENTS
Vcc 4.5 5.0 5.5 Volts
ICC 0. l 5 mA
VDD, Vss $11.4 $12.0 $12.6 Volts
loo 16 28 mA
Iss -28 - 15 IDA
Total Power 350 mW
ANALOG GROUND CURRENT' PER EACH OF 8 CHANNELS 1600 wh
MATCHING PERFORMANCE
Gain2 -5 t2.5 5 LSB
Offsets -4 i2 4 LSB
CROSSTALK
Analog (DC)' -90 dB
Digital (Transient)4 -60 dB
DYNAMIC PERFORMANCE (RL = 5 kn, Cs.. = 500 pF)
Slew Rate 3.0 V/ws
Settling Time to t1/2 LSB
Vour max to Vou-r min or Vova, min to Vovr max 8 us
POWER SUPPLY GAIN SENSITIVITY
11.4 V 5 Vol) s; 12.6 V t8 t25 ppm/% of IU,
-12.6 V s Vss s -11.4 V t8 t25 ppm/% of Vss
A075089
Parameter Min Typ Max Units
DIGITAL INPUTS
Vm 2.4 Volts
V11. 0 0.8 Volts
Im @ Vrs = Vcc --10 tl 10 WA
In. @ VIN = DGND -10 1 10 WA
DIGITAL OUTPUTS .
V0L @ ISINK = 1.6 mA 0.4 Volts
Voss @ [SOURCE = 0.5 mA 2.4 Volts
DIGITAL TIMINGS
Data Write Mode (Figure I)
Data Setup Time, IDSU 0 us
Address Setup Time, tasv 0 ns
Chip Enable-Write Time, to“, 0 ns
Write Pulse Width, tw 40 ns
Write-Chip Enable Time, twce 0 ns
Address Hold Time, tArs 0 ns
Data Hold Time, tors 1 ns
Data Readback Mode (Figure 2)
Address Setup Time, tasu 0 ns
Chip Enable-Read Time, kam 0 ns
Read Pulse Width, IR 35 us
Access Time from Read, tru, 150 ns
Data Bus Release Time, trum 40 ns
Read-Chip Enable Time, tRCE 0 ns
Address Hold Time, tArs 0 ns
Asynchronous Reset
Reset Pulse Width, tRs-r 80 ns
TEMPERATURE RANGE (T MIN, Tm) 0 +70 "C
'Analog ground current is the code dependent current flowing in each of the Gr pins.
Rain matching error is the largest difference in gain error between any two DACs in one package.
3Offset matching error is the largest difference in offset values between any two DACs in one package.
'See Definitions of Specirteations section.
'Reference level for timing measurements = 1.5 V.
See definitions of specifications later on in this data sheet.
Specifications subject to change without notice.
DATAINPUTS ( )(7777777
(00-011)
- tow" - ton l--
ADDRESS INPUTS ,
' tASU - "u,
"""-"1 f-'''"""""'
CHIP "1'le, t - twee e-
-uw'"-
“FEE it q l
(WR) ( I
Figure 1. Write Timing Diagram
D:\I n
ADDRESS I
(1teg ///ti, - Ili/l"
o/il-ii--" -eti_trrsF''-"""'
-- teen
Ti)-',', -----'-ts7-'- 'si-ti-"-"-""""""'
a): “E tneu
''l'll'l'fl ///////X ////
Figure 2. Readback Timing Diagram
AD75089
ABSOLUTE MAXIMUM RATINGS"
(Specifications apply to all grades except where noted)
*Strcsses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
Vcc to DGND or IOGND ............... o v to +7 v in the o rational section of this s . cation is m im lied.
Vos, to AGND ...................... o v to + 18 v 1s1ed,'1',,e,ra'1',1',''l1,, rating J',fd1s,,,sI,irt','tte2s, ser',:',''',',,',','; 2gt''T,,it
Vss to AGND ....................... --18 v to o v reliability.
G, to Vss ....................... 0 v to +26.4 v
AGND to DGND .................... -1 V to +1 v ORDERING GUIDE
AGND to VREFGND ..................... t 13.2 V .
AGND to VRETO-7 ...................... 113.2 v Output
VREFIN Input ........................ ka, to Vss Voltage Temperature Package
Digital Inputs ..................... -o.3 v to +7 v Model Range Range Option*
Analog Outputs AD75089JP :5 v 0°C to +70°c P-44A
........ Indefinite Shorts to Voc, VDD, Vss, and AGN D
Soldering Temperature ................ +300°C, 10 sec *P = Plastic Leaded Chip Carrier (PLCC) package.
Power Dissipation ....................... 1000 mW
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD75089 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
a .x'ha'ln In L.”
Iherour Vnzm
4.7;:Fxl/ 0.1 l
2 l TANTALuu ' " T
v +sv .12v camsc
REF . ANALOG "hm tl,
, - - SUPPLY q.TwF - 0.1..F
ANALOG - vm TANTALUM cam
GROUND Amp 42"
ANALOG " ttta
GROUND suspu ALL aanvm
LlNESC0NNEtrtED
Vm TO ANALOG oaouuo
, - 12-3" """!
m, " CATCH 12-arrmc - sr y
D10 " . v
m " as RETT
on tfrer
Br 1 12-8"
DATA no a - um: 1z-arr DAG -.. 40 van
BUS 05 23 I10 39 Vnm
BUFFER
tM ' 41 Voun
m a ' I " Vim
q - nvmrmu'r
m - ll I
a _ mum u v93:
m 2 r-V SHOWN ADT5089 "
Do t - 4 Votm
T Vour:
IOGND " ' V
o - 12-8" - 3 our:
urea 12-311mm . 9 Wm,
ce " osv LOGIC SUPPLY
OJIAF " VOUTO
csmmc mm Vnm
" GROUND common "
'roirEvTiia2mao
s--''-.-'
CONTROLBUS ADDRESS RESET
Figure 3. Recommended Circuit Schematic
REV. O
ADT5089
PIN CONFIGURATION
44-Pin PLCC Package
> > > > > > > > > ' >
vow, F st vim
VOLT" E'; '
'frerr u m Vom,
b%, m AGND
Gm, m M75089 ss A2
V“ iii, TOP VIEW E11 At
vm, " (tltntoSeaM E1 An
noun m E! CE
Vcc " 31 no
loom m a iii,
Mt m E5 RST
DEFINITIONS OF SPECIFICATIONS
INTEGRAL LINEARITY ERROR: Integral linearity error is
the maximum deviation of the actual DAC output from the
ideal analog output (a straight line drawn from --fU11 scale to
+full scale) for any digital input code.
MONOTONICITY: A DAC is said to be monotonic if the out-
put either increases or remains constant for increasing digital
inputs such that the output will always be a nondecreasing func-
tion of input. The AD75089 is monotonic over its full operating
temperature range.
DIFFERENTIAL LINEARITY ERROR: Monotonic behavior
requires that the differential linearity error be less than 1 LSB
over the temperature range of interest. Differential nonlinearity
is the measure of the variation in analog value, normalized to
full scale, associated with a 1 LSB change in digital input code.
For example, for a 10 V output span, a change of l LSB in digi-
tal input code should result in a 2.44 mV change in the analog
output (1 LSB = 10 V/4096 = 2.44 mV). If in actual use, how-
ever, a l LSB change in the input code results in a change of
only 0.61 mV (1/4 LSB) in analog output, the differential non-
linearity error would be -l.83 mV, or -3/4 LSB.
GAIN ERROR: DAC gain error is a measure of the difference
between the output span of an ideal DAC and an actual device.
SETTLING TIME: Settling time is the time required for the
output to reach and remain within a specified error band about
its final value, measured from the digital input transition.
PIN DESCRIPTIONS
Pin Name Description
1 VREFIN Reference Input
2 VREFOUT S V Reference Output
3 VREFGND Reference Ground
4 Vou-rs Analog Output 3
5 Vans Analog Return 3
6 sz Analog Return 2
7 Vova, Analog Output 2
8 Vou-n Analog Output 1
9 Vm, Analog Return 1
10 Vmo Analog Return 0
11 VOUTO Analog Output 0
12 Vss -12 V Analog Power Supply
13 Vor, + 12 V Analog Power Supply
14 DGND Digital Ground
15 Vcc +5 V Logic Power Supply
16 IOGND Bus Interface Ground
17 D11 Data Bus Bit ll (MSB)
18 D10 Data Bus Bit 10
19 D9 Data Bus Bit 9
20 D8 Data Bus Bit 8
21 D7 Data Bus Bit 7
22 D6 Data Bus Bit 6
23 D5 Data Bus Bit 5
24 D4 Data Bus Bit 4
25 D3 Data Bus Bit 3
26 D2 Data Bus Bit 2
27 D1 Data Bus Bit 1
28 D0 Data Bus Bit 0 (LSB)
29 RST Reset Input; Active High
30 ttr-R Write Input; Active Low
31 115 Read Input; Active Low
32 CE Chip Enable Input; Active Low
33 A0 Address Input Bit 0 (LSB)
34 A1 Address Input Bit 1
35 A2 Address Input Bit 2 (MSB)
36 AGND Analog Ground
37 vom Analog Output 7
38 ern Analog Return 7
39 Fur,, Analog Return 6
40 Vows Analog Output 6
41 Vows Analog Output 5
42 Vms Analog Return 5
43 VRET4 Analog Return 4
44 Vom-4 Analog Output 4
CROSSTALK: Crosstalk is the change in an output caused by a
change in one or more of the other inputs or outputs. Analog or
DC crosstalk is primarily caused by internal heating or ohmic
drops arising from changes in load current. Digital or transient
crosstalk is produced by capacitive coupling from the data
inputs or from other changing DAC outputs.
FULL-SCALE RANGE: FSR is 10 V for the t5 V range.
TRANSISTOR COUNT
The AD75089 contains 5,225 transistors.
